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llvm/lib/Target/AMDGPU
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Valery Pykhtin d1be85dd3c [AMDGPU] Refactor VOPC instruction TD definitions 
Differential Revision: https://reviews.llvm.org/D24546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281903 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 14:39:49 +00:00
..
AsmParser
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
Disassembler
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InstPrinter
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
MCTargetDesc
[AMDGPU] Fix s_branch with -1 offset
2016-09-19 10:20:55 +00:00
TargetInfo
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Utils
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
AMDGPU.h
AMDGPU: Split SILowerControlFlow into two pieces
2016-08-22 19:33:16 +00:00
AMDGPU.td
[AMDGPU] Assembler: Move disabled SDWA and DPP instruction into Disable asm variant
2016-09-12 14:42:43 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU/SI: Handle aliases in AMDGPUAlwaysInlinePass
2016-08-31 11:18:33 +00:00
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUAsmPrinter.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
AMDGPUCallingConv.td
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AMDGPUCallLowering.cpp
GlobalISel: implement simple function calls on AArch64.
2016-08-10 21:44:01 +00:00
AMDGPUCallLowering.h
GlobalISel: implement simple function calls on AArch64.
2016-08-10 21:44:01 +00:00
AMDGPUCodeGenPrepare.cpp
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
AMDGPU/R600: Remove macros
2016-08-13 01:43:46 +00:00
AMDGPUInstrInfo.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
AMDGPUInstructions.td
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
AMDGPUIntrinsicInfo.cpp
…
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td
…
AMDGPUISelDAGToDAG.cpp
AMDGPU: Fix broken FrameIndex handling
2016-09-17 16:09:55 +00:00
AMDGPUISelLowering.cpp
AMDGPU: Push bitcasts through build_vector
2016-09-17 15:44:16 +00:00
AMDGPUISelLowering.h
AMDGPU: Refactor kernel argument lowering
2016-09-16 21:53:00 +00:00
AMDGPUMachineFunction.cpp
…
AMDGPUMachineFunction.h
…
AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUPromoteAlloca.cpp
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPURuntimeMetadata.h
AMDGPU: Add hidden kernel arguments to runtime metadata
2016-09-07 17:44:00 +00:00
AMDGPUSubtarget.cpp
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
AMDGPUSubtarget.h
AMDGPU: Use i64 scalar compare instructions
2016-09-17 02:02:19 +00:00
AMDGPUTargetMachine.cpp
AMDGPU: Run LoadStoreVectorizer pass by default
2016-09-09 22:29:28 +00:00
AMDGPUTargetMachine.h
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AMDGPUTargetObjectFile.cpp
Move the Mangler from the AsmPrinter down to TLOF and clean up the
2016-09-16 07:33:15 +00:00
AMDGPUTargetObjectFile.h
Move the Mangler from the AsmPrinter down to TLOF and clean up the
2016-09-16 07:33:15 +00:00
AMDGPUTargetTransformInfo.cpp
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AMDGPUTargetTransformInfo.h
…
AMDILCFGStructurizer.cpp
CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
2016-08-24 01:52:46 +00:00
AMDKernelCodeT.h
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BUFInstructions.td
[AMDGPU] Refactor MUBUF/MTBUF instructions
2016-09-10 13:09:16 +00:00
CaymanInstructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
CIInstructions.td
[AMDGPU] Refactor MUBUF/MTBUF instructions
2016-09-10 13:09:16 +00:00
CMakeLists.txt
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
DSInstructions.td
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EvergreenInstructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
FLATInstructions.td
[AMDGPU] Refactor FLAT TD instructions
2016-09-05 11:22:51 +00:00
GCNHazardRecognizer.cpp
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GCNHazardRecognizer.h
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GCNSchedStrategy.cpp
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
GCNSchedStrategy.h
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
LLVMBuild.txt
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MIMGInstructions.td
AMDGPU/SI: MIMG TD Refactoring.
2016-09-01 17:54:54 +00:00
Processors.td
AMDGPU : Add XNACK feature to GPUs that support it.
2016-09-06 19:55:17 +00:00
R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
AMDGPU: Avoid looking for the DebugLoc in end()
2016-08-17 00:06:43 +00:00
R600Defines.h
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R600EmitClauseMarkers.cpp
Fix more dereferenced end() iterators after r278532
2016-08-13 01:12:49 +00:00
R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600FrameLowering.h
…
R600InstrFormats.td
AMDGPU/R600: Convert buffer id to VTX_READ input
2016-08-15 21:38:30 +00:00
R600InstrInfo.cpp
Finish renaming remaining analyzeBranch functions
2016-09-14 20:43:16 +00:00
R600InstrInfo.h
Finish renaming remaining analyzeBranch functions
2016-09-14 20:43:16 +00:00
R600Instructions.td
AMDGPU: Select mulhi 24-bit instructions
2016-08-27 01:32:27 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
AMDGPU: Refactor kernel argument lowering
2016-09-16 21:53:00 +00:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp
Use the range variant of find instead of unpacking begin/end
2016-08-11 22:21:41 +00:00
R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
AMDGPU: Allow some control flow intrinsics to be CSEd
2016-09-16 22:11:18 +00:00
SIDebuggerInsertNops.cpp
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SIDefines.h
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
…
SIFoldOperands.cpp
AMDGPU: Support folding FrameIndex operands
2016-09-14 15:51:33 +00:00
SIFrameLowering.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
SIFrameLowering.h
AMDGPU: Refactor frame lowering
2016-08-31 21:52:21 +00:00
SIInsertSkips.cpp
AMDGPU: Split SILowerControlFlow into two pieces
2016-08-22 19:33:16 +00:00
SIInsertWaits.cpp
…
SIInstrFormats.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00
SIInstrInfo.cpp
AMDGPU: Use i64 scalar compare instructions
2016-09-17 02:02:19 +00:00
SIInstrInfo.h
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SIInstrInfo.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00
SIInstructions.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00
SIIntrinsics.td
AMDGPU: Allow some control flow intrinsics to be CSEd
2016-09-16 22:11:18 +00:00
SIISelLowering.cpp
AMDGPU: Fix broken FrameIndex handling
2016-09-17 16:09:55 +00:00
SIISelLowering.h
AMDGPU: Fix broken FrameIndex handling
2016-09-17 16:09:55 +00:00
SILoadStoreOptimizer.cpp
SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused-variable]
2016-08-30 11:50:21 +00:00
SILowerControlFlow.cpp
AMDGPU: Remove register operand from si_mask_branch
2016-08-27 00:42:21 +00:00
SILowerI1Copies.cpp
…
SIMachineFunctionInfo.cpp
AMDGPU/SI: Add support for triples with the mesa3d operating system
2016-09-16 21:34:26 +00:00
SIMachineFunctionInfo.h
[AMDGPU] Wave and register controls
2016-09-06 20:22:28 +00:00
SIMachineScheduler.cpp
AMDGPU/SI: Use a better method for determining the largest pressure sets
2016-08-26 21:16:37 +00:00
SIMachineScheduler.h
…
SIRegisterInfo.cpp
AMDGPU: Rename spill operands to match real instruction
2016-09-17 15:52:37 +00:00
SIRegisterInfo.h
Remove unnecessary call to getAllocatableRegClass
2016-09-07 06:16:45 +00:00
SIRegisterInfo.td
AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.
2016-09-09 19:31:51 +00:00
SISchedule.td
AMDGPU/SI: Implement a custom MachineSchedStrategy
2016-08-29 19:42:52 +00:00
SIShrinkInstructions.cpp
AMDGPU: Use SOPK compare instructions
2016-09-16 21:41:16 +00:00
SITypeRewriter.cpp
…
SIWholeQuadMode.cpp
AMDGPU: Do not clobber SCC in SIWholeQuadMode
2016-09-12 16:25:20 +00:00
SMInstructions.td
[AMDGPU] Scalar Memory instructions TD refactoring
2016-09-01 09:56:47 +00:00
SOPInstructions.td
AMDGPU: Use i64 scalar compare instructions
2016-09-17 02:02:19 +00:00
VIInstrFormats.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00
VIInstructions.td
AMDGPU] Assembler: better support for immediate literals in assembler.
2016-09-09 14:44:04 +00:00
VOPCInstructions.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00
VOPInstructions.td
[AMDGPU] Refactor VOPC instruction TD definitions
2016-09-19 14:39:49 +00:00