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11e5e3bbe1
Disabling the pre-RA scheduler on large-work-group-registers causes it to be ~50% slower. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272860 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
2.1 KiB
LLVM
41 lines
2.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
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; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
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;
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; There is something about Tonga that causes this test to spend a lot of time
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; in the default register allocator.
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; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
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; is used to calculate the scratch load/store address. Make sure that this
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; mechanism works even when many spills happen.
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; Just test that it compiles successfully.
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; CHECK-LABEL: test
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define void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) {
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entry:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid
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%a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
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; mark most VGPR registers as used to increase register pressure
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call void asm sideeffect "", "~{VGPR4},~{VGPR8},~{VGPR12},~{VGPR16},~{VGPR20},~{VGPR24},~{VGPR28},~{VGPR32}" ()
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call void asm sideeffect "", "~{VGPR36},~{VGPR40},~{VGPR44},~{VGPR48},~{VGPR52},~{VGPR56},~{VGPR60},~{VGPR64}" ()
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call void asm sideeffect "", "~{VGPR68},~{VGPR72},~{VGPR76},~{VGPR80},~{VGPR84},~{VGPR88},~{VGPR92},~{VGPR96}" ()
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call void asm sideeffect "", "~{VGPR100},~{VGPR104},~{VGPR108},~{VGPR112},~{VGPR116},~{VGPR120},~{VGPR124},~{VGPR128}" ()
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call void asm sideeffect "", "~{VGPR132},~{VGPR136},~{VGPR140},~{VGPR144},~{VGPR148},~{VGPR152},~{VGPR156},~{VGPR160}" ()
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call void asm sideeffect "", "~{VGPR164},~{VGPR168},~{VGPR172},~{VGPR176},~{VGPR180},~{VGPR184},~{VGPR188},~{VGPR192}" ()
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call void asm sideeffect "", "~{VGPR196},~{VGPR200},~{VGPR204},~{VGPR208},~{VGPR212},~{VGPR216},~{VGPR220},~{VGPR224}" ()
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%outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid
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store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
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attributes #1 = { nounwind readnone }
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