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https://github.com/RPCSX/llvm.git
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a688c8eaae
There are some VectorShuffle Nodes in SDAG which can be selected to XXPERMDI Instruction, this patch recognizes them and does the selection to improve the PPC performance. Differential Revision: https://reviews.llvm.org/D33404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304298 91177308-0d34-0410-b5e6-96231b3b80d8
308 lines
11 KiB
LLVM
308 lines
11 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-BE
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; Possible LE ShuffleVector masks (Case 1):
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; ShuffleVector((vector double)a, (vector double)b, 3, 1)
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; ShuffleVector((vector double)a, (vector double)b, 2, 1)
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; ShuffleVector((vector double)a, (vector double)b, 3, 0)
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; ShuffleVector((vector double)a, (vector double)b, 2, 0)
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; which targets at:
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; xxpermdi a, b, 0
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; xxpermdi a, b, 1
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; xxpermdi a, b, 2
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; xxpermdi a, b, 3
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; Possible LE Swap ShuffleVector masks (Case 2):
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; ShuffleVector((vector double)a, (vector double)b, 1, 3)
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; ShuffleVector((vector double)a, (vector double)b, 0, 3)
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; ShuffleVector((vector double)a, (vector double)b, 1, 2)
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; ShuffleVector((vector double)a, (vector double)b, 0, 2)
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; which targets at:
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; xxpermdi b, a, 0
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; xxpermdi b, a, 1
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; xxpermdi b, a, 2
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; xxpermdi b, a, 3
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; Possible LE ShuffleVector masks when a == b, b is undef (Case 3):
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; ShuffleVector((vector double)a, (vector double)a, 1, 1)
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; ShuffleVector((vector double)a, (vector double)a, 0, 1)
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; ShuffleVector((vector double)a, (vector double)a, 1, 0)
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; ShuffleVector((vector double)a, (vector double)a, 0, 0)
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; which targets at:
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; xxpermdi a, a, 0
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; xxpermdi a, a, 1
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; xxpermdi a, a, 2
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; xxpermdi a, a, 3
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; Possible BE ShuffleVector masks (Case 4):
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; ShuffleVector((vector double)a, (vector double)b, 0, 2)
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; ShuffleVector((vector double)a, (vector double)b, 0, 3)
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; ShuffleVector((vector double)a, (vector double)b, 1, 2)
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; ShuffleVector((vector double)a, (vector double)b, 1, 3)
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; which targets at:
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; xxpermdi a, b, 0
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; xxpermdi a, b, 1
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; xxpermdi a, b, 2
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; xxpermdi a, b, 3
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; Possible BE Swap ShuffleVector masks (Case 5):
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; ShuffleVector((vector double)a, (vector double)b, 2, 0)
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; ShuffleVector((vector double)a, (vector double)b, 3, 0)
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; ShuffleVector((vector double)a, (vector double)b, 2, 1)
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; ShuffleVector((vector double)a, (vector double)b, 3, 1)
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; which targets at:
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; xxpermdi b, a, 0
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; xxpermdi b, a, 1
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; xxpermdi b, a, 2
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; xxpermdi b, a, 3
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; Possible BE ShuffleVector masks when a == b, b is undef (Case 6):
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; ShuffleVector((vector double)a, (vector double)a, 0, 0)
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; ShuffleVector((vector double)a, (vector double)a, 0, 1)
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; ShuffleVector((vector double)a, (vector double)a, 1, 0)
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; ShuffleVector((vector double)a, (vector double)a, 1, 1)
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; which targets at:
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; xxpermdi a, a, 0
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; xxpermdi a, a, 1
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; xxpermdi a, a, 2
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; xxpermdi a, a, 3
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define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_0
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; CHECK-LE: xxmrghd 34, 34, 35
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_1
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; CHECK-LE: xxpermdi 34, 34, 35, 1
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_2
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; CHECK-LE: xxpermdi 34, 34, 35, 2
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_3
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; CHECK-LE: xxmrgld 34, 34, 35
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_0
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; CHECK-LE: xxmrghd 34, 35, 34
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_1
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; CHECK-LE: xxpermdi 34, 35, 34, 1
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_2
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; CHECK-LE: xxpermdi 34, 35, 34, 2
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_3
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; CHECK-LE: xxmrgld 34, 35, 34
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_0
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; CHECK-LE: xxspltd 34, 34, 0
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_1
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; CHECK-LE: blr
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2
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; CHCECK-LE: xxswapd 34, 34
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}
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define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_3
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; CHECK-LE: xxspltd 34, 34, 1
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; CHECK-LE: blr
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}
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; Start testing BE
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define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_0
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; CHECK-BE: xxmrghd 34, 34, 35
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_1
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; CHECK-BE: xxpermdi 34, 34, 35, 1
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_2
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; CHECK-BE: xxpermdi 34, 34, 35, 2
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_3
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; CHECK-BE: xxmrgld 34, 34, 35
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_0
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; CHECK-BE: xxmrghd 34, 35, 34
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_1
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; CHECK-BE: xxpermdi 34, 35, 34, 1
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_2
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; CHECK-BE: xxpermdi 34, 35, 34, 2
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_3
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; CHECK-BE: xxmrgld 34, 35, 34
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_0
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; CHECK-BE: xxspltd 34, 34, 0
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_1
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; CHECK-BE: blr
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2
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; CHCECK-LE: xxswapd 34, 34
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}
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define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
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entry:
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%0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_3
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; CHECK-BE: xxspltd 34, 34, 1
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; CHECK-BE: blr
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}
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; More test cases to test different types of vector inputs
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define <16 x i8> @test_be_vec_xxpermdi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) {
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entry:
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%0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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ret <16 x i8> %0
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; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v16i8_v16i8
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; CHECK-BE: xxpermdi 34, 34, 35, 1
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; CHECK-BE: blr
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}
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define <8 x i16> @test_le_swap_vec_xxpermdi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) {
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entry:
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%0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v8i16_v8i16
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; CHECK-LE: xxpermdi 34, 35, 34, 1
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; CHECK-LE: blr
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}
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define <4 x i32> @test_le_swap_vec_xxpermdi_v4i32_v4i32(<4 x i32> %VA, <4 x i32> %VB) {
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entry:
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%0 = shufflevector <4 x i32> %VA, <4 x i32> %VB,<4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x i32> %0
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; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v4i32_v4i32
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; CHECK-LE: xxpermdi 34, 35, 34, 1
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; CHECK-LE: blr
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}
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