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Nemanja Ivanovic 35b282e0ac [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16 
As outlined in the PR, we didn't ensure that displacements for DQ-Form
instructions are multiples of 16. Since the instruction encoding encodes
a quad-word displacement, a sub-16 byte displacement is meaningless and
ends up being encoded incorrectly.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33671.

Differential Revision: https://reviews.llvm.org/D35007


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307934 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-13 18:17:10 +00:00
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[PowerPC] fix incorrect processor name for -mcpu in a test case
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[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
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[PowerPC] Eliminate integer compare instructions - vol. 3
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Summary
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[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
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[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
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[PowerPC] set optimization level in SelectionDAGISel
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[PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.
2017-05-31 18:20:17 +00:00
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[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
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[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.
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ppc64le-smallarg.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
ppc440-fp-basic.ll
…
ppc440-msync.ll
…
ppc-crbits-onoff.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
ppc-ctr-dead-code.ll
[PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.
2017-07-05 17:57:57 +00:00
ppc-empty-fs.ll
…
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
[PPC] Fix two bugs in frame lowering.
2017-07-11 16:42:20 +00:00
ppc-shrink-wrapping.ll
…
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-endian.ll
…
ppcf128sf.ll
…
ppcsoftops.ll
…
pr3711_widen_bit.ll
…
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
…
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
…
pr16556.ll
…
pr16573.ll
…
pr17168.ll
…
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
…
pr24216.ll
…
pr24546.ll
…
pr24636.ll
…
pr25157-peephole.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
pr25157.ll
…
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
pr27350.ll
…
pr28130.ll
…
pr28630.ll
…
pr30451.ll
…
pr30640.ll
…
pr30663.ll
…
pr30715.ll
…
pr31144.ll
…
pr32063.ll
…
pr32140.ll
…
pr33093.ll
[PPC CodeGen] Expand the bitreverse.i64 intrinsic.
2017-07-10 18:11:23 +00:00
PR33636.ll
Add the missing triple to the test case added as part of r307120.
2017-07-05 05:14:43 +00:00
PR33671.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
preinc-ld-sel-crash.ll
…
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
…
private.ll
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
…
qpx-bv-sint.ll
…
qpx-bv.ll
…
qpx-func-clobber.ll
…
qpx-load-splat.ll
…
qpx-load.ll
…
qpx-recipest.ll
…
qpx-rounding-ops.ll
…
qpx-s-load.ll
…
qpx-s-sel.ll
…
qpx-s-store.ll
…
qpx-sel.ll
…
qpx-split-vsetcc.ll
…
qpx-store.ll
…
qpx-unal-cons-lds.ll
…
qpx-unalperm.ll
…
quadint-return.ll
…
r31.ll
…
recipest.ll
…
reg-coalesce-simple.ll
…
reg-names.ll
…
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
remove-redundant-moves.ll
…
resolvefi-basereg.ll
…
resolvefi-disp.ll
…
restore-r30.ll
…
retaddr2.ll
…
retaddr.ll
…
return-val-i128.ll
…
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
…
rlwinm2.ll
…
rlwinm-zero-ext.ll
…
rlwinm.ll
…
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
save-bp.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
save-cr-ppc32svr4.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
save-crbp-ppc32svr4.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
scavenging.mir
RegScavenging: Add scavengeRegisterBackwards()
2017-06-17 02:08:18 +00:00
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
…
select_lt0.ll
…
select-addrRegRegOnly.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
select-cc.ll
…
select-i1-vs-i1.ll
…
selectiondag-extload-computeknownbits.ll
…
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
setcc-to-sub.ll
…
setcclike-or-comb.ll
…
seteq-0.ll
…
shift128.ll
CodeGen: Power: Add lowering for shifts of v1i128.
2017-05-17 21:54:41 +00:00
shift_mask.ll
…
shift-cmp.ll
…
shl_elim.ll
…
shl_sext.ll
…
sign_ext_inreg1.ll
…
sj-ctr-loop.ll
…
sjlj_no0x.ll
…
sjlj.ll
…
small-arguments.ll
…
spill-nor0.ll
…
splat-bug.ll
…
split-index-tc.ll
…
srl-mask.ll
…
stack-no-redzone.ll
…
stack-protector.ll
…
stack-realign.ll
…
stackmap-frame-setup.ll
…
stacksize.ll
…
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store-load-fwd.ll
…
store-update.ll
…
structsinmem.ll
…
structsinregs.ll
…
stubs.ll
…
stwu8.ll
…
stwu-gta.ll
…
stwux.ll
…
sub-bv-types.ll
…
subc.ll
…
subreg-postra-2.ll
…
subreg-postra.ll
…
subtract_from_imm.ll
…
svr4-redzone.ll
[PPC] Fix two bugs in frame lowering.
2017-07-11 16:42:20 +00:00
swaps-le-1.ll
…
swaps-le-2.ll
…
swaps-le-3.ll
…
swaps-le-4.ll
…
swaps-le-5.ll
…
swaps-le-6.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
swaps-le-7.ll
…
tail-dup-analyzable-fallthrough.ll
…
tail-dup-branch-to-fallthrough.ll
…
tail-dup-break-cfg.ll
…
tail-dup-layout.ll
…
tailcall1-64.ll
Specify complete target triple in test
2017-07-12 01:16:50 +00:00
tailcall1.ll
…
tailcall-string-rvo.ll
…
tailcallpic1.ll
…
testBitReverse.ll
[PPC CodeGen] Expand the bitreverse.i64 intrinsic.
2017-07-10 18:11:23 +00:00
testComparesieqsc.ll
…
testComparesieqsi.ll
…
testComparesieqsll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesieqss.ll
…
testComparesiequc.ll
…
testComparesiequi.ll
…
testComparesiequll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesiequs.ll
…
testComparesinesc.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesinesi.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesiness.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineuc.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineui.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineus.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testCompareslleqsc.ll
…
testCompareslleqsi.ll
…
testCompareslleqsll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testCompareslleqss.ll
…
testComparesllequc.ll
…
testComparesllequi.ll
…
testComparesllequll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesllequs.ll
…
thread-pointer.ll
…
tls_get_addr_clobbers.ll
…
tls_get_addr_fence1.mir
[PowerPC] fix potential verification error on __tls_get_addr
2017-06-29 14:13:38 +00:00
tls_get_addr_fence2.mir
[PowerPC] fix potential verification error on __tls_get_addr
2017-06-29 14:13:38 +00:00
tls_get_addr_stackframe.ll
…
tls-cse.ll
…
tls-pic.ll
…
tls-store2.ll
…
tls.ll
[PowerPC] set optimization level in SelectionDAGISel
2017-06-27 04:52:17 +00:00
toc-load-sched-bug.ll
…
trampoline.ll
…
unal4-std.ll
…
unal-altivec2.ll
…
unal-altivec-wint.ll
…
unal-altivec.ll
…
unal-vec-ldst.ll
…
unal-vec-negarith.ll
…
unaligned.ll
…
unsafe-math.ll
…
unwind-dw2-g.ll
…
unwind-dw2.ll
…
vaddsplat.ll
…
varargs-struct-float.ll
…
varargs.ll
…
variable_elem_vec_extracts.ll
…
vcmp-fold.ll
…
vec_abs.ll
…
vec_absd.ll
…
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
…
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
…
vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
…
vec_cmpd.ll
…
vec_constants.ll
…
vec_conv.ll
…
vec_extload.ll
…
vec_extract_p9.ll
[Power9] Exploit vector extract with variable index.
2017-07-05 16:55:00 +00:00
vec_fmuladd.ll
…
vec_fneg.ll
…
vec_insert.ll
…
vec_int_ext.ll
[Power9] Exploit vector integer extend instructions when indices aren't correct.
2017-07-05 16:00:38 +00:00
vec_mergeow.ll
…
vec_minmax.ll
…
vec_misaligned.ll
…
vec_mul_even_odd.ll
…
vec_mul.ll
…
vec_perf_shuffle.ll
…
vec_popcnt.ll
…
vec_revb.ll
[PowerPC] Match vec_revb builtins to P9 instructions.
2017-06-12 18:24:36 +00:00
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
…
vec_shift.ll
…
vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
…
vec_shuffle_p8vector.ll
…
vec_shuffle.ll
…
vec_sldwi.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
vec_splat_constant.ll
…
vec_splat.ll
…
vec_sqrt.ll
…
vec_urem_const.ll
…
vec_veqv_vnand_vorc.ll
…
vec_vrsave.ll
…
vec_xxpermdi.ll
[PowerPC] Fix a performance bug for PPC::XXPERMDI.
2017-05-31 13:09:57 +00:00
vec_zero.ll
…
vec-abi-align.ll
…
vec-asm-disabled.ll
…
vector-identity-shuffle.ll
…
vector-merge-store-fp-constants.ll
…
vector.ll
…
vperm-instcombine.ll
…
vperm-lowering.ll
…
vrsave-spill.ll
…
vrspill.ll
…
vsel-prom.ll
…
vsx_insert_extract_le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx_scalar_ld_st.ll
…
vsx_shuffle_le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-args.ll
…
VSX-DForm-Scalars.ll
…
vsx-div.ll
…
vsx-elementary-arith.ll
…
vsx-fma-m.ll
…
vsx-fma-mutate-trivial-copy.ll
…
vsx-fma-mutate-undef.ll
…
vsx-fma-sp.ll
…
vsx-infl-copy1.ll
…
vsx-infl-copy2.ll
…
vsx-ldst-builtin-le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-ldst.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-minmax.ll
…
vsx-p8.ll
…
vsx-p9.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
vsx-partword-int-loads-and-stores.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
vsx-recip-est.ll
…
vsx-self-copy.ll
…
vsx-spill-norwstore.ll
…
vsx-spill.ll
RegisterScavenging: Followup to r305625
2017-06-20 18:43:14 +00:00
vsx-vec-spill.ll
…
vsx-word-splats.ll
…
vsx.ll
RegisterScavenging: Followup to r305625
2017-06-20 18:43:14 +00:00
vtable-reloc.ll
…
weak_def_can_be_hidden.ll
…
xvcmpeqdp-v2f64.ll
…
xxleqv_xxlnand_xxlorc.ll
…
zero-not-run.ll
…
zext-free.ll
…