llvm/test/CodeGen/PowerPC/atomics-constant.ll
Hiroshi Inoue 1a33599c52 [PowerPC] fix potential verification errors on CFENCE8
This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs.

Differential Revision: https://reviews.llvm.org/D34208



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-15 16:51:28 +00:00

24 lines
604 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target triple = "powerpc64le-unknown-linux-gnu"
@a = constant i64 zeroinitializer
define i64 @foo() {
; CHECK-LABEL: foo:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: cmpd 7, 4, 4
; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr
entry:
%value = load atomic i64, i64* @a acquire, align 8
ret i64 %value
}