Artem Tamazov ea912da38b [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. ... Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268762 91177308-0d34-0410-b5e6-96231b3b80d8		2016-05-06 17:48:48 +00:00
..
buffer_wbinv1l_vol_vi.s	[AMDGPU] Fix missing assembler predicates.	2016-03-23 04:27:26 +00:00
ds-err.s	AMDGPU/SI: Assembler: Unify parsing/printing of operands.	2016-04-29 09:02:30 +00:00
ds.s	[AMDGPU] [llvm-mc] [VI] Fix encoding of LDS/GDS instructions.	2016-02-22 19:17:53 +00:00
flat-scratch.s	AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI	2015-12-21 18:44:27 +00:00
flat.s	[TableGen] AsmMatcher: Skip optional operands in the midle of instruction if it is not present	2016-03-01 08:34:43 +00:00
hsa_code_object_isa_noargs.s
hsa-text.s	AMDGPU/SI: Add support for AMD code object version 2.	2016-05-05 17:03:33 +00:00
hsa.s	AMDGPU/SI: Add support for AMD code object version 2.	2016-05-05 17:03:33 +00:00
lit.local.cfg
mimg.s	AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsics	2016-03-04 10:39:50 +00:00
mubuf.s	Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."	2016-04-29 17:04:50 +00:00
out-of-range-registers.s	AMDGPU: Fix asserts on invalid register ranges	2015-11-03 22:50:32 +00:00
reg-syntax-extra.s	Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."	2016-04-29 17:04:50 +00:00
smem.s	[AMDGPU] Assembler: SOP* instruction fixes	2016-03-14 11:17:19 +00:00
smrd-err.s	AMDGPU: Disallow s[102:103] on VI in assembler	2015-11-05 03:11:27 +00:00
smrd.s	Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."	2016-04-29 17:04:50 +00:00
sop1-err.s	AMDGPU: Disallow s[102:103] on VI in assembler	2015-11-05 03:11:27 +00:00
sop1.s	[AMDGPU] Assembler: Update SOP* tests	2016-03-15 07:44:57 +00:00
sop2.s	[AMDGPU] Assembler: Update SOP* tests	2016-03-15 07:44:57 +00:00
sopc.s	[AMDGPU] Assembler: Update SOP* tests	2016-03-15 07:44:57 +00:00
sopk-err.s	[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.	2016-04-27 15:17:03 +00:00
sopk.s	[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.	2016-04-27 15:17:03 +00:00
sopp-err.s	[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.	2016-05-06 17:48:48 +00:00
sopp.s	[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.	2016-05-06 17:48:48 +00:00
trap.s	[AMDGPU][llvm-mc] Add some missing testcases to trap.s	2016-04-29 17:41:44 +00:00
vop1.s	AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp	2015-10-06 15:57:53 +00:00
vop2-err.s	AMDGPU/SI: Fix input vcc operand for VOP2b instructions	2015-09-08 21:15:00 +00:00
vop2.s	[AMDGPU] Assembler: change v_madmk operands to have same order as mad.	2016-03-11 09:27:25 +00:00
vop3-errs.s	[AMDGPU][llvm-mc] Support for 32-bit inline literals	2016-02-22 19:17:56 +00:00
vop3-vop1-nosrc.s	AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp	2015-10-06 15:57:53 +00:00
vop3.s	[AMDGPU] Assembler: Support abs() syntax.	2016-03-09 11:03:21 +00:00
vop_dpp.s	[AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp.	2016-04-06 13:29:59 +00:00
vop_sdwa.s	[AMDGPU] Assembler: basic support for SDWA instructions	2016-04-26 13:33:56 +00:00
vopc-errs.s	AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions	2015-08-07 22:00:56 +00:00
vopc.s	AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions	2015-08-07 22:00:56 +00:00