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This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276747 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| MCDisassembler | ||
| MCParser | ||
| CMakeLists.txt | ||
| ConstantPools.cpp | ||
| ELFObjectWriter.cpp | ||
| LLVMBuild.txt | ||
| MachObjectWriter.cpp | ||
| MCAsmBackend.cpp | ||
| MCAsmInfo.cpp | ||
| MCAsmInfoCOFF.cpp | ||
| MCAsmInfoDarwin.cpp | ||
| MCAsmInfoELF.cpp | ||
| MCAsmStreamer.cpp | ||
| MCAssembler.cpp | ||
| MCCodeEmitter.cpp | ||
| MCCodeView.cpp | ||
| MCContext.cpp | ||
| MCDwarf.cpp | ||
| MCELFObjectTargetWriter.cpp | ||
| MCELFStreamer.cpp | ||
| MCExpr.cpp | ||
| MCFragment.cpp | ||
| MCInst.cpp | ||
| MCInstPrinter.cpp | ||
| MCInstrAnalysis.cpp | ||
| MCInstrDesc.cpp | ||
| MCLabel.cpp | ||
| MCLinkerOptimizationHint.cpp | ||
| MCMachObjectTargetWriter.cpp | ||
| MCMachOStreamer.cpp | ||
| MCNullStreamer.cpp | ||
| MCObjectFileInfo.cpp | ||
| MCObjectStreamer.cpp | ||
| MCObjectWriter.cpp | ||
| MCRegisterInfo.cpp | ||
| MCSchedule.cpp | ||
| MCSection.cpp | ||
| MCSectionCOFF.cpp | ||
| MCSectionELF.cpp | ||
| MCSectionMachO.cpp | ||
| MCStreamer.cpp | ||
| MCSubtargetInfo.cpp | ||
| MCSymbol.cpp | ||
| MCSymbolELF.cpp | ||
| MCTargetOptions.cpp | ||
| MCValue.cpp | ||
| MCWin64EH.cpp | ||
| MCWinEH.cpp | ||
| StringTableBuilder.cpp | ||
| SubtargetFeature.cpp | ||
| WinCOFFObjectWriter.cpp | ||
| WinCOFFStreamer.cpp | ||