llvm/test/CodeGen
James Molloy e03e2fa99d [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently
This recommits r281323, which was backed out for two reasons. One, a selfhost failure, and two, it apparently caused Chromium failures. Actually, the latter was a red herring. The log has expired from the former, but I suspect that was a red herring too (actually caused by another problematic patch of mine). Therefore reapplying, and will watch the bots like a hawk.

For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).

1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.
2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.
3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).
4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.

1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-03 10:18:20 +00:00
..
AArch64 GlobalISel: allow truncating pointer casts on AArch64. 2016-10-31 18:31:09 +00:00
AMDGPU AMDGPU: Cleanup some xfailed tests 2016-11-02 17:24:54 +00:00
ARM [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently 2016-11-03 10:18:20 +00:00
AVR
BPF
Generic
Hexagon [Hexagon] Remove registers coalesced in expand-condsets from live intervals 2016-11-02 17:59:54 +00:00
Inputs
Lanai
Mips [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass. 2016-10-27 15:50:36 +00:00
MIR AMDGPU: Allow additional implicit operands on MOVRELS instructions 2016-11-02 17:03:11 +00:00
MSP430
NVPTX [NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass. 2016-10-31 21:51:42 +00:00
PowerPC [PowerPC] Implement vector shift builtins - llvm portion 2016-11-01 09:42:32 +00:00
SPARC [Sparc][LEON] Test for FixFDIVSQRT erratum fix. 2016-11-01 14:23:37 +00:00
SystemZ
Thumb [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently 2016-11-03 10:18:20 +00:00
Thumb2 [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently 2016-11-03 10:18:20 +00:00
WebAssembly
WinEH
X86 [AVX-512] Use 'vnot' instead of 'not' in patterns involving vXi1 vectors. 2016-11-03 06:04:28 +00:00
XCore