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llvm/test/CodeGen/AMDGPU/set-dx10.ll
Matthias Braun 7adbf112c7 ScheduleDAGInstrs: Rework schedule graph builder. 
Re-comitting with a change that avoids undefined uses getting put into
the VRegUses list.

The new algorithm remembers the uses encountered while walking backwards
until a matching def is found. Contrary to the previous version this:
- Works without LiveIntervals being available
- Allows to increase the precision to subregisters/lanemasks
  (not used for now)

The changes in the AMDGPU tests are necessary because the R600 scheduler
is not stable with respect to the order of nodes in the ready queues.

Differential Revision: http://reviews.llvm.org/D9068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-04 01:51:19 +00:00

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LLVM
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; These tests check that floating point comparisons which are used by select
; to store integer true (-1) and false (0) values are lowered to one of the
; SET*DX10 instructions.
; CHECK: {{^}}fcmp_une_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp une float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_une_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp une float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_oeq_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_oeq_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oeq float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_oeq_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_oeq_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oeq float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_ogt_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_ogt_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ogt float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_ogt_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_ogt_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ogt float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_oge_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_oge_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oge float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_oge_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_oge_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp oge float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_ole_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_ole_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ole float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_ole_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_ole_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ole float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_olt_select_fptosi:
; CHECK: LSHR
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_olt_select_fptosi(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp olt float %in, 5.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
store i32 %3, i32 addrspace(1)* %out
ret void
}
; CHECK: {{^}}fcmp_olt_select_i32:
; CHECK: LSHR
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
; CHECK-NEXT: 1084227584(5.000000e+00)
define void @fcmp_olt_select_i32(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp olt float %in, 5.0
%1 = select i1 %0, i32 -1, i32 0
store i32 %1, i32 addrspace(1)* %out
ret void
}
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