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a070c921e5
This is a generic combine enabled via target hook to reduce icmp logic as discussed in: https://bugs.llvm.org/show_bug.cgi?id=32401 It's likely that other targets will want to enable this hook for scalar transforms, and there are probably other patterns that can use bitwise logic to reduce comparisons. Note that we are missing an IR canonicalization for these patterns, and we will probably prefer the pair-of-compares form in IR (shorter, more likely to fold). Differential Revision: https://reviews.llvm.org/D31483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299542 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.2 KiB
LLVM
75 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
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define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
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; CHECK-LABEL: ne_neg1_and_ne_zero:
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; CHECK: @ BB#0:
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; CHECK-NEXT: add r1, r0, #1
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: cmp r1, #1
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; CHECK-NEXT: movwhi r0, #1
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; CHECK-NEXT: bx lr
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%cmp1 = icmp ne i32 %x, -1
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%cmp2 = icmp ne i32 %x, 0
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
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define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK-LABEL: and_eq:
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; CHECK: @ BB#0:
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; CHECK-NEXT: eor r2, r2, r3
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; CHECK-NEXT: eor r0, r0, r1
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; CHECK-NEXT: orrs r0, r0, r2
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: movweq r0, #1
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; CHECK-NEXT: bx lr
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%cmp1 = icmp eq i32 %a, %b
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%cmp2 = icmp eq i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK-LABEL: or_ne:
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; CHECK: @ BB#0:
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; CHECK-NEXT: eor r2, r2, r3
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; CHECK-NEXT: eor r0, r0, r1
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; CHECK-NEXT: orrs r0, r0, r2
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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%cmp1 = icmp ne i32 %a, %b
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%cmp2 = icmp ne i32 %c, %d
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%or = or i1 %cmp1, %cmp2
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ret i1 %or
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}
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define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
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; CHECK-LABEL: and_eq_vec:
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; CHECK: @ BB#0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: vmov d19, r2, r3
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; CHECK-NEXT: add r12, sp, #40
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; CHECK-NEXT: add lr, sp, #8
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; CHECK-NEXT: vmov d18, r0, r1
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; CHECK-NEXT: vld1.64 {d16, d17}, [lr]
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; CHECK-NEXT: add r0, sp, #24
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; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
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; CHECK-NEXT: vceq.i32 q8, q9, q8
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; CHECK-NEXT: vld1.64 {d22, d23}, [r0]
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; CHECK-NEXT: vceq.i32 q9, q11, q10
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; CHECK-NEXT: vmovn.i32 d16, q8
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; CHECK-NEXT: vmovn.i32 d17, q9
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; CHECK-NEXT: vand d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: pop {r11, pc}
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%cmp1 = icmp eq <4 x i32> %a, %b
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%cmp2 = icmp eq <4 x i32> %c, %d
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%and = and <4 x i1> %cmp1, %cmp2
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ret <4 x i1> %and
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}
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