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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
3.5 KiB
LLVM
122 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vnegs8:
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;CHECK: vneg.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vnegs16:
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;CHECK: vneg.s16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vnegs32:
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;CHECK: vneg.s32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vnegf32:
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;CHECK: vneg.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: vnegQs8:
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;CHECK: vneg.s8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vnegQs16:
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;CHECK: vneg.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vnegQs32:
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;CHECK: vneg.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
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;CHECK-LABEL: vnegQf32:
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;CHECK: vneg.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <4 x float> %tmp2
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}
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define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vqnegs8:
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;CHECK: vqneg.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vqnegs16:
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;CHECK: vqneg.s16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vqnegs32:
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;CHECK: vqneg.s32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: vqnegQs8:
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;CHECK: vqneg.s8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqnegQs16:
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;CHECK: vqneg.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqnegQs32:
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;CHECK: vqneg.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone
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