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ed541fe200
llvm/test/CodeGen
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Daniel Sanders ed541fe200 [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 
Summary:
The -mcpu=mips16 option caused the Integrated Assembler to crash because
it couldn't figure out the architecture revision number to write to the
.MIPS.abiflags section. This CPU definition has been removed because, like
microMIPS, MIPS16 is an ASE to a base architecture.

Reviewers: vkalintiris

Subscribers: rkotler, llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13656



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-15 14:34:23 +00:00
..
AArch64 DAGCombiner: Combine extract_vector_elt from build_vector 2015-10-12 23:59:50 +00:00
AMDGPU DAGCombiner: Don't stop finding better chain on 2 aliases 2015-10-13 00:49:00 +00:00
ARM [ARM] Make sure we do not dereference the end iterator when accessing debug 2015-10-15 00:41:26 +00:00
BPF [bpf] Do not expand UNDEF SDNode during insn selection lowering 2015-10-08 18:52:40 +00:00
CPP Fix CPP Backend for GEP API changes for opaque pointer types 2015-09-08 18:42:29 +00:00
Generic Fix assert in X86 backend. 2015-10-09 20:10:14 +00:00
Hexagon [Hexagon] Add an early if-conversion pass 2015-10-06 15:49:14 +00:00
Inputs DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
Mips [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
MIR [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
MSP430
NVPTX [NVPTX] Let NVPTX backend detect integer min and max patterns. 2015-08-26 23:22:02 +00:00
PowerPC [MachO] Stop generating *coal* sections. 2015-10-15 05:28:38 +00:00
SPARC Fix assert when emitting llvm.pow.f86. 2015-10-09 21:36:19 +00:00
SystemZ [SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs 2015-10-10 07:20:23 +00:00
Thumb [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-10-05 14:49:54 +00:00
Thumb2 [ARM] Use correct half-precision functions in EABI mode 2015-10-07 16:58:49 +00:00
WebAssembly [WebAssembly] Rename floating-point operators to match their spec names. 2015-10-09 17:50:00 +00:00
WinEH [WinEH] Add CoreCLR EH table emission 2015-10-13 20:18:27 +00:00
X86 AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( shuffle packed values at 128-bit granularity ) 2015-10-15 13:29:07 +00:00
XCore [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00