llvm/MIR at f02821bc980c269c30e7f6e02ed03dfcabb3bd39 - llvm

RPCSX/llvm

mirror of https://github.com/RPCSX/llvm.git synced 2025-01-10 22:46:20 +00:00

History

Tom Stellard 6b339ba8ac AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer

Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D25526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284298 91177308-0d34-0410-b5e6-96231b3b80d8

2016-10-15 00:58:14 +00:00

AArch64

Add AArch64 unit tests

2016-10-12 09:00:44 +00:00

AMDGPU

AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer

2016-10-15 00:58:14 +00:00

ARM

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

Generic

MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it

2016-08-24 22:34:06 +00:00

Hexagon

[MIRParser] Parse lane masks for register live-ins

2016-10-12 21:06:45 +00:00

Lanai

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

Mips

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

NVPTX

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

PowerPC

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

X86

MIRParser: Rewrite register info initialization; mostly NFC

2016-10-11 03:13:01 +00:00