llvm/test/CodeGen/X86/pr16807.ll
Michael Liao dc8c044a9a Fix PR16807
- Lower signed division by constant powers-of-2 to target-independent
  DAG operators instead of target-dependent ones to support them better
  on targets where vector types are legal but shift operators on that
  types are illegal. E.g., on AVX, PSRAW is only available on <8 x i16>
  though <16 x i16> is a legal type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 17:51:02 +00:00

19 lines
449 B
LLVM

; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core-avx-i | FileCheck %s
define <16 x i16> @f_fu(<16 x i16> %bf) {
allocas:
%avg.i.i = sdiv <16 x i16> %bf, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
ret <16 x i16> %avg.i.i
}
; CHECK: f_fu
; CHECK: psraw
; CHECK: psrlw
; CHECK: paddw
; CHECK: psraw
; CHECK: psraw
; CHECK: psrlw
; CHECK: paddw
; CHECK: psraw
; CHECK: ret