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This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
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done
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done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.5 KiB
LLVM
43 lines
1.5 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -tailcallopt | FileCheck %s
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; FIXME: Win64 does not support byval.
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; Expect the entry point.
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; CHECK-LABEL: tailcaller:
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; Expect 2 rep;movs because of tail call byval lowering.
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; CHECK: rep;
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; CHECK: rep;
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; A sequence of copyto/copyfrom virtual registers is used to deal with byval
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; lowering appearing after moving arguments to registers. The following two
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; checks verify that the register allocator changes those sequences to direct
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; moves to argument register where it can (for registers that are not used in
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; byval lowering - not rsi, not rdi, not rcx).
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; Expect argument 4 to be moved directly to register edx.
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; CHECK: movl $7, %edx
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; Expect argument 6 to be moved directly to register r8.
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; CHECK: movl $17, %r8d
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; Expect not call but jmp to @tailcallee.
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; CHECK: jmp tailcallee
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; Expect the trailer.
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; CHECK: .size tailcaller
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%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
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i64, i64, i64, i64, i64, i64, i64, i64,
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i64, i64, i64, i64, i64, i64, i64, i64 }
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declare fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5)
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define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
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entry:
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%tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
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%tmp3 = load i64* %tmp2, align 8
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%tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
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ret i64 %tmp4
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}
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