Matt Arsenault f8e2c0ab06 AMDGPU: Use brev for materializing SGPR constants ...

This is already done with VGPR immediates and saves 4 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285765 91177308-0d34-0410-b5e6-96231b3b80d8

2016-11-01 23:14:20 +00:00

..

AArch64

GlobalISel: allow truncating pointer casts on AArch64.

2016-10-31 18:31:09 +00:00

AMDGPU

AMDGPU: Use brev for materializing SGPR constants

2016-11-01 23:14:20 +00:00

ARM

This is a 1 character fix for an ARM build attribute test (r284571): the

2016-11-01 15:59:37 +00:00

AVR

…

BPF

…

Generic

…

Hexagon

[Hexagon] Don't expand mux instructions with both sources identical

2016-10-31 15:45:09 +00:00

Inputs

…

Lanai

…

Mips

[mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass.

2016-10-27 15:50:36 +00:00

MIR

AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions

2016-10-28 23:53:48 +00:00

MSP430

…

NVPTX

[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.

2016-10-31 21:51:42 +00:00

PowerPC

[PowerPC] Implement vector shift builtins - llvm portion

2016-11-01 09:42:32 +00:00

SPARC

[Sparc][LEON] Test for FixFDIVSQRT erratum fix.

2016-11-01 14:23:37 +00:00

SystemZ

…

Thumb

…

Thumb2

[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables

2016-11-01 13:37:41 +00:00

WebAssembly

…

WinEH

…

X86

[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841)

2016-10-31 23:28:45 +00:00

XCore

…