Krzysztof Parzyszek 19cc1fb430 [Hexagon] Define certain aliases for vector instructions ... Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267901 91177308-0d34-0410-b5e6-96231b3b80d8		2016-04-28 16:43:16 +00:00
..
AArch64	MCParser: diagnose missing directional labels more clearly.	2016-04-11 19:50:46 +00:00
AMDGPU	Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."	2016-04-27 18:29:11 +00:00
ARM	Reapply: "ARM: put correct symbol index on indirect pointers in __thread_ptr.""	2016-04-26 18:29:16 +00:00
AsmParser	[LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.	2016-04-19 23:51:52 +00:00
COFF	CodeGen: Use PLT relocations for relative references to unnamed_addr functions.	2016-04-22 20:40:10 +00:00
Disassembler	[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.	2016-04-27 15:17:03 +00:00
ELF	[MC/ELF] Make the relaxation test more interesting.	2016-04-24 01:08:35 +00:00
Hexagon	[Hexagon] Define certain aliases for vector instructions	2016-04-28 16:43:16 +00:00
Lanai	[lanai] isBrImm should accept any non-constant immediate.	2016-03-31 17:58:55 +00:00
MachO	CodeGen: Use PLT relocations for relative references to unnamed_addr functions.	2016-04-22 20:40:10 +00:00
Markup
Mips	[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions	2016-04-27 11:31:44 +00:00
PowerPC	[PowerPC] Basic support for P9 byte comparison and count trailing zero insns	2016-04-13 18:51:18 +00:00
Sparc	Sparc: silently ignore .proc assembler directive	2016-03-28 14:00:11 +00:00
SystemZ	[SystemZ] Add SVC instruction	2016-04-11 14:35:39 +00:00
X86	[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.	2016-04-15 15:57:41 +00:00