Bob Wilson ffde080ae6 Convert VLD1 and VLD2 instructions to use pseudo-instructions until ... after regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8		2010-09-02 16:00:54 +00:00
..
Alpha	PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually	2010-08-01 21:13:28 +00:00
ARM	Convert VLD1 and VLD2 instructions to use pseudo-instructions until	2010-09-02 16:00:54 +00:00
Blackfin	Remove TargetInstrInfo::copyRegToReg entirely.	2010-07-11 17:01:17 +00:00
CBackend
CellSPU	Fix lowering of INSERT_VECTOR_ELT in SPU.	2010-08-29 12:41:50 +00:00
CPP
Generic	Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself	2010-07-27 18:02:18 +00:00
MBlaze	Split big test into multiple directories to cater to	2010-04-07 20:43:35 +00:00
Mips	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
MSP430	Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),	2010-05-01 12:52:34 +00:00
PIC16	Remove XFAIL for vg_leak as the leaks are fixed by 100601.	2010-04-07 07:06:48 +00:00
PowerPC	PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.	2010-08-02 00:18:19 +00:00
SPARC	Split big test into multiple directories to cater to	2010-04-07 20:43:35 +00:00
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Update test for 112609	2010-08-31 17:58:47 +00:00
Thumb2	temporarily revert r112664, it is causing a decoding conflict, and	2010-09-01 16:00:50 +00:00
X86	test/loop-strength-reduce4: Add explicit triplet for Win32 host.	2010-09-02 03:45:58 +00:00
XCore	Start function numbering at 0.	2010-04-17 16:29:15 +00:00