Mark Charney 841f7d71c6 VCVT{,T}{SD,SS}2SI: AVX instr made LIG. ... * SNB/IVB/HSW required VEX.L=0. BDW-onwards changed this to LIG. Matching the "current" behavior. * I could make a chip-based decode so that SNB/IVB/HSW XED chips require VEX.L=0, but as those chips get older this issue is less relevant. Change-Id: I2f0abc2c05ecb253f092c9d9aa0b6553fc08f011 (cherry picked from commit 6f513163e757d61624b428d29772a1d56497a1bd)		2017-05-01 12:16:04 -04:00
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avx-aes-isa.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-chips.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-fields.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-fma-isa.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-imm-enc.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-imm.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-isa-supp-enc.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-isa-supp.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-isa.txt	VCVT{,T}{SD,SS}2SI: AVX instr made LIG.	2017-05-01 12:16:04 -04:00
avx-movnt-store.txt	add NONTEMPORAL attribute to relevant instructions	2017-05-01 12:16:04 -04:00
avx-operand-width.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-pclmul-isa.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-pointer-width.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-reg-table.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-regs.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-spine.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-state-bits.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-vex-enc.txt	initial commit	2016-12-16 16:09:38 -05:00
avx-vex.txt	initial commit	2016-12-16 16:09:38 -05:00
cpuid.xed.txt	initial commit	2016-12-16 16:09:38 -05:00
files-fma.cfg	initial commit	2016-12-16 16:09:38 -05:00
files.cfg	initial commit	2016-12-16 16:09:38 -05:00