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Merge pull request #808 from negativeExponent/fds-audio-fix
fds_apu: Update mod/sweep emulation
This commit is contained in:
thor2016
+132
-60
@@ -335,18 +335,16 @@ static DECLFR(FDSRead4033) {
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/* Begin FDS sound */
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/* 2025-09-12 - negativeExponent
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Ported modulation/sweep logic from Mednafen NES
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*/
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#define FDSClock (1789772.7272727272727272 / 2)
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typedef struct {
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int64 cycles; // Cycles per PCM sample
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int64 count; // Cycle counter
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int64 envcount; // Envelope cycle counter
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uint32 b19shiftreg60;
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uint32 b24adder66;
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uint32 b24latch68;
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uint32 b17latch76;
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int32 clockcount; // Counter to divide frequency by 8.
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uint8 b8shiftreg88; // Modulation register.
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uint8 amplitude[2]; // Current amplitudes.
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uint8 speedo[2];
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uint8 mwcount;
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@@ -354,33 +352,53 @@ typedef struct {
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uint8 mwave[0x20]; // Modulation waveform
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uint8 cwave[0x40]; // Game-defined waveform(carrier)
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uint8 SPSG[0xB];
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uint32 cwave_freq; /* $4082 and lower 4 bits of $4083 */
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uint32 cwave_pos;
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uint32 mod_freq; /* $4086 and lower 4 bits of $4087 */
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uint32 mod_pos; /* Should be named "mwave_pos", but "mod_pos" distinguishes it more. */
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uint8 mod_disabled; /* Upper bit of $4087 */
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uint32 sweep_bias;
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int32 mod_out; /* output from modulator */
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uint32 sample_cache_out; /* Sample out cache, with volume, modulation, and others applied */
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} FDSSOUND;
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static FDSSOUND fdso;
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static const int bias_tab[8] = { 0, 1, 2, 4, 0, -4, -2, -1 };
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#define SPSG fdso.SPSG
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#define b19shiftreg60 fdso.b19shiftreg60
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#define b24adder66 fdso.b24adder66
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#define b24latch68 fdso.b24latch68
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#define b17latch76 fdso.b17latch76
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#define b8shiftreg88 fdso.b8shiftreg88
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#define clockcount fdso.clockcount
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#define amplitude fdso.amplitude
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#define speedo fdso.speedo
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#define cwave_freq fdso.cwave_freq
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#define cwave_pos fdso.cwave_pos
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#define mod_freq fdso.mod_freq
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#define mod_pos fdso.mod_pos
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#define mod_disabled fdso.mod_disabled
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#define sweep_bias fdso.sweep_bias
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void FDSSoundStateAdd(void) {
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AddExState(fdso.cwave, 64, 0, "WAVE");
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AddExState(fdso.mwave, 32, 0, "MWAV");
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AddExState(amplitude, 2, 0, "AMPL");
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AddExState(SPSG, 0xB, 0, "SPSG");
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AddExState(&b8shiftreg88, 1, 0, "B88");
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AddExState(&cwave_freq, 4, 1, "CFRQ");
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AddExState(&cwave_pos, 4, 1, "CPOS");
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AddExState(&clockcount, 4, 1, "CLOC");
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AddExState(&b19shiftreg60, 4, 1, "B60");
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AddExState(&b24adder66, 4, 1, "B66");
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AddExState(&b24latch68, 4, 1, "B68");
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AddExState(&b17latch76, 4, 1, "B76");
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AddExState(&mod_freq, 4, 1, "MFRQ");
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AddExState(&mod_pos, 4, 1, "MPOS");
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AddExState(&mod_disabled, 1, 1, "MDIS");
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AddExState(&sweep_bias, 4, 1, "BIAS");
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AddExState(&fdso.mod_out, 4, 1, "MOUT");
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AddExState(&fdso.sample_cache_out, 4, 1, "WOUT");
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}
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static DECLFR(FDSSRead) {
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@@ -405,14 +423,47 @@ static DECLFW(FDSSWrite) {
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if (V & 0x80)
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amplitude[(A & 0xF) >> 2] = V & 0x3F;
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break;
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case 0x7:
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b17latch76 = 0;
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SPSG[0x5] = 0;
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case 0x2:
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cwave_freq &= 0xFF00;
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cwave_freq |= V << 0;
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break;
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case 0x3:
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if (!(V & 0x80) && (SPSG[0x3] & 0x80))
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cwave_pos = 0;
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cwave_freq &= 0x00FF;
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cwave_freq |= (V & 0xF) << 8;
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break;
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case 0x5:
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sweep_bias = (V & 0x7F) << 4;
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mod_pos = 0;
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break;
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case 0x6:
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mod_freq &= 0xFF00;
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mod_freq |= V << 0;
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break;
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case 0x7:
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mod_freq &= 0x00FF;
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mod_freq |= (V & 0xF) << 8;
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mod_disabled = (bool)(V & 0x80);
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break;
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case 0x8:
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b17latch76 = 0;
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fdso.mwave[SPSG[0x5] & 0x1F] = V & 0x7;
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SPSG[0x5] = (SPSG[0x5] + 1) & 0x1F;
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if(mod_disabled) {
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int i;
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for(i = 0; i < 31; i++)
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fdso.mwave[i] = fdso.mwave[i + 1];
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fdso.mwave[0x1F] = bias_tab[V & 0x7];
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if((V & 0x7) == 0x4)
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fdso.mwave[0x1F] = 0x10;
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}
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break;
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}
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SPSG[A] = V;
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@@ -459,52 +510,73 @@ static DECLFW(FDSWaveWrite) {
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fdso.cwave[A & 0x3f] = V & 0x3F;
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}
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static int ta;
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static INLINE void ClockRise(void) {
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if (!clockcount) {
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ta++;
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b19shiftreg60 = (SPSG[0x2] | ((SPSG[0x3] & 0xF) << 8));
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b17latch76 = (SPSG[0x6] | ((SPSG[0x07] & 0xF) << 8)) + b17latch76;
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static int32 sign_x_to_s32(int n, int32 v) {
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return ((int32)((uint32)v << (32 - n)) >> (32 - n));
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}
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if (!(SPSG[0x7] & 0x80)) {
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int t = fdso.mwave[(b17latch76 >> 13) & 0x1F] & 7;
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int t2 = amplitude[1];
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int adj = 0;
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static void ClockMod(void) {
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if (!mod_disabled) {
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uint32 prev_mod_pos = mod_pos;
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int32 temp;
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if ((t & 3)) {
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if ((t & 4))
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adj -= (t2 * ((4 - (t & 3))));
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else
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adj += (t2 * ((t & 3)));
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}
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adj *= 2;
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if (adj > 0x7F) adj = 0x7F;
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if (adj < -0x80) adj = -0x80;
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b8shiftreg88 = 0x80 + adj;
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} else {
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b8shiftreg88 = 0x80;
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mod_pos += mod_freq;
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if ((mod_pos & (0x3F << 11)) != (prev_mod_pos & (0x3F << 11))) {
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const int32 mw = fdso.mwave[((mod_pos >> 16) & 0x1F)];
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sweep_bias = (sweep_bias + mw) & 0x7FF;
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if (mw == 0x10)
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sweep_bias = 0;
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}
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} else {
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b19shiftreg60 <<= 1;
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b8shiftreg88 >>= 1;
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temp = sign_x_to_s32(11, sweep_bias) * ((amplitude[1] > 0x20) ? 0x20 : amplitude[1]);
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// >> 4 or / 16? / 16 sounds better in Zelda...
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if (temp & 0x0F0) {
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temp /= 256;
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if (sweep_bias & 0x400)
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temp--;
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else
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temp += 2;
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} else
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temp /= 256;
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if (temp >= 194) {
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temp -= 258;
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}
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if (temp < -64) {
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temp += 256;
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}
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fdso.mod_out = temp;
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}
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b24adder66 = (b24latch68 + b19shiftreg60) & 0x1FFFFFF;
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}
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static INLINE void ClockFall(void) {
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if ((b8shiftreg88 & 1))
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b24latch68 = b24adder66;
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clockcount = (clockcount + 1) & 7;
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static void ClockCarrier(void) {
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int32 cur_cwave_freq;
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if (!mod_disabled) {
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cur_cwave_freq = (int32)(cwave_freq << 6) + (int32)cwave_freq * fdso.mod_out;
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if (cur_cwave_freq < 0)
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cur_cwave_freq = 0;
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} else
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cur_cwave_freq = cwave_freq << 6;
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cwave_pos += cur_cwave_freq;
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}
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static INLINE int32 FDSDoSound(void) {
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static int32 FDSDoSound(void) {
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int32 prev_cwave_pos = cwave_pos;
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fdso.count += fdso.cycles;
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if (fdso.count >= ((int64)1 << 40)) {
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dogk:
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fdso.count -= (int64)1 << 40;
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ClockRise();
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ClockFall();
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ClockMod();
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if (!(SPSG[0x3] & 0x80)) {
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ClockCarrier();
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}
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fdso.envcount--;
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if (fdso.envcount <= 0) {
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fdso.envcount += SPSG[0xA] * 3;
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@@ -513,12 +585,12 @@ static INLINE int32 FDSDoSound(void) {
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}
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if (fdso.count >= 32768) goto dogk;
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// Might need to emulate applying the amplitude to the waveform a bit better...
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{
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if ((cwave_pos ^ prev_cwave_pos) & (1 << 21)) {
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int k = amplitude[0];
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if (k > 0x20) k = 0x20;
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return (fdso.cwave[b24latch68 >> 19] * k) * 4 / ((SPSG[0x9] & 0x3) + 2);
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fdso.sample_cache_out = (fdso.cwave[(cwave_pos >> 21) & 0x3F] * k) * 4 / ((SPSG[0x9] & 0x3) + 2);
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}
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return fdso.sample_cache_out;
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}
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static int32 FBC = 0;
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