Commit Graph
4253 Commits
Author SHA1 Message Date
Matthew Callis 2bd312e602 Fix macOS build when show-sdk-platform-version fails 2026-09-13 15:51:16 +01:00
Giovanni Bajo af4cbb04f0 Align semantic of all RTC implementations:
* Initialize using the PC localtime
* Handle backward time warp by ignoring it
2026-09-06 12:34:34 +01:00
Giovanni Bajo dee49f55ae n64: avoid infinite loop at boot when time goes backward 2026-09-06 12:34:34 +01:00
Giovanni Bajo e6130f66e7 n64: speed up first boot of games with RTC
There is no reason to advance ~1.7 billion times from the epoch. We can
just initialize the RTC with the current time.
2026-09-06 12:34:34 +01:00
user 5de16c334d fc: implement PPU internal shift registers 2026-09-06 12:33:37 +01:00
ZengGengSen 7b51c8ab71 desktop-ui: guard hot-swappable port changes
Generic port menu callbacks could mutate scheduler threads and audio streams while the emulator worker was active. Route both disconnect and connect actions through one Program::Guard-protected helper and add a deterministic concurrent regression test.
2026-08-30 19:24:24 +01:00
ZengGengSen 66a53e2ed8 a26: advance save-state format to v141 2026-08-30 19:24:24 +01:00
ZengGengSen 24ab7df1e4 a26: add QuadTari controller support 2026-08-30 19:24:24 +01:00
ZengGengSen 8381b5ae05 a26: add AtariVox speech synthesis 2026-08-30 19:24:24 +01:00
ZengGengSen 0b87e304a0 a26: add SaveKey controller support 2026-08-30 19:24:24 +01:00
ZengGengSen 9092f818b9 a26: add KidVid Voice Module support 2026-08-30 19:24:24 +01:00
ZengGengSen a6869c924d a26: add MindLink controller support 2026-08-30 19:24:24 +01:00
ZengGengSen a144d3150a a26: add XG-1 light gun support 2026-08-30 19:24:24 +01:00
ZengGengSen 5ca93ea4d2 a26: add relative pointing controllers 2026-08-30 19:24:24 +01:00
ZengGengSen cc6b83228f a26: add extra-button controller support 2026-08-30 19:24:24 +01:00
ZengGengSen 4a71d93bb6 a26: add ROM-profiled phosphor persistence 2026-08-30 19:24:24 +01:00
ZengGengSen 751f615205 mia: add Atari 2600 cartridge database 2026-08-30 19:24:24 +01:00
ZengGengSen 39ca282454 a26: implement MovieCart streaming cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen f0c946b55e a26: implement ELF executable cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen 742cc93106 armv6m: add Cortex-M0 processor component 2026-08-30 19:24:24 +01:00
ZengGengSen 6495f9ea0f a26: implement FA2 cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen de92243f40 a26: implement EFF cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen 403c81a8cb a26: implement Chetiry cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen b255ec7f31 a26: add persistent cartridge storage 2026-08-30 19:24:24 +01:00
ZengGengSen 22af611ad5 a26: implement BUS cartridges 2026-08-30 19:24:24 +01:00
ZengGengSen 73d1382c61 a26: implement CDF cartridges 2026-08-30 19:24:24 +01:00
ZengGengSen 7f40b23068 a26: implement DPC+ cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen 99f2d442a7 a26: add Harmony cartridge runtime 2026-08-30 19:24:24 +01:00
ZengGengSen 6c629246bc a26: implement ordinary homebrew cartridge mappers 2026-08-30 19:24:24 +01:00
ZengGengSen bd4e506a19 a26: normalize supported cartridge dump layouts 2026-08-30 19:24:24 +01:00
ZengGengSen 0f15baebfd a26: implement DPC cartridge 2026-08-30 19:24:24 +01:00
ZengGengSen 6cf7770c4c a26: implement ordinary cartridge mappers 2026-08-30 19:24:24 +01:00
ZengGengSen cd3cc0087e a26: finalize cartridge board interface 2026-08-30 19:24:24 +01:00
ZengGengSen 5578e7ca89 a26: improve RIOT accuracy 2026-08-30 19:24:24 +01:00
ZengGengSen eac791413a a26: improve TIA and video accuracy 2026-08-30 19:24:24 +01:00
ZengGengSen 65e69f7159 a26: implement controller devices 2026-08-30 19:24:24 +01:00
ZengGengSen fb7544b169 a26: improve CPU bus timing 2026-08-30 19:24:24 +01:00
ZengGengSen a2d94ebba1 a26: initialize CPU interrupt tracer 2026-08-30 19:24:24 +01:00
Giovanni Bajo e4217366cf n64: report the up-to-date cycle counter when software reads COUNT
The CPU keeps a free-running cycle counter (COUNT) that guest software
reads to measure elapsed time. Internally the emulator does not update
that counter after every instruction: cycles are accumulated in a
running clock and only folded into COUNT when the CPU synchronizes with
the rest of the machine. Reading the register returned the folded value
only, ignoring any cycles accumulated since the last fold, so the value
handed back to software could be stale.

How stale depends on how often synchronization happens, which is why
this was mostly invisible with the interpreter and clearly wrong with
the recompiler. The interpreter synchronizes after every instruction, so
at most one instruction worth of cycles was missing. The recompiler
translates a whole run of instructions into a single unit of host code
and only folds the accumulated cycles at its boundaries, so several
consecutive reads of COUNT inside one such unit all returned the exact
same number. Code that reads the counter repeatedly to check that time
is moving forward would see it standing still; the test_timer_ticks test
in the libdragon test suite fails this way, with two successive readings
comparing equal.

Track how many cycles have already been folded into COUNT in a separate
countClock field, so the cycles accumulated since then can be recovered
at any point. Reading COUNT now folds those pending cycles in first,
which both returns an up-to-date value and evaluates the COMPARE match
at the same moment, keeping the register and the timer interrupt
consistent with each other. Writing COUNT or COMPARE folds them in as
well, so the pending cycles are attributed to the old value rather than
being added on top of the newly written one.
2026-08-26 23:38:43 +01:00
Giovanni Bajo 430def86f2 n64: fix timer interrupt never firing when COMPARE is zero
The CPU has a free-running cycle counter (COUNT) and a programmable
target register (COMPARE); an interrupt is raised whenever the counter
reaches the target. The check for that event was written as
"count < compare && count + elapsed >= compare", which assumes the
target always lies ahead of the current counter value in plain
arithmetic order. Since both registers are unsigned, that assumption
breaks as soon as the target is behind the counter, and it breaks
permanently when the target is exactly zero: no unsigned value is ever
less than zero, so the first half of the condition is never true and the
interrupt is never raised at all.

That is not a corner case in practice. The counter is only 32 bits wide
and wraps around roughly every 90 seconds, so software that wants to
maintain a wider timestamp typically arms the target at zero in order to
be notified on every wrap. libdragon did exactly this: timer_init()
programs COMPARE to zero and used the resulting interrupt to increment
the high half of a 64-bit tick counter. Under ares that interrupt never
arrived, so the high half was never incremented and timer_ticks() went
backwards across a wrap, which is what the test_timer_ticks test in the
libdragon test suite reports.

Replace the ordered comparison with a modular distance computed over the
counter's full range: the number of ticks remaining until the target is
(compare - count) truncated to the counter width, and the interrupt
fires when at least that many ticks elapse. This behaves identically
when the target is ahead of the counter and additionally handles the
wrap-around case, including a target of zero. The counter update, the
crossing check and the cycle profiling counters are moved together into
a new stepCount() helper so that a single implementation stays
authoritative.
2026-08-26 23:38:43 +01:00
Christopher Bonhage 4bfccfc3d5 nall/gdb: support QPassSignals
The client can now ask the stub to deliver chosen signals without stopping
or reporting (gdb sends QPassSignals automatically for signals configured
'handle <sig> nostop noprint pass'). Advertised in qSupported; the pass set
is client state, cleared on connect/disconnect like breakpoints.
2026-08-25 17:56:11 +01:00
invertego e3b53a6ec9 Merge commit '8a22cd8096c8ce366cccd44813b6210c2160ff29' 2026-08-24 02:23:23 -07:00
invertego 8a22cd8096 Squashed 'thirdparty/sljit/' changes from 666125ad6..de0259c7a
de0259c7a aarch64: set bit 14 for encoding [S|U]MULH (#370)
fdb8e8ce2 Fix build warnings by avoid function pointer to object pointer casts (#368)
67893de6c alpha: Add 64-bit JIT backend (#364)
f8d585b76 ppc: add SLJIT_BREAKPOINT (#367)
8c4127005 ubsan: avoid UB with << of a signed integer (#365)
3907e6900 Add zext.w support for riscv (#363)
d8c86ea66 regexJIT: guard dfa_transitions allocation against size overflow (#361)
d74aa8871 ppc64: Cast mask to sljit_sw in TEST_UI_IMM macro (#360)
d9902b1ba config: prevent aarch64_be from being autodetected (#345)
35ffee1a8 remove smartquotes in C comment (#353)
d034fb107 x86_64: fix near jump check (#352)
acf9f8f85 Move modular header includes outside `extern "C"` scope (#351)
68f01a538 Improve overflow check on RISCV (#350)
8d40e0306 riscv: make sure platform identification for RISCV is succint (#348)
8d0d05c58 Improve carry flag handling (#347)
a8d667f81 Improve signed/unsigned comparison of integers larger than a single register (#346)
c2598a9c2 netbsd: allow mprotect exception for PAX in wxalloc (#344)
3150656bb x86: avoid SIGILL in test25 for older CPUs (#343)
45f910b78 Improve sljit_emit_op2_shift on x86 (#342)
72f95ea56 Small emit_select improvements (#341)
31d2e5308 loongarch: Implement compare select (min/max) operation (#340)
15c64bb72 Implement compare select (min/max) operation on s390x (#339)
39754d085 Implement compare select (min/max) operation (#338)
b7442be1c loongarch: Implement sljit_emit_op2_shift (#337)
f621129c0 \Implement sljit_emit_op2_shift on s390x (#336)
6612fe51e Attempt some further improvements to -Wimplicit-fallthrough support (#331)
f9fd801f4 Implement sljit_emit_op2_shift (#335)
88d0ce0c0 Ensure that some log messages are written to the verbose stream (#333)
c57378efb Correct doc string for sljit_emit_jump (#332)
1bec7a611 config: add SLJIT_FALLTHROUGH to exempt -Wimplicit-fallthrough or C5262 (#330)
e281e199c Add more SLJIT_TMP_OPT_REG tests (#328)
a9e5ec6ae Introducing SLJIT_TMP_OPT_REG (#327)
d1fd994c1 Improve tmp register support (#326)
1fade852b aarch64: avoid -Wunused_parameter in older CPUs (#324)
1232958de Improve the description of sljit_emit_[f]select instructions
7779da89d Add test for dynamic code generation in buffers (#318)
8766c3abf Fix spelling in C code comments (#317)
2e7b6f2a7 Fix Docusaurus URL configuration (#316)
5e42fc93b Rework website (#310)
8b3029792 loongarch: improve immediate generator (#315)
1e66c9054 loongarch: Update toolchain and minor code style change (#314)
f9beb306b Fix sljit_emit_icall on Linux x86_64 (#313)
e93aa7c62 Fix test_buffer1 (#312)
98802d939 Improve jump/op_addr code generation on s390x (#309)
f0a7de957 Implement add address operation (#308)
4ec49e599 Improve CI (#307)
2dd451147 Fix test fails on loongarch (#306)
4c9e95004 Fix test fails on s390x (#305)
5aa4885ee Add more buffer tests (#304)
d7bf1f5b2 Implement read-only buffer allocation (#303)
994c013d6 Implement aligned labels on s390x
06e5b0ed5 Implement aligned labels (#302)
abbb179b1 Consolidate docs (#301)
a442875df Improve rewritable consts on s390x (#300)
f57890048 Improve rewritable consts (#299)
959c13542 loongarch: Fix sljit_emit_single and sljit_emit_op2cmpz (#298)
370630ec0 Implement emit_op2cmp operation (#296)
8bacc9aee Rename doc to docs (#297)
a96da7a86 Improve immediate generation on RISCV (#295)
2984ac7b1 Implement 16 bit branches for RISCV (#294)
d3cec21d9 Implement compressed arithmetic instructions for RISCV (#293)
85782cfb7 Implement load/store compressed instructions for RISCV (#291)
500037920 Implement several compressed instructions for RISCV (#290)
a969602da Better detection of available features on RISCV (#289)
2cdf4edee Change instruction size unit to 16 bit on RISCV (#288)
8481dde36 Enable -Wshadow warning, and rename shadowed variables (#286)
415ddeaea Fix sljit_emit_simd_sign RISCV (#284)
eb8ef1e81 Fix sljit_get_local_base (#282)
e51eabbfb Implement proper argument checks for float/simd registers (#280)
f7037aa15 Improve vector reg support on s390x (#279)
dcd3b10cd Improve vector reg support (#278)
a5ecc9c2e Comment else-s and endif-s in macros (#277)
2cf8a2495 Checks for separated vector registers (#275)
9dc3a4cf2 loongarch: Add SLJIT_UPPER_BITS_SIGN_EXTENDED (#276)
c0fd3d1ae Rename zeroed to zero extended
4b419b4bf Provide information about 32 bit operations on s390x
504672a9f Provide information about 32 bit operations register usage
20edfb055 CI: Update uraimo/run-on-arch-action to 2.8.1 (#274)
446e5c71f loongarch: Optimize jump maximum offset prediction & update action compiler (#273)

git-subtree-dir: thirdparty/sljit
git-subtree-split: de0259c7aaf36aa40cba8014f3fad3edde9307f9
2026-08-24 02:23:13 -07:00
invertego 3918992a41 n64: fix builds with ARES_UNITY_CORES=OFF 2026-08-24 09:37:50 +01:00
invertego f42f60d744 recompiler: fix floating-point issues impacting n64 core (#2611) 2026-08-24 10:00:48 +02:00
Giovanni Bajo fc83454343 n64: rename qnan/snan naming
Ares previous naming was following IEE754 but VR4300 uses an inverted
encoding for NaNs. This also shows that the CPU behavior is more logical.
2026-08-22 09:17:02 +01:00
ZengGengSen f23eb39ad5 a52: add v148 save-state support 2026-08-20 16:37:55 +01:00
ZengGengSen f67757e35e a52: add CX53 Trak-Ball controller 2026-08-20 16:37:55 +01:00
ZengGengSen 190afd8ad2 a52: implement POKEY and standard controller 2026-08-20 16:37:55 +01:00
ZengGengSen e2cdee5038 a52: implement GTIA hardware model 2026-08-20 16:37:55 +01:00