Update to bsnes v024 release.

This is an interim release between some major changes to the video mode support, which may take a long time to complete. It also fixes a bug with CGRAM access timing, re-adds the Sufami Turbo load menu, and adds support for the ST-010 coprocessor, used by F1 Race of Champions.
To load Sufami Turbo cartridges, stbios.bin must be placed inside a folder named bios in the bsnes folder. There is not currently a warning if this file is missing.

license.txt

@@ -1,26 +1,63 @@
-bsnes License:
---------------
-You are free to redistribute this software, and its source code; provided
-there is no charge for the software, nor any charge for the medium used to
-distribute the software. You are also free to use and modify the source code
-as you desire for personal use only. No publically-released derivative works
-of this source code are permitted without my permission, though I will likely
-grant you permission if you ask me. You must also abide by the terms of any
-additional source code licenses contained within this program.
+bsnes (TM) Open Source Reference License
+Copyright (C) 2004 - 2007 byuu
+All rights reserved
 
-Simple DirectMedia Layer License:
----------------------------------
-The Simple DirectMedia Layer (SDL for short) is a cross-platform library
-designed to make it easy to write multi-media software, such as games and
-emulators.
+1. Definitions
 
-The Simple DirectMedia Layer library source code is available from:
-http://www.libsdl.org/
+The terms "reproduce", "reproduction", "distribute" and "distribution" have the
+same meaning here as under U.S. copyright law.
 
-This library is distributed under the terms of the GNU LGPL:
-http://www.gnu.org/copyleft/lesser.html
+"The software" means this software package as a whole, including, but not
+limited to, this license, binaries, source code, documentation, and data.
 
-Licensing Exemptions:
----------------------
-Richard Bannister has asked for and received my permission to distribute
-a binary-only port of bsnes on the Mac OS X platform.
+"You" means the licensee of the software.
+
+"The licensor" means the copyright holder of the software, byuu.
+
+2. Grant of Rights
+
+Subject to the terms of this license, the licensor grants you a
+non-transferable, non-exclusive, worldwide, royalty-free copyright license to
+reproduce the software for non-commercial use only, provided the software
+remains unmodified, and there is no charge for the software itself, its' use,
+nor for the medium upon which the software is distributed. The reproduction of
+modified or derivative works of the software is strictly prohibited, except when
+transmitted solely to the licensor.
+
+3. Limitations
+
+This license does not grant you any rights to use the licensor's name, logo or
+trademarks.
+
+The software is provided "as is", and any express or implied warranties,
+including, but not limited to, the implied warranties of merchantability and
+fitness for a particular purpose are disclaimed. In no event shall the licensor
+be liable for any direct, indirect, incidental, special, exemplary, or
+consequential damages (including, but not limited to, procurement of substitute
+goods or services; loss of use, data, or profits; or business interruption)
+however caused and on any theory of liability, whether in contract, strict
+liability, or tort (including negligence or otherwise) arising in any way out of
+the use of the software, even if advised of the possibility of such damage.
+
+In the event that this license is determined to be invalid or unenforceable, the
+Grant of Rights will become null and void, and no rights shall be granted to the
+licensee, within the scope of U.S. copyright law.
+
+4. Exemptions
+
+The software includes the work of other copyright holders, which is licensed
+under different agreements, and exempt from this license. Below is a complete
+list of all such software, and their respective copyright holders and licenses.
+Further, respective source code files are labeled with their correct licensing
+information in the header. The lack of such a header indicates said file falls
+under the bsnes license.
+
+HQ2x Filter, author: MaxST, license: LGPL
+JMA, author: NSRT Team, license: GPL (*)
+libco, author: byuu, license: public domain
+libui, author: byuu, license: public domain
+NTSC Filter, author: blargg, license: LGPL
+S-DD1, author: Andreas Naive, license: public domain
+zlib, license: zlib license
+
+(*) bsnes has received an exemption from the copyright holder to use this work.

readme.txt

@@ -0,0 +1,97 @@
+bsnes
+Version 0.024
+Author: byuu
+
+--------
+General:
+--------
+bsnes is a Super Nintendo / Super Famicom emulator that began on
+October 14th, 2004.
+
+The latest version can be downloaded from:
+http://byuu.org/
+
+Please see license.txt for important licensing information.
+
+--------------
+Shortcut Keys:
+--------------
+Esc - Toggle menubar visibility
+F11 - Toggle fullscreen
+
+------------------
+Known Limitations:
+------------------
+S-CPU
+- Invalid DMA / HDMA transfers not fully emulated
+- Multiply / Divide register delays not implemented
+
+S-PPU
+- Uses scanline-based renderer. This is very inaccurate, but few (if any)
+  games rely on mid-scanline writes to function correctly
+- Does not support FirstSprite+Y priority
+- OAM / CGRAM accesses during active display not supported correctly
+- RTO flags are not calculated on frames that are skipped when frameskipping
+  is enabled. This provides a major speedup, however it will cause in issues
+  in games that test these flags, eg the SNES Test Program Electronics Test.
+  Turning frameskipping off will allow RTO flag calculation on every frame
+
+Hardware Bugs
+- S-CPU.r1 HDMA crashing bug not emulated
+- S-CPU<>S-SMP communication bus conflicts not emulated
+
+---------------------
+Unsupported Hardware:
+---------------------
+SA-1
+Coprocessor used in many popular games, including:
+- Dragon Ball Z Hyper Dimension
+- Kirby Super Star
+- Kirby's Dreamland 3
+- Marvelous
+- SD Gundam G-NEXT
+- Super Mario RPG
+
+Super FX
+Coprocessor used in many popular games, including:
+- Doom
+- Star Fox
+- Star Fox 2 (unreleased beta)
+- Super Mario World 2: Yoshi's Island
+
+SPC7110
+Coprocessor used only by the following games:
+- Far East of Eden Zero
+- Far East of Eden Zero: Shounen Jump no Shou
+- Momotarou Densetsu Happy
+- Super Power League 4
+
+DSP-3
+Coprocessor used only by SD Gundam GX
+
+DSP-4
+Coprocessor used only by Top Gear 3000
+
+ST011
+SETA DSP used only by Quick-move Shogi Match with Nidan Rank-holder Morita
+
+ST018
+SETA RISC CPU used only by Quick-move Shogi Match with Nidan Rank-holder Morita 2
+
+BS-X (Broadcast Satellite)
+Add-on unit sold only in Japan that played specially-made games that were
+downloaded via satellite
+
+BS-X Flashcart
+Flash cartridge used by BS-X, as well as some standalone games by Asciisoft
+
+Super Gameboy
+Cartridge passthrough used for playing Gameboy games
+
+------------------------
+Unsupported Controllers:
+------------------------
+Mouse
+Super Scope
+Justifier
+Multitap (4-port and 5-port)

src/Makefile

@@ -0,0 +1,312 @@
+######################
+### bsnes makefile ###
+######################
+
+ifeq ($(PLATFORM),)
+_null_: help
+endif
+
+##################################
+### platform-specific settings ###
+##################################
+
+ifeq ($(PLATFORM),x-gcc-lui)
+OS = unix
+CC = gcc
+CFLAGS = -O3 -fomit-frame-pointer -DPLATFORM_X -DCOMPILER_GCC -DPROCESSOR_X86 -DUI_LUI `pkg-config --cflags gtk+-2.0`
+AS = nasm
+ASFLAGS = -f elf
+LIBS = `pkg-config --libs gtk+-2.0` -lXv -lao
+LIBCO = libco_x86
+LIBUI = libui_gtk
+endif
+
+ifeq ($(PLATFORM),x-gcc-lui-x64)
+OS = unix
+CC = gcc
+CFLAGS = -O3 -fomit-frame-pointer -DPLATFORM_X -DCOMPILER_GCC -DPROCESSOR_X86_64 -DUI_LUI `pkg-config --cflags gtk+-2.0`
+AS = yasm
+ASFLAGS = -f elf64
+LIBS = `pkg-config --libs gtk+-2.0` -lXv -lao
+LIBCO = libco_x86_64
+LIBUI = libui_gtk
+endif
+
+ifeq ($(PLATFORM),win-visualc-lui)
+OS = win
+CC = cl
+CFLAGS = /nologo /wd4996 /O2 /EHsc /DPLATFORM_WIN /DCOMPILER_VISUALC /DPROCESSOR_X86 /DUI_LUI
+AS = nasm
+ASFLAGS = -f win32 -DWIN32
+LIBS = d3d9.lib ddraw.lib dsound.lib dinput8.lib dxguid.lib kernel32.lib user32.lib gdi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib
+LIBCO = libco_x86
+LIBUI = libui_win
+endif
+
+ifeq ($(PLATFORM),win-visualc-lui-pgi)
+OS = win
+CC = cl
+CFLAGS = /nologo /wd4996 /O2 /GL /EHsc /DPLATFORM_WIN /DCOMPILER_VISUALC /DPROCESSOR_X86 /DUI_LUI
+AS = nasm
+ASFLAGS = -f win32 -DWIN32
+LIBS = d3d9.lib ddraw.lib dsound.lib dinput8.lib dxguid.lib kernel32.lib user32.lib gdi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib
+LINK = /link /PGD:bsnes.pgd /LTCG:PGINSTRUMENT
+LIBCO = libco_x86
+LIBUI = libui_win
+endif
+
+ifeq ($(PLATFORM),win-visualc-lui-pgo)
+OS = win
+CC = cl
+CFLAGS = /nologo /wd4996 /O2 /GL /EHsc /DPLATFORM_WIN /DCOMPILER_VISUALC /DPROCESSOR_X86 /DUI_LUI
+AS = nasm
+ASFLAGS = -f win32 -DWIN32
+LIBS = d3d9.lib ddraw.lib dsound.lib dinput8.lib dxguid.lib kernel32.lib user32.lib gdi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib
+LINK = /link /PGD:bsnes.pgd /LTCG:PGOPTIMIZE
+LIBCO = libco_x86
+LIBUI = libui_win
+endif
+
+ifeq ($(PLATFORM),win-mingw-lui)
+OS = win
+CC = mingw32-gcc
+CFLAGS = -mwindows -O3 -fomit-frame-pointer -DPLATFORM_WIN -DCOMPILER_GCC -DPROCESSOR_X86 -DUI_LUI
+AS = nasm
+ASFLAGS = -f win32 -DWIN32
+LIBS = -ld3d9 -lddraw -ldsound -ldinput8 -ldxguid -luuid -lkernel32 -luser32 -lgdi32 -lshell32 -lwinmm -lcomdlg32 -lcomctl32
+LIBCO = libco_x86
+LIBUI = libui_win
+endif
+
+ifeq ($(PLATFORM),win-mingw4-lui)
+OS = win
+CC = mingw32-gcc-sjlj
+CFLAGS = -mwindows -O3 -fomit-frame-pointer -DPLATFORM_WIN -DCOMPILER_GCC -DPROCESSOR_X86 -DUI_LUI
+AS = nasm
+ASFLAGS = -f win32 -DWIN32
+LIBS = -ld3d9 -lddraw -ldsound -ldinput8 -ldxguid -luuid -lkernel32 -luser32 -lgdi32 -lshell32 -lwinmm -lcomdlg32 -lcomctl32
+LIBCO = libco_x86
+LIBUI = libui_win
+endif
+
+#####################################
+### compiler / assembler switches ###
+#####################################
+
+ifeq ($(CC),gcc)
+OUT = -obsnes
+CPP = g++
+OBJ = o
+CARGS = -c $< -o $@
+DEFINE = -D
+endif
+
+ifeq ($(CC),mingw32-gcc)
+OUT = -obsnes
+CPP = mingw32-g++
+OBJ = o
+CARGS = -c $< -o $@
+DEFINE = -D
+endif
+
+ifeq ($(CC),mingw32-gcc-sjlj)
+OUT = -obsnes
+CPP = mingw32-g++-sjlj
+OBJ = o
+CARGS = -c $< -o $@
+DEFINE = -D
+endif
+
+ifeq ($(CC),cl)
+OUT = /Febsnes
+CPP = cl
+OBJ = obj
+CARGS = /c $< /Fo$@
+DEFINE = /D
+endif
+
+ifeq ($(AS),nasm)
+ASARGS = $< -o $@
+endif
+
+ifeq ($(AS),yasm)
+ASARGS = $< -o $@
+endif
+
+###################
+### OS switches ###
+###################
+
+ifeq ($(OS),unix)
+RM = rm -f
+endif
+
+ifeq ($(OS),win)
+OUT := $(OUT).exe
+RM = del
+endif
+
+####################################
+### main target and dependencies ###
+####################################
+
+OBJECTS = main.$(OBJ) $(LIBCO).$(OBJ) $(LIBUI).$(OBJ) \
+  libstring.$(OBJ) \
+  reader.$(OBJ) cart.$(OBJ) cheat.$(OBJ) memory.$(OBJ) bmemory.$(OBJ) \
+  cpu.$(OBJ) scpu.$(OBJ) smp.$(OBJ) ssmp.$(OBJ) bdsp.$(OBJ) ppu.$(OBJ) \
+  bppu.$(OBJ) snes.$(OBJ) srtc.$(OBJ) sdd1.$(OBJ) c4.$(OBJ) dsp1.$(OBJ) \
+  dsp2.$(OBJ) obc1.$(OBJ) st010.$(OBJ)
+
+ifeq ($(GZIP_SUPPORT),true)
+  OBJECTS += adler32.$(OBJ) compress.$(OBJ) crc32.$(OBJ) deflate.$(OBJ) \
+    gzio.$(OBJ) inffast.$(OBJ) inflate.$(OBJ) inftrees.$(OBJ) ioapi.$(OBJ) \
+    trees.$(OBJ) unzip.$(OBJ) zip.$(OBJ) zutil.$(OBJ)
+  CFLAGS += $(DEFINE)GZIP_SUPPORT
+endif
+
+ifeq ($(JMA_SUPPORT),true)
+  OBJECTS += jma.$(OBJ) jcrc32.$(OBJ) lzmadec.$(OBJ) 7zlzma.$(OBJ) \
+    iiostrm.$(OBJ) inbyte.$(OBJ) lzma.$(OBJ) winout.$(OBJ)
+  CFLAGS += $(DEFINE)JMA_SUPPORT
+endif
+
+ifeq ($(OS),win)
+  ifeq ($(CC),cl)
+    OBJECTS += bsnes.res
+  endif
+endif
+
+all: $(OBJECTS)
+	$(CPP) $(OUT) $(CFLAGS) $(OBJECTS) $(LIBS) $(LINK)
+#	mt -nologo -manifest bsnes.exe.manifest -outputresource:bsnes.exe;1
+
+######################
+### implicit rules ###
+######################
+
+%.$(OBJ): $<
+	$(if $(filter %.asm,$<),$(AS) $(ASFLAGS) $(ASARGS))
+	$(if $(filter %.c,$<),$(CC) $(CFLAGS) $(CARGS))
+	$(if $(filter %.cpp,$<),$(CPP) $(CFLAGS) $(CARGS))
+
+#########################
+### platform-specific ###
+#########################
+main.$(OBJ): ui/main.cpp config/* ui/* ui/video/* ui/audio/* ui/input/* \
+ui/lui/* ui/lui/settings/* \
+ui/win/* ui/win/settings/* ui/win/debugger/*
+bsnes.res  : ui/bsnes.rc ; rc /r /fobsnes.res ui/bsnes.rc
+
+#############
+### libco ###
+#############
+libco_x86.$(OBJ)   : lib/libco_x86.asm lib/*
+libco_x86_64.$(OBJ): lib/libco_x86_64.asm lib/*
+
+#############
+### libui ###
+#############
+libui_gtk.$(OBJ): lib/libui_gtk.cpp lib/*
+libui_win.$(OBJ): lib/libui_win.cpp lib/*
+
+#################
+### libraries ###
+#################
+libstring.$(OBJ): lib/libstring.cpp lib/*
+
+#################
+### utilities ###
+#################
+reader.$(OBJ): reader/reader.cpp reader/*
+cart.$(OBJ)  : cart/cart.cpp cart/*
+cheat.$(OBJ) : cheat/cheat.cpp cheat/*
+
+##############
+### memory ###
+##############
+memory.$(OBJ) : memory/memory.cpp memory/*
+bmemory.$(OBJ): memory/bmemory/bmemory.cpp memory/bmemory/* memory/bmemory/mapper/*
+
+###########
+### cpu ###
+###########
+cpu.$(OBJ) : cpu/cpu.cpp cpu/*
+scpu.$(OBJ): cpu/scpu/scpu.cpp cpu/scpu/* cpu/scpu/core/* cpu/scpu/dma/* cpu/scpu/memory/* cpu/scpu/mmio/* cpu/scpu/timing/*
+
+###########
+### smp ###
+###########
+smp.$(OBJ) : smp/smp.cpp smp/*
+ssmp.$(OBJ): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/* smp/ssmp/timing/*
+
+###########
+### dsp ###
+###########
+adsp.$(OBJ): dsp/adsp/adsp.cpp dsp/adsp/*
+bdsp.$(OBJ): dsp/bdsp/bdsp.cpp dsp/bdsp/*
+
+###########
+### ppu ###
+###########
+ppu.$(OBJ) : ppu/ppu.cpp ppu/*
+bppu.$(OBJ): ppu/bppu/bppu.cpp ppu/bppu/*
+
+############
+### snes ###
+############
+snes.$(OBJ): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/* snes/input/*
+
+#####################
+### special chips ###
+#####################
+srtc.$(OBJ) : chip/srtc/srtc.cpp chip/srtc/*
+sdd1.$(OBJ) : chip/sdd1/sdd1.cpp chip/sdd1/*
+c4.$(OBJ)   : chip/c4/c4.cpp chip/c4/*
+dsp1.$(OBJ) : chip/dsp1/dsp1.cpp chip/dsp1/*
+dsp2.$(OBJ) : chip/dsp2/dsp2.cpp chip/dsp2/*
+obc1.$(OBJ) : chip/obc1/obc1.cpp chip/obc1/*
+st010.$(OBJ): chip/st010/st010.cpp chip/st010/*
+
+############
+### zlib ###
+############
+adler32.$(OBJ) : reader/zlib/adler32.c reader/zlib/*
+compress.$(OBJ): reader/zlib/compress.c reader/zlib/*
+crc32.$(OBJ)   : reader/zlib/crc32.c reader/zlib/*
+deflate.$(OBJ) : reader/zlib/deflate.c reader/zlib/*
+gzio.$(OBJ)    : reader/zlib/gzio.c reader/zlib/*
+inffast.$(OBJ) : reader/zlib/inffast.c reader/zlib/*
+inflate.$(OBJ) : reader/zlib/inflate.c reader/zlib/*
+inftrees.$(OBJ): reader/zlib/inftrees.c reader/zlib/*
+ioapi.$(OBJ)   : reader/zlib/ioapi.c reader/zlib/*
+trees.$(OBJ)   : reader/zlib/trees.c reader/zlib/*
+unzip.$(OBJ)   : reader/zlib/unzip.c reader/zlib/*
+zip.$(OBJ)     : reader/zlib/zip.c reader/zlib/*
+zutil.$(OBJ)   : reader/zlib/zutil.c reader/zlib/*
+
+###########
+### jma ###
+###########
+jma.$(OBJ)    : reader/jma/jma.cpp reader/jma/*
+jcrc32.$(OBJ) : reader/jma/jcrc32.cpp reader/jma/*
+lzmadec.$(OBJ): reader/jma/lzmadec.cpp reader/jma/*
+7zlzma.$(OBJ) : reader/jma/7zlzma.cpp reader/jma/*
+iiostrm.$(OBJ): reader/jma/iiostrm.cpp reader/jma/*
+inbyte.$(OBJ) : reader/jma/inbyte.cpp reader/jma/*
+lzma.$(OBJ)   : reader/jma/lzma.cpp reader/jma/*
+winout.$(OBJ) : reader/jma/winout.cpp reader/jma/*
+
+####################
+### misc targets ###
+####################
+clean:
+	-@$(RM) *.$(OBJ)
+	-@$(RM) *.res
+	-@$(RM) *.pgd
+	-@$(RM) *.pgc
+	-@$(RM) *.ilk
+	-@$(RM) *.pdb
+	-@$(RM) *.manifest
+
+help:
+	@echo Please specify which platform to compile for with PLATFORM=platform_name

src/apu/apu.h

@@ -1,33 +0,0 @@
-#include "apuregs.h"
-
-class APU {
-public:
-APURegs regs;
-static const uint8 iplrom[64];
-  enum {
-    FLAG_N = 0x80, FLAG_V = 0x40,
-    FLAG_P = 0x20, FLAG_B = 0x10,
-    FLAG_H = 0x08, FLAG_I = 0x04,
-    FLAG_Z = 0x02, FLAG_C = 0x01
-  };
-
-  virtual uint8  spcram_read (uint16 addr) = 0;
-  virtual void   spcram_write(uint16 addr, uint8 value) = 0;
-//$f4-$f7
-  virtual uint8  port_read (uint8 port) = 0;
-  virtual void   port_write(uint8 port, uint8 value) = 0;
-
-  virtual uint8 *get_spcram_handle() = 0;
-  virtual void   run() = 0;
-  virtual uint32 cycles_executed() = 0;
-  virtual void   power() = 0;
-  virtual void   reset() = 0;
-
-//debugging functions
-  virtual bool in_opcode();
-  void disassemble_opcode(char *output);
-  inline uint16 __relb(int8 offset, int op_len);
-
-  APU() {}
-  virtual ~APU() {}
-};

src/apu/apuregs.h

@@ -1,49 +0,0 @@
-class APURegFlags {
-private:
-  template <uint8 B> class bit {
-  public:
-  uint8 _b;
-    inline operator bool() { return (_b & B); }
-    inline bool operator =  (bool i) { (i) ? _b |= B : _b &= ~B; return (_b & B); }
-    inline bool operator &  (bool i) { if(i)_b &= ~B; return (_b & B); }
-    inline bool operator &= (bool i) { if(i)_b &= ~B; return (_b & B); }
-    inline bool operator |  (bool i) { if(i)_b |= B; return (_b & B); }
-    inline bool operator |= (bool i) { if(i)_b |= B; return (_b & B); }
-    inline bool operator ^  (bool i) { if(i)_b ^= B; return (_b & B); }
-    inline bool operator ^= (bool i) { if(i)_b ^= B; return (_b & B); }
-  };
-public:
-union {
-  uint8 _b;
-  bit<0x80> n;
-  bit<0x40> v;
-  bit<0x20> p;
-  bit<0x10> b;
-  bit<0x08> h;
-  bit<0x04> i;
-  bit<0x02> z;
-  bit<0x01> c;
-};
-
-  APURegFlags() { _b = 0; }
-  inline operator uint8() { return _b; }
-  inline unsigned operator  = (uint8 i) { _b  = i; return _b; }
-  inline unsigned operator &= (uint8 i) { _b &= i; return _b; }
-  inline unsigned operator |= (uint8 i) { _b |= i; return _b; }
-  inline unsigned operator ^= (uint8 i) { _b ^= i; return _b; }
-};
-
-class APURegs {
-public:
-uint16 pc;
-union {
-  uint16 ya;
-#ifdef ARCH_LSB
-  struct { uint8 a, y; };
-#else
-  struct { uint8 y, a; };
-#endif
-};
-uint8 x, sp;
-APURegFlags p;
-};

src/apu/bapu/bapu.h

@@ -1,24 +0,0 @@
-class bAPU : public APU {
-public:
-#include "core/core.h"
-#include "memory/memory.h"
-#include "timing/timing.h"
-
-struct {
-  uint8  cycle_pos, opcode;
-  uint32 cycles_executed;
-
-//$f1
-  bool   iplrom_enabled;
-
-//$f2
-  uint8  dsp_addr;
-} status;
-
-  inline void run();
-  inline void power();
-  inline void reset();
-
-  bAPU();
-  ~bAPU();
-};

src/apu/bapu/core/cc.bat

@@ -1,3 +0,0 @@
-cl /O2 /wd4996 bapugen.cpp
-@pause
-@del *.obj

src/apu/bapu/core/clean.bat

@@ -1,8 +0,0 @@
-@del *.exe
-@del op.h
-@del optable.cpp
-@del op_mov.cpp
-@del op_pc.cpp
-@del op_read.cpp
-@del op_rmw.cpp
-@del op_misc.cpp

src/apu/bapu/core/core.cpp

@@ -1,36 +0,0 @@
-#include "opfn.cpp"
-#include "op_mov.cpp"
-#include "op_pc.cpp"
-#include "op_read.cpp"
-#include "op_rmw.cpp"
-#include "op_misc.cpp"
-
-void bAPU::exec() {
-  if(status.cycle_pos) {
-    (this->*optbl[status.opcode])();
-    add_cycles(1);
-    if(status.cycle_pos == 0) {
-    #ifdef DEBUGGER
-      snes->notify(SNES::APU_EXEC_OPCODE_END);
-    #endif
-    }
-    return;
-  }
-
-//on first cycle?
-#ifdef DEBUGGER
-  snes->notify(SNES::APU_EXEC_OPCODE_BEGIN);
-#endif
-  status.opcode = op_read();
-  status.cycle_pos = 1;
-  add_cycles(1);
-}
-
-//only return true when we are on an opcode edge
-bool bAPU::in_opcode() {
-  return (status.cycle_pos != 0);
-}
-
-void bAPU::init_op_table() {
-  #include "optable.cpp"
-}

src/apu/bapu/core/core.h

@@ -1,25 +0,0 @@
-void (bAPU::*optbl[256])();
-uint16 dp, sp, rd, wr, bit, ya;
-  inline uint8  op_adc (uint8  x, uint8  y);
-  inline uint16 op_addw(uint16 x, uint16 y);
-  inline uint8  op_and (uint8  x, uint8  y);
-  inline uint8  op_cmp (uint8  x, uint8  y);
-  inline uint16 op_cmpw(uint16 x, uint16 y);
-  inline uint8  op_eor (uint8  x, uint8  y);
-  inline uint8  op_inc (uint8  x);
-  inline uint16 op_incw(uint16 x);
-  inline uint8  op_dec (uint8  x);
-  inline uint16 op_decw(uint16 x);
-  inline uint8  op_or  (uint8  x, uint8  y);
-  inline uint8  op_sbc (uint8  x, uint8  y);
-  inline uint16 op_subw(uint16 x, uint16 y);
-  inline uint8  op_asl (uint8  x);
-  inline uint8  op_lsr (uint8  x);
-  inline uint8  op_rol (uint8  x);
-  inline uint8  op_ror (uint8  x);
-
-  inline void   exec();
-  inline bool   in_opcode();
-  inline void   init_op_table();
-
-#include "op.h"

src/apu/bapu/core/op_misc.cpp

@@ -1,643 +0,0 @@
-void bAPU::op_nop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_sleep() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.pc--;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_stop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.pc--;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_xcn() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    regs.a = (regs.a >> 4) | (regs.a << 4);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_daa() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    if(regs.p.c || (regs.a) > 0x99) {
-      regs.a += 0x60;
-      regs.p.c = 1;
-    }
-    if(regs.p.h || (regs.a & 15) > 0x09) {
-      regs.a += 0x06;
-    }
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_das() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    if(!regs.p.c || (regs.a) > 0x99) {
-      regs.a -= 0x60;
-      regs.p.c = 0;
-    }
-    if(!regs.p.h || (regs.a & 15) > 0x09) {
-      regs.a -= 0x06;
-    }
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clrc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.p.c = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clrp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.p.p = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_setc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.p.c = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_setp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.p.p = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clrv() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.p.v = 0;
-    regs.p.h = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_notc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.p.c ^= 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_ei() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.p.i = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_di() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.p.i = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set0_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x01;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr0_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x01;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set1_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x02;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr1_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x02;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set2_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x04;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr2_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x04;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set3_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x08;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr3_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x08;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set4_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x10;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr4_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x10;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set5_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x20;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr5_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x20;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set6_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x40;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr6_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x40;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_set7_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |=  0x80;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_clr7_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd &= ~0x80;
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_tset_addr_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    regs.p.n = !!((rd & regs.a) & 0x80);
-    regs.p.z = ((rd & regs.a) == 0);
-    rd |= regs.a;
-    } break;
-  case 5: {
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_tclr_addr_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    regs.p.n = !!((rd & regs.a) & 0x80);
-    regs.p.z = ((rd & regs.a) == 0);
-    rd &=~ regs.a;
-    } break;
-  case 5: {
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_push_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    stack_write(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_push_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    stack_write(regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_push_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    stack_write(regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_push_p() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    stack_write(regs.p);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_pop_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.a = stack_read();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_pop_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.x = stack_read();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_pop_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.y = stack_read();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_pop_p() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.p = stack_read();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mul_ya() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    } break;
-  case 5: {
-    } break;
-  case 6: {
-    } break;
-  case 7: {
-    } break;
-  case 8: {
-    ya = regs.y * regs.a;
-    regs.a = ya;
-    regs.y = ya >> 8;
-  //result is set based on y (high-byte) only
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_div_ya_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    } break;
-  case 5: {
-    } break;
-  case 6: {
-    } break;
-  case 7: {
-    } break;
-  case 8: {
-    } break;
-  case 9: {
-    } break;
-  case 10: {
-    } break;
-  case 11: {
-    ya = regs.ya;
-  //overflow set if quotient >= 256
-    regs.p.v = !!(regs.y >= regs.x);
-    regs.p.h = !!((regs.y & 15) >= (regs.x & 15));
-    if(regs.y < (regs.x << 1)) {
-    //if quotient is <= 511 (will fit into 9-bit result)
-      regs.a = ya / regs.x;
-      regs.y = ya % regs.x;
-    } else {
-    //otherwise, the quotient won't fit into regs.p.v + regs.a
-    //this emulates the odd behavior of the SPC700 in this case
-      regs.a = 255    - (ya - (regs.x << 9)) / (256 - regs.x);
-      regs.y = regs.x + (ya - (regs.x << 9)) % (256 - regs.x);
-    }
-  //result is set based on a (quotient) only
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/apu/bapu/core/op_mov.b

@@ -1,207 +0,0 @@
-mov_a_x(0x7d, a, x),
-mov_a_y(0xdd, a, y),
-mov_x_a(0x5d, x, a),
-mov_y_a(0xfd, y, a),
-mov_x_sp(0x9d, x, sp),
-mov_sp_x(0xbd, sp, x) {
-1:regs.$1 = regs.$2;
-  regs.p.n = !!(regs.$1 & 0x80);
-  regs.p.z = (regs.$1 == 0);
-}
-
-mov_a_const(0xe8, a),
-mov_x_const(0xcd, x),
-mov_y_const(0x8d, y) {
-1:regs.$1 = op_read();
-  regs.p.n = !!(regs.$1 & 0x80);
-  regs.p.z = (regs.$1 == 0);
-}
-
-mov_a_ix(0xe6) {
-1:
-2:regs.a = op_read(OPMODE_DP, regs.x);
-  regs.p.n = !!(regs.a & 0x80);
-  regs.p.z = (regs.a == 0);
-}
-
-mov_a_ixinc(0xbf) {
-1:
-2:
-3:regs.a = op_read(OPMODE_DP, regs.x++);
-  regs.p.n = !!(regs.a & 0x80);
-  regs.p.z = (regs.a == 0);
-}
-
-mov_a_dp(0xe4, a),
-mov_x_dp(0xf8, x),
-mov_y_dp(0xeb, y) {
-1:sp = op_read();
-2:regs.$1 = op_read(OPMODE_DP, sp);
-  regs.p.n = !!(regs.$1 & 0x80);
-  regs.p.z = (regs.$1 == 0);
-}
-
-mov_a_dpx(0xf4, a, x),
-mov_x_dpy(0xf9, x, y),
-mov_y_dpx(0xfb, y, x) {
-1:sp = op_read();
-2:
-3:regs.$1 = op_read(OPMODE_DP, sp + regs.$2);
-  regs.p.n = !!(regs.$1 & 0x80);
-  regs.p.z = (regs.$1 == 0);
-}
-
-mov_a_addr(0xe5, a),
-mov_x_addr(0xe9, x),
-mov_y_addr(0xec, y) {
-1:sp  = op_read();
-2:sp |= op_read() << 8;
-3:regs.$1 = op_read(OPMODE_ADDR, sp);
-  regs.p.n = !!(regs.$1 & 0x80);
-  regs.p.z = (regs.$1 == 0);
-}
-
-mov_a_addrx(0xf5, x),
-mov_a_addry(0xf6, y) {
-1:sp  = op_read();
-2:sp |= op_read() << 8;
-3:
-4:regs.a = op_read(OPMODE_ADDR, sp + regs.$1);
-  regs.p.n = !!(regs.a & 0x80);
-  regs.p.z = (regs.a == 0);
-}
-
-mov_a_idpx(0xe7) {
-1:dp = op_read() + regs.x;
-2:
-3:sp  = op_read(OPMODE_DP, dp);
-4:sp |= op_read(OPMODE_DP, dp + 1) << 8;
-5:regs.a = op_read(OPMODE_ADDR, sp);
-  regs.p.n = !!(regs.a & 0x80);
-  regs.p.z = (regs.a == 0);
-}
-
-mov_a_idpy(0xf7) {
-1:dp = op_read();
-2:
-3:sp  = op_read(OPMODE_DP, dp);
-4:sp |= op_read(OPMODE_DP, dp + 1) << 8;
-5:regs.a = op_read(OPMODE_ADDR, sp + regs.y);
-  regs.p.n = !!(regs.a & 0x80);
-  regs.p.z = (regs.a == 0);
-}
-
-mov_dp_dp(0xfa) {
-1:sp = op_read();
-2:dp = op_read();
-3:rd = op_read(OPMODE_DP, sp);
-4:op_write(OPMODE_DP, dp, rd);
-}
-
-mov_dp_const(0x8f) {
-1:rd = op_read();
-2:dp = op_read();
-3:
-4:op_write(OPMODE_DP, dp, rd);
-}
-
-mov_ix_a(0xc6) {
-1:
-2:
-3:op_write(OPMODE_DP, regs.x, regs.a);
-}
-
-mov_ixinc_a(0xaf) {
-1:
-2:
-3:op_write(OPMODE_DP, regs.x++, regs.a);
-}
-
-mov_dp_a(0xc4, a),
-mov_dp_x(0xd8, x),
-mov_dp_y(0xcb, y) {
-1:dp = op_read();
-2:
-3:op_write(OPMODE_DP, dp, regs.$1);
-}
-
-mov_dpx_a(0xd4, x, a),
-mov_dpy_x(0xd9, y, x),
-mov_dpx_y(0xdb, x, y) {
-1:dp = op_read();
-2:
-3:
-4:op_write(OPMODE_DP, dp + regs.$1, regs.$2);
-}
-
-mov_addr_a(0xc5, a),
-mov_addr_x(0xc9, x),
-mov_addr_y(0xcc, y) {
-1:dp  = op_read();
-2:dp |= op_read() << 8;
-3:
-4:op_write(OPMODE_ADDR, dp, regs.$1);
-}
-
-mov_addrx_a(0xd5, x),
-mov_addry_a(0xd6, y) {
-1:dp  = op_read();
-2:dp |= op_read() << 8;
-3:
-4:
-5:op_write(OPMODE_ADDR, dp + regs.$1, regs.a);
-}
-
-mov_idpx_a(0xc7) {
-1:sp = op_read() + regs.x;
-2:
-3:dp  = op_read(OPMODE_DP, sp);
-4:dp |= op_read(OPMODE_DP, sp + 1) << 8;
-5:
-6:op_write(OPMODE_ADDR, dp, regs.a);
-}
-
-mov_idpy_a(0xd7) {
-1:sp = op_read();
-2:
-3:dp  = op_read(OPMODE_DP, sp);
-4:dp |= op_read(OPMODE_DP, sp + 1) << 8;
-5:
-6:op_write(OPMODE_ADDR, dp + regs.y, regs.a);
-}
-
-movw_ya_dp(0xba) {
-1:sp = op_read();
-2:
-3:regs.a = op_read(OPMODE_DP, sp);
-4:regs.y = op_read(OPMODE_DP, sp + 1);
-  regs.p.n = !!(regs.ya & 0x8000);
-  regs.p.z = (regs.ya == 0);
-}
-
-movw_dp_ya(0xda) {
-1:dp = op_read();
-2:
-3:op_write(OPMODE_DP, dp,     regs.a);
-4:op_write(OPMODE_DP, dp + 1, regs.y);
-}
-
-mov1_c_bit(0xaa) {
-1:sp  = op_read();
-2:sp |= op_read() << 8;
-3:bit = sp >> 13;
-  sp &= 0x1fff;
-  rd = op_read(OPMODE_ADDR, sp);
-  regs.p.c = !!(rd & (1 << bit));
-}
-
-mov1_bit_c(0xca) {
-1:dp  = op_read();
-2:dp |= op_read() << 8;
-3:bit = dp >> 13;
-  dp &= 0x1fff;
-  rd = op_read(OPMODE_ADDR, dp);
-  if(regs.p.c)rd |=  (1 << bit);
-  else        rd &= ~(1 << bit);
-4:op_write(OPMODE_ADDR, dp, rd);
-}

src/apu/bapu/core/op_mov.cpp

@@ -1,710 +0,0 @@
-void bAPU::op_mov_a_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = regs.x;
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = regs.y;
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.x = regs.a;
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_y_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.y = regs.a;
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_sp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.x = regs.sp;
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_sp_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.sp = regs.x;
-    regs.p.n = !!(regs.sp & 0x80);
-    regs.p.z = (regs.sp == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_const() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_read();
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_const() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.x = op_read();
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_y_const() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.y = op_read();
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_ix() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    regs.a = op_read(OPMODE_DP, regs.x);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_ixinc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.a = op_read(OPMODE_DP, regs.x++);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    regs.a = op_read(OPMODE_DP, sp);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    regs.x = op_read(OPMODE_DP, sp);
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_y_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    regs.y = op_read(OPMODE_DP, sp);
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.a = op_read(OPMODE_DP, sp + regs.x);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_dpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.x = op_read(OPMODE_DP, sp + regs.y);
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_y_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.y = op_read(OPMODE_DP, sp + regs.x);
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    regs.a = op_read(OPMODE_ADDR, sp);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_x_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    regs.x = op_read(OPMODE_ADDR, sp);
-    regs.p.n = !!(regs.x & 0x80);
-    regs.p.z = (regs.x == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_y_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    regs.y = op_read(OPMODE_ADDR, sp);
-    regs.p.n = !!(regs.y & 0x80);
-    regs.p.z = (regs.y == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_addrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    regs.a = op_read(OPMODE_ADDR, sp + regs.x);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_addry() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    regs.a = op_read(OPMODE_ADDR, sp + regs.y);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_idpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read() + regs.x;
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    sp  = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    sp |= op_read(OPMODE_DP, dp + 1) << 8;
-    } break;
-  case 5: {
-    regs.a = op_read(OPMODE_ADDR, sp);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_a_idpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    sp  = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    sp |= op_read(OPMODE_DP, dp + 1) << 8;
-    } break;
-  case 5: {
-    regs.a = op_read(OPMODE_ADDR, sp + regs.y);
-    regs.p.n = !!(regs.a & 0x80);
-    regs.p.z = (regs.a == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dp_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    dp = op_read();
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, sp);
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dp_const() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd = op_read();
-    } break;
-  case 2: {
-    dp = op_read();
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_ix_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, regs.x, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_ixinc_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, regs.x++, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dp_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, dp, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dp_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, dp, regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dp_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, dp, regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dpx_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp + regs.x, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dpy_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp + regs.y, regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_dpx_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp + regs.x, regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_addr_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_ADDR, dp, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_addr_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_ADDR, dp, regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_addr_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    op_write(OPMODE_ADDR, dp, regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_addrx_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    } break;
-  case 5: {
-    op_write(OPMODE_ADDR, dp + regs.x, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_addry_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    } break;
-  case 4: {
-    } break;
-  case 5: {
-    op_write(OPMODE_ADDR, dp + regs.y, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_idpx_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read() + regs.x;
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    dp  = op_read(OPMODE_DP, sp);
-    } break;
-  case 4: {
-    dp |= op_read(OPMODE_DP, sp + 1) << 8;
-    } break;
-  case 5: {
-    } break;
-  case 6: {
-    op_write(OPMODE_ADDR, dp, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov_idpy_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    dp  = op_read(OPMODE_DP, sp);
-    } break;
-  case 4: {
-    dp |= op_read(OPMODE_DP, sp + 1) << 8;
-    } break;
-  case 5: {
-    } break;
-  case 6: {
-    op_write(OPMODE_ADDR, dp + regs.y, regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_movw_ya_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    regs.a = op_read(OPMODE_DP, sp);
-    } break;
-  case 4: {
-    regs.y = op_read(OPMODE_DP, sp + 1);
-    regs.p.n = !!(regs.ya & 0x8000);
-    regs.p.z = (regs.ya == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_movw_dp_ya() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    op_write(OPMODE_DP, dp,     regs.a);
-    } break;
-  case 4: {
-    op_write(OPMODE_DP, dp + 1, regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov1_c_bit() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp  = op_read();
-    } break;
-  case 2: {
-    sp |= op_read() << 8;
-    } break;
-  case 3: {
-    bit = sp >> 13;
-    sp &= 0x1fff;
-    rd = op_read(OPMODE_ADDR, sp);
-    regs.p.c = !!(rd & (1 << bit));
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_mov1_bit_c() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    bit = dp >> 13;
-    dp &= 0x1fff;
-    rd = op_read(OPMODE_ADDR, dp);
-    if(regs.p.c)rd |=  (1 << bit);
-    else        rd &= ~(1 << bit);
-    } break;
-  case 4: {
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/apu/bapu/core/op_pc.b

@@ -1,166 +0,0 @@
-bra(0x2f, 0),
-beq(0xf0, !regs.p.z),
-bne(0xd0, regs.p.z),
-bcs(0xb0, !regs.p.c),
-bcc(0x90, regs.p.c),
-bvs(0x70, !regs.p.v),
-bvc(0x50, regs.p.v),
-bmi(0x30, !regs.p.n),
-bpl(0x10, regs.p.n) {
-1:rd = op_read();
-  if($1)end;
-2:
-3:regs.pc += (int8)rd;
-}
-
-bbs0(0x03, 0x01, !=),
-bbc0(0x13, 0x01, ==),
-bbs1(0x23, 0x02, !=),
-bbc1(0x33, 0x02, ==),
-bbs2(0x43, 0x04, !=),
-bbc2(0x53, 0x04, ==),
-bbs3(0x63, 0x08, !=),
-bbc3(0x73, 0x08, ==),
-bbs4(0x83, 0x10, !=),
-bbc4(0x93, 0x10, ==),
-bbs5(0xa3, 0x20, !=),
-bbc5(0xb3, 0x20, ==),
-bbs6(0xc3, 0x40, !=),
-bbc6(0xd3, 0x40, ==),
-bbs7(0xe3, 0x80, !=),
-bbc7(0xf3, 0x80, ==) {
-1:dp = op_read();
-2:rd = op_read();
-3:sp = op_read(OPMODE_DP, dp);
-4:if((sp & $1) $2 $1)end;
-5:
-6:regs.pc += (int8)rd;
-}
-
-cbne_dp(0x2e) {
-1:dp = op_read();
-2:rd = op_read();
-3:sp = op_read(OPMODE_DP, dp);
-4:if(regs.a == sp)end;
-5:
-6:regs.pc += (int8)rd;
-}
-
-cbne_dpx(0xde) {
-1:dp = op_read();
-2:rd = op_read();
-3:
-4:sp = op_read(OPMODE_DP, dp + regs.x);
-5:if(regs.a == sp)end;
-6:
-7:regs.pc += (int8)rd;
-}
-
-dbnz_dp(0x6e) {
-1:dp = op_read();
-2:rd = op_read();
-3:wr = op_read(OPMODE_DP, dp);
-4:wr--;
-  op_write(OPMODE_DP, dp, wr);
-  if(wr == 0x00)end;
-5:
-6:regs.pc += (int8)rd;
-}
-
-dbnz_y(0xfe) {
-1:rd = op_read();
-2:regs.y--;
-3:if(regs.y == 0x00)end;
-4:
-5:regs.pc += (int8)rd;
-}
-
-jmp_addr(0x5f) {
-1:rd  = op_read();
-2:rd |= op_read() << 8;
-  regs.pc = rd;
-}
-
-jmp_iaddrx(0x1f) {
-1:dp  = op_read();
-2:dp |= op_read() << 8;
-3:dp += regs.x;
-4:rd  = op_read(OPMODE_ADDR, dp);
-5:rd |= op_read(OPMODE_ADDR, dp + 1) << 8;
-  regs.pc = rd;
-}
-
-call(0x3f) {
-1:rd  = op_read();
-2:rd |= op_read() << 8;
-3:
-4:
-5:
-6:stack_write(regs.pc >> 8);
-7:stack_write(regs.pc);
-  regs.pc = rd;
-}
-
-pcall(0x4f) {
-1:rd = op_read();
-2:
-3:
-4:stack_write(regs.pc >> 8);
-5:stack_write(regs.pc);
-  regs.pc = 0xff00 | rd;
-}
-
-tcall_0(0x01, 0),
-tcall_1(0x11, 1),
-tcall_2(0x21, 2),
-tcall_3(0x31, 3),
-tcall_4(0x41, 4),
-tcall_5(0x51, 5),
-tcall_6(0x61, 6),
-tcall_7(0x71, 7),
-tcall_8(0x81, 8),
-tcall_9(0x91, 9),
-tcall_10(0xa1, 10),
-tcall_11(0xb1, 11),
-tcall_12(0xc1, 12),
-tcall_13(0xd1, 13),
-tcall_14(0xe1, 14),
-tcall_15(0xf1, 15) {
-1:dp = 0xffde - ($1 << 1);
-  rd  = op_read(OPMODE_ADDR, dp);
-2:rd |= op_read(OPMODE_ADDR, dp + 1) << 8;
-3:
-4:
-5:
-6:stack_write(regs.pc >> 8);
-7:stack_write(regs.pc);
-  regs.pc = rd;
-}
-
-brk(0x0f) {
-1:rd  = op_read(OPMODE_ADDR, 0xffde);
-2:rd |= op_read(OPMODE_ADDR, 0xffdf) << 8;
-3:
-4:
-5:stack_write(regs.pc >> 8);
-6:stack_write(regs.pc);
-7:stack_write(regs.p);
-  regs.pc = rd;
-  regs.p.b = 1;
-  regs.p.i = 0;
-}
-
-ret(0x6f) {
-1:rd  = stack_read();
-2:rd |= stack_read() << 8;
-3:
-4:regs.pc = rd;
-}
-
-reti(0x7f) {
-1:regs.p = stack_read();
-2:rd  = stack_read();
-3:rd |= stack_read() << 8;
-4:
-5:regs.pc = rd;
-}

src/apu/bapu/core/op_rmw.b

@@ -1,60 +0,0 @@
-inc_a(0xbc, inc, a),
-inc_x(0x3d, inc, x),
-inc_y(0xfc, inc, y),
-dec_a(0x9c, dec, a),
-dec_x(0x1d, dec, x),
-dec_y(0xdc, dec, y),
-asl_a(0x1c, asl, a),
-lsr_a(0x5c, lsr, a),
-rol_a(0x3c, rol, a),
-ror_a(0x7c, ror, a) {
-1:regs.$2 = op_$1(regs.$2);
-}
-
-inc_dp(0xab, inc),
-dec_dp(0x8b, dec),
-asl_dp(0x0b, asl),
-lsr_dp(0x4b, lsr),
-rol_dp(0x2b, rol),
-ror_dp(0x6b, ror) {
-1:dp = op_read();
-2:rd = op_read(OPMODE_DP, dp);
-3:rd = op_$1(rd);
-  op_write(OPMODE_DP, dp, rd);
-}
-
-inc_dpx(0xbb, inc),
-dec_dpx(0x9b, dec),
-asl_dpx(0x1b, asl),
-lsr_dpx(0x5b, lsr),
-rol_dpx(0x3b, rol),
-ror_dpx(0x7b, ror) {
-1:dp = op_read();
-2:
-3:rd = op_read(OPMODE_DP, dp + regs.x);
-4:rd = op_$1(rd);
-  op_write(OPMODE_DP, dp + regs.x, rd);
-}
-
-inc_addr(0xac, inc),
-dec_addr(0x8c, dec),
-asl_addr(0x0c, asl),
-lsr_addr(0x4c, lsr),
-rol_addr(0x2c, rol),
-ror_addr(0x6c, ror) {
-1:dp  = op_read();
-2:dp |= op_read() << 8;
-3:rd = op_read(OPMODE_ADDR, dp);
-4:rd = op_$1(rd);
-  op_write(OPMODE_ADDR, dp, rd);
-}
-
-incw_dp(0x3a, incw),
-decw_dp(0x1a, decw) {
-1:dp = op_read();
-2:rd  = op_read(OPMODE_DP, dp);
-3:rd |= op_read(OPMODE_DP, dp + 1) << 8;
-4:rd = op_$1(rd);
-  op_write(OPMODE_DP, dp + 1, rd >> 8);
-5:op_write(OPMODE_DP, dp,     rd);
-}

src/apu/bapu/core/op_rmw.cpp

@@ -1,452 +0,0 @@
-void bAPU::op_inc_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_inc(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_inc_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.x = op_inc(regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_inc_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.y = op_inc(regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_dec(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_x() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.x = op_dec(regs.x);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_y() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.y = op_dec(regs.y);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_asl_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_asl(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_lsr_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_lsr(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_rol_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_rol(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_ror_a() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    regs.a = op_ror(regs.a);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_inc_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_inc(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_dec(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_asl_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_asl(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_lsr_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_lsr(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_rol_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_rol(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_ror_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd = op_ror(rd);
-    op_write(OPMODE_DP, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_inc_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_inc(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_dec(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_asl_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_asl(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_lsr_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_lsr(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_rol_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_rol(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_ror_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_DP, dp + regs.x);
-    } break;
-  case 4: {
-    rd = op_ror(rd);
-    op_write(OPMODE_DP, dp + regs.x, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_inc_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_inc(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_dec_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_dec(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_asl_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_asl(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_lsr_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_lsr(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_rol_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_rol(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_ror_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp  = op_read();
-    } break;
-  case 2: {
-    dp |= op_read() << 8;
-    } break;
-  case 3: {
-    rd = op_read(OPMODE_ADDR, dp);
-    } break;
-  case 4: {
-    rd = op_ror(rd);
-    op_write(OPMODE_ADDR, dp, rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_incw_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd  = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |= op_read(OPMODE_DP, dp + 1) << 8;
-    } break;
-  case 4: {
-    rd = op_incw(rd);
-    op_write(OPMODE_DP, dp + 1, rd >> 8);
-    } break;
-  case 5: {
-    op_write(OPMODE_DP, dp,     rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bAPU::op_decw_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    rd  = op_read(OPMODE_DP, dp);
-    } break;
-  case 3: {
-    rd |= op_read(OPMODE_DP, dp + 1) << 8;
-    } break;
-  case 4: {
-    rd = op_decw(rd);
-    op_write(OPMODE_DP, dp + 1, rd >> 8);
-    } break;
-  case 5: {
-    op_write(OPMODE_DP, dp,     rd);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/apu/bapu/core/optable.cpp

@@ -1,256 +0,0 @@
-optbl[0x7d] = &bAPU::op_mov_a_x;
-optbl[0xdd] = &bAPU::op_mov_a_y;
-optbl[0x5d] = &bAPU::op_mov_x_a;
-optbl[0xfd] = &bAPU::op_mov_y_a;
-optbl[0x9d] = &bAPU::op_mov_x_sp;
-optbl[0xbd] = &bAPU::op_mov_sp_x;
-optbl[0xe8] = &bAPU::op_mov_a_const;
-optbl[0xcd] = &bAPU::op_mov_x_const;
-optbl[0x8d] = &bAPU::op_mov_y_const;
-optbl[0xe6] = &bAPU::op_mov_a_ix;
-optbl[0xbf] = &bAPU::op_mov_a_ixinc;
-optbl[0xe4] = &bAPU::op_mov_a_dp;
-optbl[0xf8] = &bAPU::op_mov_x_dp;
-optbl[0xeb] = &bAPU::op_mov_y_dp;
-optbl[0xf4] = &bAPU::op_mov_a_dpx;
-optbl[0xf9] = &bAPU::op_mov_x_dpy;
-optbl[0xfb] = &bAPU::op_mov_y_dpx;
-optbl[0xe5] = &bAPU::op_mov_a_addr;
-optbl[0xe9] = &bAPU::op_mov_x_addr;
-optbl[0xec] = &bAPU::op_mov_y_addr;
-optbl[0xf5] = &bAPU::op_mov_a_addrx;
-optbl[0xf6] = &bAPU::op_mov_a_addry;
-optbl[0xe7] = &bAPU::op_mov_a_idpx;
-optbl[0xf7] = &bAPU::op_mov_a_idpy;
-optbl[0xfa] = &bAPU::op_mov_dp_dp;
-optbl[0x8f] = &bAPU::op_mov_dp_const;
-optbl[0xc6] = &bAPU::op_mov_ix_a;
-optbl[0xaf] = &bAPU::op_mov_ixinc_a;
-optbl[0xc4] = &bAPU::op_mov_dp_a;
-optbl[0xd8] = &bAPU::op_mov_dp_x;
-optbl[0xcb] = &bAPU::op_mov_dp_y;
-optbl[0xd4] = &bAPU::op_mov_dpx_a;
-optbl[0xd9] = &bAPU::op_mov_dpy_x;
-optbl[0xdb] = &bAPU::op_mov_dpx_y;
-optbl[0xc5] = &bAPU::op_mov_addr_a;
-optbl[0xc9] = &bAPU::op_mov_addr_x;
-optbl[0xcc] = &bAPU::op_mov_addr_y;
-optbl[0xd5] = &bAPU::op_mov_addrx_a;
-optbl[0xd6] = &bAPU::op_mov_addry_a;
-optbl[0xc7] = &bAPU::op_mov_idpx_a;
-optbl[0xd7] = &bAPU::op_mov_idpy_a;
-optbl[0xba] = &bAPU::op_movw_ya_dp;
-optbl[0xda] = &bAPU::op_movw_dp_ya;
-optbl[0xaa] = &bAPU::op_mov1_c_bit;
-optbl[0xca] = &bAPU::op_mov1_bit_c;
-optbl[0x2f] = &bAPU::op_bra;
-optbl[0xf0] = &bAPU::op_beq;
-optbl[0xd0] = &bAPU::op_bne;
-optbl[0xb0] = &bAPU::op_bcs;
-optbl[0x90] = &bAPU::op_bcc;
-optbl[0x70] = &bAPU::op_bvs;
-optbl[0x50] = &bAPU::op_bvc;
-optbl[0x30] = &bAPU::op_bmi;
-optbl[0x10] = &bAPU::op_bpl;
-optbl[0x03] = &bAPU::op_bbs0;
-optbl[0x13] = &bAPU::op_bbc0;
-optbl[0x23] = &bAPU::op_bbs1;
-optbl[0x33] = &bAPU::op_bbc1;
-optbl[0x43] = &bAPU::op_bbs2;
-optbl[0x53] = &bAPU::op_bbc2;
-optbl[0x63] = &bAPU::op_bbs3;
-optbl[0x73] = &bAPU::op_bbc3;
-optbl[0x83] = &bAPU::op_bbs4;
-optbl[0x93] = &bAPU::op_bbc4;
-optbl[0xa3] = &bAPU::op_bbs5;
-optbl[0xb3] = &bAPU::op_bbc5;
-optbl[0xc3] = &bAPU::op_bbs6;
-optbl[0xd3] = &bAPU::op_bbc6;
-optbl[0xe3] = &bAPU::op_bbs7;
-optbl[0xf3] = &bAPU::op_bbc7;
-optbl[0x2e] = &bAPU::op_cbne_dp;
-optbl[0xde] = &bAPU::op_cbne_dpx;
-optbl[0x6e] = &bAPU::op_dbnz_dp;
-optbl[0xfe] = &bAPU::op_dbnz_y;
-optbl[0x5f] = &bAPU::op_jmp_addr;
-optbl[0x1f] = &bAPU::op_jmp_iaddrx;
-optbl[0x3f] = &bAPU::op_call;
-optbl[0x4f] = &bAPU::op_pcall;
-optbl[0x01] = &bAPU::op_tcall_0;
-optbl[0x11] = &bAPU::op_tcall_1;
-optbl[0x21] = &bAPU::op_tcall_2;
-optbl[0x31] = &bAPU::op_tcall_3;
-optbl[0x41] = &bAPU::op_tcall_4;
-optbl[0x51] = &bAPU::op_tcall_5;
-optbl[0x61] = &bAPU::op_tcall_6;
-optbl[0x71] = &bAPU::op_tcall_7;
-optbl[0x81] = &bAPU::op_tcall_8;
-optbl[0x91] = &bAPU::op_tcall_9;
-optbl[0xa1] = &bAPU::op_tcall_10;
-optbl[0xb1] = &bAPU::op_tcall_11;
-optbl[0xc1] = &bAPU::op_tcall_12;
-optbl[0xd1] = &bAPU::op_tcall_13;
-optbl[0xe1] = &bAPU::op_tcall_14;
-optbl[0xf1] = &bAPU::op_tcall_15;
-optbl[0x0f] = &bAPU::op_brk;
-optbl[0x6f] = &bAPU::op_ret;
-optbl[0x7f] = &bAPU::op_reti;
-optbl[0x88] = &bAPU::op_adc_a_const;
-optbl[0x28] = &bAPU::op_and_a_const;
-optbl[0x68] = &bAPU::op_cmp_a_const;
-optbl[0xc8] = &bAPU::op_cmp_x_const;
-optbl[0xad] = &bAPU::op_cmp_y_const;
-optbl[0x48] = &bAPU::op_eor_a_const;
-optbl[0x08] = &bAPU::op_or_a_const;
-optbl[0xa8] = &bAPU::op_sbc_a_const;
-optbl[0x86] = &bAPU::op_adc_a_ix;
-optbl[0x26] = &bAPU::op_and_a_ix;
-optbl[0x66] = &bAPU::op_cmp_a_ix;
-optbl[0x46] = &bAPU::op_eor_a_ix;
-optbl[0x06] = &bAPU::op_or_a_ix;
-optbl[0xa6] = &bAPU::op_sbc_a_ix;
-optbl[0x84] = &bAPU::op_adc_a_dp;
-optbl[0x24] = &bAPU::op_and_a_dp;
-optbl[0x64] = &bAPU::op_cmp_a_dp;
-optbl[0x3e] = &bAPU::op_cmp_x_dp;
-optbl[0x7e] = &bAPU::op_cmp_y_dp;
-optbl[0x44] = &bAPU::op_eor_a_dp;
-optbl[0x04] = &bAPU::op_or_a_dp;
-optbl[0xa4] = &bAPU::op_sbc_a_dp;
-optbl[0x94] = &bAPU::op_adc_a_dpx;
-optbl[0x34] = &bAPU::op_and_a_dpx;
-optbl[0x74] = &bAPU::op_cmp_a_dpx;
-optbl[0x54] = &bAPU::op_eor_a_dpx;
-optbl[0x14] = &bAPU::op_or_a_dpx;
-optbl[0xb4] = &bAPU::op_sbc_a_dpx;
-optbl[0x85] = &bAPU::op_adc_a_addr;
-optbl[0x25] = &bAPU::op_and_a_addr;
-optbl[0x65] = &bAPU::op_cmp_a_addr;
-optbl[0x1e] = &bAPU::op_cmp_x_addr;
-optbl[0x5e] = &bAPU::op_cmp_y_addr;
-optbl[0x45] = &bAPU::op_eor_a_addr;
-optbl[0x05] = &bAPU::op_or_a_addr;
-optbl[0xa5] = &bAPU::op_sbc_a_addr;
-optbl[0x95] = &bAPU::op_adc_a_addrx;
-optbl[0x96] = &bAPU::op_adc_a_addry;
-optbl[0x35] = &bAPU::op_and_a_addrx;
-optbl[0x36] = &bAPU::op_and_a_addry;
-optbl[0x75] = &bAPU::op_cmp_a_addrx;
-optbl[0x76] = &bAPU::op_cmp_a_addry;
-optbl[0x55] = &bAPU::op_eor_a_addrx;
-optbl[0x56] = &bAPU::op_eor_a_addry;
-optbl[0x15] = &bAPU::op_or_a_addrx;
-optbl[0x16] = &bAPU::op_or_a_addry;
-optbl[0xb5] = &bAPU::op_sbc_a_addrx;
-optbl[0xb6] = &bAPU::op_sbc_a_addry;
-optbl[0x87] = &bAPU::op_adc_a_idpx;
-optbl[0x27] = &bAPU::op_and_a_idpx;
-optbl[0x67] = &bAPU::op_cmp_a_idpx;
-optbl[0x47] = &bAPU::op_eor_a_idpx;
-optbl[0x07] = &bAPU::op_or_a_idpx;
-optbl[0xa7] = &bAPU::op_sbc_a_idpx;
-optbl[0x97] = &bAPU::op_adc_a_idpy;
-optbl[0x37] = &bAPU::op_and_a_idpy;
-optbl[0x77] = &bAPU::op_cmp_a_idpy;
-optbl[0x57] = &bAPU::op_eor_a_idpy;
-optbl[0x17] = &bAPU::op_or_a_idpy;
-optbl[0xb7] = &bAPU::op_sbc_a_idpy;
-optbl[0x99] = &bAPU::op_adc_ix_iy;
-optbl[0x39] = &bAPU::op_and_ix_iy;
-optbl[0x79] = &bAPU::op_cmp_ix_iy;
-optbl[0x59] = &bAPU::op_eor_ix_iy;
-optbl[0x19] = &bAPU::op_or_ix_iy;
-optbl[0xb9] = &bAPU::op_sbc_ix_iy;
-optbl[0x89] = &bAPU::op_adc_dp_dp;
-optbl[0x29] = &bAPU::op_and_dp_dp;
-optbl[0x69] = &bAPU::op_cmp_dp_dp;
-optbl[0x49] = &bAPU::op_eor_dp_dp;
-optbl[0x09] = &bAPU::op_or_dp_dp;
-optbl[0xa9] = &bAPU::op_sbc_dp_dp;
-optbl[0x98] = &bAPU::op_adc_dp_const;
-optbl[0x38] = &bAPU::op_and_dp_const;
-optbl[0x78] = &bAPU::op_cmp_dp_const;
-optbl[0x58] = &bAPU::op_eor_dp_const;
-optbl[0x18] = &bAPU::op_or_dp_const;
-optbl[0xb8] = &bAPU::op_sbc_dp_const;
-optbl[0x7a] = &bAPU::op_addw_ya_dp;
-optbl[0x5a] = &bAPU::op_cmpw_ya_dp;
-optbl[0x9a] = &bAPU::op_subw_ya_dp;
-optbl[0x4a] = &bAPU::op_and1_bit;
-optbl[0x6a] = &bAPU::op_and1_notbit;
-optbl[0x8a] = &bAPU::op_eor1_bit;
-optbl[0xea] = &bAPU::op_not1_bit;
-optbl[0x0a] = &bAPU::op_or1_bit;
-optbl[0x2a] = &bAPU::op_or1_notbit;
-optbl[0xbc] = &bAPU::op_inc_a;
-optbl[0x3d] = &bAPU::op_inc_x;
-optbl[0xfc] = &bAPU::op_inc_y;
-optbl[0x9c] = &bAPU::op_dec_a;
-optbl[0x1d] = &bAPU::op_dec_x;
-optbl[0xdc] = &bAPU::op_dec_y;
-optbl[0x1c] = &bAPU::op_asl_a;
-optbl[0x5c] = &bAPU::op_lsr_a;
-optbl[0x3c] = &bAPU::op_rol_a;
-optbl[0x7c] = &bAPU::op_ror_a;
-optbl[0xab] = &bAPU::op_inc_dp;
-optbl[0x8b] = &bAPU::op_dec_dp;
-optbl[0x0b] = &bAPU::op_asl_dp;
-optbl[0x4b] = &bAPU::op_lsr_dp;
-optbl[0x2b] = &bAPU::op_rol_dp;
-optbl[0x6b] = &bAPU::op_ror_dp;
-optbl[0xbb] = &bAPU::op_inc_dpx;
-optbl[0x9b] = &bAPU::op_dec_dpx;
-optbl[0x1b] = &bAPU::op_asl_dpx;
-optbl[0x5b] = &bAPU::op_lsr_dpx;
-optbl[0x3b] = &bAPU::op_rol_dpx;
-optbl[0x7b] = &bAPU::op_ror_dpx;
-optbl[0xac] = &bAPU::op_inc_addr;
-optbl[0x8c] = &bAPU::op_dec_addr;
-optbl[0x0c] = &bAPU::op_asl_addr;
-optbl[0x4c] = &bAPU::op_lsr_addr;
-optbl[0x2c] = &bAPU::op_rol_addr;
-optbl[0x6c] = &bAPU::op_ror_addr;
-optbl[0x3a] = &bAPU::op_incw_dp;
-optbl[0x1a] = &bAPU::op_decw_dp;
-optbl[0x00] = &bAPU::op_nop;
-optbl[0xef] = &bAPU::op_sleep;
-optbl[0xff] = &bAPU::op_stop;
-optbl[0x9f] = &bAPU::op_xcn;
-optbl[0xdf] = &bAPU::op_daa;
-optbl[0xbe] = &bAPU::op_das;
-optbl[0x60] = &bAPU::op_clrc;
-optbl[0x20] = &bAPU::op_clrp;
-optbl[0x80] = &bAPU::op_setc;
-optbl[0x40] = &bAPU::op_setp;
-optbl[0xe0] = &bAPU::op_clrv;
-optbl[0xed] = &bAPU::op_notc;
-optbl[0xa0] = &bAPU::op_ei;
-optbl[0xc0] = &bAPU::op_di;
-optbl[0x02] = &bAPU::op_set0_dp;
-optbl[0x12] = &bAPU::op_clr0_dp;
-optbl[0x22] = &bAPU::op_set1_dp;
-optbl[0x32] = &bAPU::op_clr1_dp;
-optbl[0x42] = &bAPU::op_set2_dp;
-optbl[0x52] = &bAPU::op_clr2_dp;
-optbl[0x62] = &bAPU::op_set3_dp;
-optbl[0x72] = &bAPU::op_clr3_dp;
-optbl[0x82] = &bAPU::op_set4_dp;
-optbl[0x92] = &bAPU::op_clr4_dp;
-optbl[0xa2] = &bAPU::op_set5_dp;
-optbl[0xb2] = &bAPU::op_clr5_dp;
-optbl[0xc2] = &bAPU::op_set6_dp;
-optbl[0xd2] = &bAPU::op_clr6_dp;
-optbl[0xe2] = &bAPU::op_set7_dp;
-optbl[0xf2] = &bAPU::op_clr7_dp;
-optbl[0x0e] = &bAPU::op_tset_addr_a;
-optbl[0x4e] = &bAPU::op_tclr_addr_a;
-optbl[0x2d] = &bAPU::op_push_a;
-optbl[0x4d] = &bAPU::op_push_x;
-optbl[0x6d] = &bAPU::op_push_y;
-optbl[0x0d] = &bAPU::op_push_p;
-optbl[0xae] = &bAPU::op_pop_a;
-optbl[0xce] = &bAPU::op_pop_x;
-optbl[0xee] = &bAPU::op_pop_y;
-optbl[0x8e] = &bAPU::op_pop_p;
-optbl[0xcf] = &bAPU::op_mul_ya;
-optbl[0x9e] = &bAPU::op_div_ya_x;

src/apu/bapu/memory/memory.cpp

@@ -1,199 +0,0 @@
-uint8 bAPU::spcram_read(uint16 addr) {
-uint8 r;
-  if(addr >= 0x00f0 && addr <= 0x00ff) {
-    switch(addr) {
-    case 0xf0: //TEST -- operation unknown, supposedly returns 0x00
-      r = 0x00;
-      break;
-    case 0xf1: //CONTROL -- write-only register, always returns 0x00
-      r = 0x00;
-      break;
-    case 0xf2: //DSPADDR
-      r = status.dsp_addr;
-      break;
-    case 0xf3: //DSPDATA
-    //0x80-0xff is a read-only mirror of 0x00-0x7f
-      r = r_dsp->read(status.dsp_addr & 0x7f);
-      break;
-    case 0xf4: //CPUIO0
-    case 0xf5: //CPUIO1
-    case 0xf6: //CPUIO2
-    case 0xf7: //CPUIO3
-      r = r_cpu->port_read(addr & 3);
-      break;
-    case 0xf8: //???
-    case 0xf9: //??? -- Mapped to SPCRAM
-      r = spcram[addr];
-      break;
-    case 0xfa: //T0TARGET
-    case 0xfb: //T1TARGET
-    case 0xfc: //T2TARGET -- write-only registers, always return 0x00
-      r = 0x00;
-      break;
-    case 0xfd: //T0OUT -- 4-bit counter value
-      r = t0.stage3_ticks & 15;
-      t0.stage3_ticks = 0;
-      break;
-    case 0xfe: //T1OUT -- 4-bit counter value
-      r = t1.stage3_ticks & 15;
-      t1.stage3_ticks = 0;
-      break;
-    case 0xff: //T2OUT -- 4-bit counter value
-      r = t2.stage3_ticks & 15;
-      t2.stage3_ticks = 0;
-      break;
-    }
-  } else if(addr < 0xffc0) {
-    r = spcram[addr];
-  } else {
-    if(status.iplrom_enabled == true) {
-      r = iplrom[addr & 0x3f];
-    } else {
-      r = spcram[addr];
-    }
-  }
-
-#ifdef DEBUGGER
-  snes->notify(SNES::SPCRAM_READ, addr, r);
-#endif
-  return r;
-}
-
-void bAPU::spcram_write(uint16 addr, uint8 value) {
-  if(addr >= 0x00f0 && addr <= 0x00ff) {
-    switch(addr) {
-    case 0xf0: //TEST -- operation unknown
-      break;
-    case 0xf1: //CONTROL
-      status.iplrom_enabled = !!(value & 0x80);
-
-    //one-time clearing of APU port read registers,
-    //emulated by simulating CPU writes of 0x00
-      if(value & 0x20) {
-        r_cpu->port_write(2, 0x00);
-        r_cpu->port_write(3, 0x00);
-      }
-      if(value & 0x10) {
-        r_cpu->port_write(0, 0x00);
-        r_cpu->port_write(1, 0x00);
-      }
-
-    //0->1 transistion resets timers
-      if(t2.enabled == false && (value & 0x04)) {
-        t2.stage2_ticks = 0;
-        t2.stage3_ticks = 0;
-      }
-      t2.enabled = !!(value & 0x04);
-
-      if(t1.enabled == false && (value & 0x02)) {
-        t1.stage2_ticks = 0;
-        t1.stage3_ticks = 0;
-      }
-      t1.enabled = !!(value & 0x02);
-
-      if(t0.enabled == false && (value & 0x01)) {
-        t0.stage2_ticks = 0;
-        t0.stage3_ticks = 0;
-      }
-      t0.enabled = !!(value & 0x01);
-      break;
-    case 0xf2: //DSPADDR
-      status.dsp_addr = value;
-      break;
-    case 0xf3: //DSPDATA
-    //0x80-0xff is a read-only mirror of 0x00-0x7f
-      if(status.dsp_addr < 0x80) {
-        r_dsp->write(status.dsp_addr & 0x7f, value);
-      }
-      break;
-    case 0xf4: //CPUIO0
-    case 0xf5: //CPUIO1
-    case 0xf6: //CPUIO2
-    case 0xf7: //CPUIO3
-      port_write(addr & 3, value);
-      break;
-    case 0xf8: //???
-    case 0xf9: //??? - Mapped to SPCRAM
-      spcram[addr] = value;
-      break;
-    case 0xfa: //T0TARGET
-      t0.target = value;
-      break;
-    case 0xfb: //T1TARGET
-      t1.target = value;
-      break;
-    case 0xfc: //T2TARGET
-      t2.target = value;
-      break;
-    case 0xfd: //T0OUT
-    case 0xfe: //T1OUT
-    case 0xff: //T2OUT -- read-only registers
-      break;
-    }
-  } else {
-  //writes to $ffc0-$ffff always go to spcram,
-  //even if the iplrom is enabled.
-    spcram[addr] = value;
-  }
-
-#ifdef DEBUGGER
-  snes->notify(SNES::SPCRAM_WRITE, addr, value);
-#endif
-}
-
-uint8 bAPU::port_read(uint8 port) {
-  return spcram[0xf4 + (port & 3)];
-}
-
-void bAPU::port_write(uint8 port, uint8 value) {
-  spcram[0xf4 + (port & 0x03)] = value;
-}
-
-uint8 bAPU::op_read() {
-uint8 r;
-  r = spcram_read(regs.pc);
-  regs.pc++;
-  return r;
-}
-
-uint8 bAPU::op_read(uint8 mode, uint16 addr) {
-uint8 r;
-  switch(mode) {
-  case OPMODE_ADDR:
-    r = spcram_read(addr);
-    break;
-  case OPMODE_DP:
-    r = spcram_read(((regs.p.p)?0x100:0x000) + (addr & 0xff));
-    break;
-  }
-  return r;
-}
-
-void bAPU::op_write(uint8 mode, uint16 addr, uint8 value) {
-  switch(mode) {
-  case OPMODE_ADDR:
-    spcram_write(addr, value);
-    break;
-  case OPMODE_DP:
-    spcram_write(((regs.p.p)?0x100:0x000) + (addr & 0xff), value);
-    break;
-  }
-}
-
-uint8 bAPU::stack_read() {
-  regs.sp++;
-  return spcram_read(0x0100 | regs.sp);
-}
-
-void bAPU::stack_write(uint8 value) {
-  spcram_write(0x0100 | regs.sp, value);
-  regs.sp--;
-}
-
-uint8 *bAPU::get_spcram_handle() {
-  if(!spcram) {
-    alert("bAPU::get_spcram_handle() -- spcram uninitialized");
-  }
-
-  return spcram;
-}

src/apu/bapu/memory/memory.h

@@ -1,14 +0,0 @@
-enum { OPMODE_ADDR, OPMODE_DP };
-uint8 *spcram;
-  inline uint8  spcram_read (uint16 addr);
-  inline void   spcram_write(uint16 addr, uint8 value);
-  inline uint8  port_read (uint8 port);
-  inline void   port_write(uint8 port,  uint8 value);
-
-  inline uint8 *get_spcram_handle();
-
-  inline uint8  op_read();
-  inline uint8  op_read (uint8 mode, uint16 addr);
-  inline void   op_write(uint8 mode, uint16 addr, uint8 value);
-  inline uint8  stack_read();
-  inline void   stack_write(uint8 value);

src/apu/bapu/timing/timing.cpp

@@ -1,35 +0,0 @@
-void bAPU::add_cycles(int cycles) {
-  status.cycles_executed += cycles;
-
-  t0.add_cycles(cycles);
-  t1.add_cycles(cycles);
-  t2.add_cycles(cycles);
-}
-
-uint32 bAPU::cycles_executed() {
-uint32 r = status.cycles_executed;
-  status.cycles_executed = 0;
-  return (r << 4) + (r << 3);
-}
-
-//cycles should never be greater than 12. since the minimum
-//cycle_frequency value is 16, we don't have to worry about
-//two ticks occuring in one call to this function.
-void bAPU::bAPUTimer::add_cycles(int cycles) {
-//stage 1 increment
-  stage1_ticks += cycles;
-  if(stage1_ticks < cycle_frequency)return;
-
-  stage1_ticks -= cycle_frequency;
-  if(enabled == false)return;
-
-//stage 2 increment
-  stage2_ticks++;
-
-  if(stage2_ticks != target)return;
-
-//stage 3 increment
-  stage2_ticks = 0;
-  stage3_ticks++;
-  stage3_ticks &= 15;
-}

src/apu/bapu/timing/timing.h

@@ -1,9 +0,0 @@
-class bAPUTimer {
-public:
-uint8 cycle_frequency, target;
-uint8 stage1_ticks, stage2_ticks, stage3_ticks;
-bool  enabled;
-  inline void add_cycles(int cycles);
-} t0, t1, t2;
-  inline void   add_cycles(int cycles);
-  inline uint32 cycles_executed();

src/apu/dapu.cpp

@@ -1,306 +0,0 @@
-//virtual function, see src/cpu/dcpu.cpp
-//for explanation of this function
-bool APU::in_opcode() { return false; }
-
-uint16 APU::__relb(int8 offset, int op_len) {
-uint16 pc = regs.pc + op_len;
-  return pc + offset;
-}
-
-void APU::disassemble_opcode(char *output) {
-char *s, t[512];
-uint8  op, op0, op1;
-uint16 opw, opdp0, opdp1;
-  s = output;
-
-  if(in_opcode() == true) {
-    strcpy(s, "..???? <APU within opcode>");
-    return;
-  }
-
-  sprintf(s, "..%0.4x ", regs.pc);
-
-  op  = spcram_read(regs.pc);
-  op0 = spcram_read(regs.pc + 1);
-  op1 = spcram_read(regs.pc + 2);
-  opw = (op0) | (op1 << 8);
-  opdp0 = ((regs.p.p)?0x100:0x000) + op0;
-  opdp1 = ((regs.p.p)?0x100:0x000) + op1;
-
-  strcpy(t, "                        ");
-  switch(op) {
-  case 0x00:sprintf(t, "nop");                                         break;
-  case 0x01:sprintf(t, "tcall 0");                                     break;
-  case 0x02:sprintf(t, "set0  $%0.3x", opdp0);                         break;
-  case 0x03:sprintf(t, "bbs0  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x04:sprintf(t, "or    a,$%0.3x", opdp0);                       break;
-  case 0x05:sprintf(t, "or    a,$%0.4x", opw);                         break;
-  case 0x06:sprintf(t, "or    a,(x)");                                 break;
-  case 0x07:sprintf(t, "or    a,($%0.3x+x)", opdp0);                   break;
-  case 0x08:sprintf(t, "or    a,#$%0.2x", op0);                        break;
-  case 0x09:sprintf(t, "or    $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0x0a:sprintf(t, "or1   c,$%0.4x:%d", opw & 0x1fff, opw >> 13);  break;
-  case 0x0b:sprintf(t, "asl   $%0.3x", opdp0);                         break;
-  case 0x0c:sprintf(t, "asl   $%0.4x", opw);                           break;
-  case 0x0d:sprintf(t, "push  p");                                     break;
-  case 0x0e:sprintf(t, "tset  $%0.4x,a", opw);                         break;
-  case 0x0f:sprintf(t, "brk");                                         break;
-  case 0x10:sprintf(t, "bpl   $%0.4x", __relb(op0, 2));                break;
-  case 0x11:sprintf(t, "tcall 1");                                     break;
-  case 0x12:sprintf(t, "clr0  $%0.3x", opdp0);                         break;
-  case 0x13:sprintf(t, "bbc0  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x14:sprintf(t, "or    a,$%0.3x+x", opdp0);                     break;
-  case 0x15:sprintf(t, "or    a,$%0.4x+x", opw);                       break;
-  case 0x16:sprintf(t, "or    a,$%0.4x+y", opw);                       break;
-  case 0x17:sprintf(t, "or    a,($%0.3x)+y", opdp0);                   break;
-  case 0x18:sprintf(t, "or    $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x19:sprintf(t, "or    (x),(y)");                               break;
-  case 0x1a:sprintf(t, "decw  $%0.3x", opdp0);                         break;
-  case 0x1b:sprintf(t, "asl   $%0.3x+x", opdp0);                       break;
-  case 0x1c:sprintf(t, "asl   a");                                     break;
-  case 0x1d:sprintf(t, "dec   x");                                     break;
-  case 0x1e:sprintf(t, "cmp   x,$%0.4x", opw);                         break;
-  case 0x1f:sprintf(t, "jmp   ($%0.4x+x)", opw);                       break;
-  case 0x20:sprintf(t, "clrp");                                        break;
-  case 0x21:sprintf(t, "tcall 2");                                     break;
-  case 0x22:sprintf(t, "set1  $%0.3x", opdp0);                         break;
-  case 0x23:sprintf(t, "bbs1  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x24:sprintf(t, "and   a,$%0.3x", opdp0);                       break;
-  case 0x25:sprintf(t, "and   a,$%0.4x", opw);                         break;
-  case 0x26:sprintf(t, "and   a,(x)");                                 break;
-  case 0x27:sprintf(t, "and   a,($%0.3x+x)", opdp0);                   break;
-  case 0x28:sprintf(t, "and   a,#$%0.2x", op0);                        break;
-  case 0x29:sprintf(t, "and   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0x2a:sprintf(t, "or1   c,!$%0.4x:%d", opw & 0x1fff, opw >> 13); break;
-  case 0x2b:sprintf(t, "rol   $%0.3x", opdp0);                         break;
-  case 0x2c:sprintf(t, "rol   $%0.4x", opw);                           break;
-  case 0x2d:sprintf(t, "push  a");                                     break;
-  case 0x2e:sprintf(t, "cbne  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x2f:sprintf(t, "bra   $%0.4x", __relb(op0, 2));                break;
-  case 0x30:sprintf(t, "bmi   $%0.4x", __relb(op0, 2));                break;
-  case 0x31:sprintf(t, "tcall 3");                                     break;
-  case 0x32:sprintf(t, "clr1  $%0.3x", opdp0);                         break;
-  case 0x33:sprintf(t, "bbc1  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x34:sprintf(t, "and   a,$%0.3x+x", opdp0);                     break;
-  case 0x35:sprintf(t, "and   a,$%0.4x+x", opw);                       break;
-  case 0x36:sprintf(t, "and   a,$%0.4x+y", opw);                       break;
-  case 0x37:sprintf(t, "and   a,($%0.3x)+y", opdp0);                   break;
-  case 0x38:sprintf(t, "and   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x39:sprintf(t, "and   (x),(y)");                               break;
-  case 0x3a:sprintf(t, "incw  $%0.3x", opdp0);                         break;
-  case 0x3b:sprintf(t, "rol   $%0.3x+x", opdp0);                       break;
-  case 0x3c:sprintf(t, "rol   a");                                     break;
-  case 0x3d:sprintf(t, "inc   x");                                     break;
-  case 0x3e:sprintf(t, "cmp   x,$%0.3x", opdp0);                       break;
-  case 0x3f:sprintf(t, "call  $%0.4x", opw);                           break;
-  case 0x40:sprintf(t, "setp");                                        break;
-  case 0x41:sprintf(t, "tcall 4");                                     break;
-  case 0x42:sprintf(t, "set2  $%0.3x", opdp0);                         break;
-  case 0x43:sprintf(t, "bbs2  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x44:sprintf(t, "eor   a,$%0.3x", opdp0);                       break;
-  case 0x45:sprintf(t, "eor   a,$%0.4x", opw);                         break;
-  case 0x46:sprintf(t, "eor   a,(x)");                                 break;
-  case 0x47:sprintf(t, "eor   a,($%0.3x+x)", opdp0);                   break;
-  case 0x48:sprintf(t, "eor   a,#$%0.2x", op0);                        break;
-  case 0x49:sprintf(t, "eor   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0x4a:sprintf(t, "and1  c,$%0.4x:%d", opw & 0x1fff, opw >> 13);  break;
-  case 0x4b:sprintf(t, "lsr   $%0.3x", opdp0);                         break;
-  case 0x4c:sprintf(t, "lsr   $%0.4x", opw);                           break;
-  case 0x4d:sprintf(t, "push  x");                                     break;
-  case 0x4e:sprintf(t, "tclr  $%0.4x,a", opw);                         break;
-  case 0x4f:sprintf(t, "pcall $ff%0.2x", op0);                         break;
-  case 0x50:sprintf(t, "bvc   $%0.4x", __relb(op0, 2));                break;
-  case 0x51:sprintf(t, "tcall 5");                                     break;
-  case 0x52:sprintf(t, "clr2  $%0.3x", opdp0);                         break;
-  case 0x53:sprintf(t, "bbc2  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x54:sprintf(t, "eor   a,$%0.3x+x", opdp0);                     break;
-  case 0x55:sprintf(t, "eor   a,$%0.4x+x", opw);                       break;
-  case 0x56:sprintf(t, "eor   a,$%0.4x+y", opw);                       break;
-  case 0x57:sprintf(t, "eor   a,($%0.3x)+y", opdp0);                   break;
-  case 0x58:sprintf(t, "eor   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x59:sprintf(t, "eor   (x),(y)");                               break;
-  case 0x5a:sprintf(t, "cmpw  ya,$%0.3x", opdp0);                      break;
-  case 0x5b:sprintf(t, "lsr   $%0.3x+x", opdp0);                       break;
-  case 0x5c:sprintf(t, "lsr   a");                                     break;
-  case 0x5d:sprintf(t, "mov   x,a");                                   break;
-  case 0x5e:sprintf(t, "cmp   y,$%0.4x", opw);                         break;
-  case 0x5f:sprintf(t, "jmp   $%0.4x", opw);                           break;
-  case 0x60:sprintf(t, "clrc");                                        break;
-  case 0x61:sprintf(t, "tcall 6");                                     break;
-  case 0x62:sprintf(t, "set3  $%0.3x", opdp0);                         break;
-  case 0x63:sprintf(t, "bbs3  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x64:sprintf(t, "cmp   a,$%0.3x", opdp0);                       break;
-  case 0x65:sprintf(t, "cmp   a,$%0.4x", opw);                         break;
-  case 0x66:sprintf(t, "cmp   a,(x)");                                 break;
-  case 0x67:sprintf(t, "cmp   a,($%0.3x+x)", opdp0);                   break;
-  case 0x68:sprintf(t, "cmp   a,#$%0.2x", op0);                        break;
-  case 0x69:sprintf(t, "cmp   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0x6a:sprintf(t, "and1  c,!$%0.4x:%d", opw & 0x1fff, opw >> 13); break;
-  case 0x6b:sprintf(t, "ror   $%0.3x", opdp0);                         break;
-  case 0x6c:sprintf(t, "ror   $%0.4x", opw);                           break;
-  case 0x6d:sprintf(t, "push  y");                                     break;
-  case 0x6e:sprintf(t, "dbnz  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x6f:sprintf(t, "ret");                                         break;
-  case 0x70:sprintf(t, "bvs   $%0.4x", __relb(op0, 2));                break;
-  case 0x71:sprintf(t, "tcall 7");                                     break;
-  case 0x72:sprintf(t, "clr3  $%0.3x", opdp0);                         break;
-  case 0x73:sprintf(t, "bbc3  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x74:sprintf(t, "cmp   a,$%0.3x+x", opdp0);                     break;
-  case 0x75:sprintf(t, "cmp   a,$%0.4x+x", opw);                       break;
-  case 0x76:sprintf(t, "cmp   a,$%0.4x+y", opw);                       break;
-  case 0x77:sprintf(t, "cmp   a,($%0.3x)+y", opdp0);                   break;
-  case 0x78:sprintf(t, "cmp   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x79:sprintf(t, "cmp   (x),(y)");                               break;
-  case 0x7a:sprintf(t, "addw  ya,$%0.3x", opdp0);                      break;
-  case 0x7b:sprintf(t, "ror   $%0.3x+x", opdp0);                       break;
-  case 0x7c:sprintf(t, "ror   a");                                     break;
-  case 0x7d:sprintf(t, "mov   a,x");                                   break;
-  case 0x7e:sprintf(t, "cmp   y,$%0.3x", opdp0);                       break;
-  case 0x7f:sprintf(t, "reti");                                        break;
-  case 0x80:sprintf(t, "setc");                                        break;
-  case 0x81:sprintf(t, "tcall 8");                                     break;
-  case 0x82:sprintf(t, "set4  $%0.3x", opdp0);                         break;
-  case 0x83:sprintf(t, "bbs4  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x84:sprintf(t, "adc   a,$%0.3x", opdp0);                       break;
-  case 0x85:sprintf(t, "adc   a,$%0.4x", opw);                         break;
-  case 0x86:sprintf(t, "adc   a,(x)");                                 break;
-  case 0x87:sprintf(t, "adc   a,($%0.3x+x)", opdp0);                   break;
-  case 0x88:sprintf(t, "adc   a,#$%0.2x", op0);                        break;
-  case 0x89:sprintf(t, "adc   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0x8a:sprintf(t, "eor1  c,$%0.4x:%d", opw & 0x1fff, opw >> 13);  break;
-  case 0x8b:sprintf(t, "dec   $%0.3x", opdp0);                         break;
-  case 0x8c:sprintf(t, "dec   $%0.4x", opw);                           break;
-  case 0x8d:sprintf(t, "mov   y,#$%0.2x", op0);                        break;
-  case 0x8e:sprintf(t, "pop   p");                                     break;
-  case 0x8f:sprintf(t, "mov   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x90:sprintf(t, "bcc   $%0.4x", __relb(op0, 2));                break;
-  case 0x91:sprintf(t, "tcall 9");                                     break;
-  case 0x92:sprintf(t, "clr4  $%0.3x", opdp0);                         break;
-  case 0x93:sprintf(t, "bbc4  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0x94:sprintf(t, "adc   a,$%0.3x+x", opdp0);                     break;
-  case 0x95:sprintf(t, "adc   a,$%0.4x+x", opw);                       break;
-  case 0x96:sprintf(t, "adc   a,$%0.4x+y", opw);                       break;
-  case 0x97:sprintf(t, "adc   a,($%0.3x)+y", opdp0);                   break;
-  case 0x98:sprintf(t, "adc   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0x99:sprintf(t, "adc   (x),(y)");                               break;
-  case 0x9a:sprintf(t, "subw  ya,$%0.3x", opdp0);                      break;
-  case 0x9b:sprintf(t, "dec   $%0.3x+x", opdp0);                       break;
-  case 0x9c:sprintf(t, "dec   a");                                     break;
-  case 0x9d:sprintf(t, "mov   x,sp");                                  break;
-  case 0x9e:sprintf(t, "div   ya,x");                                  break;
-  case 0x9f:sprintf(t, "xcn   a");                                     break;
-  case 0xa0:sprintf(t, "ei");                                          break;
-  case 0xa1:sprintf(t, "tcall 10");                                    break;
-  case 0xa2:sprintf(t, "set5  $%0.3x", opdp0);                         break;
-  case 0xa3:sprintf(t, "bbs5  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xa4:sprintf(t, "sbc   a,$%0.3x", opdp0);                       break;
-  case 0xa5:sprintf(t, "sbc   a,$%0.4x", opw);                         break;
-  case 0xa6:sprintf(t, "sbc   a,(x)");                                 break;
-  case 0xa7:sprintf(t, "sbc   a,($%0.3x+x)", opdp0);                   break;
-  case 0xa8:sprintf(t, "sbc   a,#$%0.2x", op0);                        break;
-  case 0xa9:sprintf(t, "sbc   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0xaa:sprintf(t, "mov1  c,$%0.4x:%d", opw & 0x1fff, opw >> 13);  break;
-  case 0xab:sprintf(t, "inc   $%0.3x", opdp0);                         break;
-  case 0xac:sprintf(t, "inc   $%0.4x", opw);                           break;
-  case 0xad:sprintf(t, "cmp   y,#$%0.2x", op0);                        break;
-  case 0xae:sprintf(t, "pop   a");                                     break;
-  case 0xaf:sprintf(t, "mov   (x)+,a");                                break;
-  case 0xb0:sprintf(t, "bcs   $%0.4x", __relb(op0, 2));                break;
-  case 0xb1:sprintf(t, "tcall 11");                                    break;
-  case 0xb2:sprintf(t, "clr5  $%0.3x", opdp0);                         break;
-  case 0xb3:sprintf(t, "bbc5  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xb4:sprintf(t, "sbc   a,$%0.3x+x", opdp0);                     break;
-  case 0xb5:sprintf(t, "sbc   a,$%0.4x+x", opw);                       break;
-  case 0xb6:sprintf(t, "sbc   a,$%0.4x+y", opw);                       break;
-  case 0xb7:sprintf(t, "sbc   a,($%0.3x)+y", opdp0);                   break;
-  case 0xb8:sprintf(t, "sbc   $%0.3x,#$%0.2x", opdp1, op0);            break;
-  case 0xb9:sprintf(t, "sbc   (x),(y)");                               break;
-  case 0xba:sprintf(t, "movw  ya,$%0.3x", opdp0);                      break;
-  case 0xbb:sprintf(t, "inc   $%0.3x+x", opdp0);                       break;
-  case 0xbc:sprintf(t, "inc   a");                                     break;
-  case 0xbd:sprintf(t, "mov   sp,x");                                  break;
-  case 0xbe:sprintf(t, "das   a");                                     break;
-  case 0xbf:sprintf(t, "mov   a,(x)+");                                break;
-  case 0xc0:sprintf(t, "di");                                          break;
-  case 0xc1:sprintf(t, "tcall 12");                                    break;
-  case 0xc2:sprintf(t, "set6  $%0.3x", opdp0);                         break;
-  case 0xc3:sprintf(t, "bbs6  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xc4:sprintf(t, "mov   $%0.3x,a", opdp0);                       break;
-  case 0xc5:sprintf(t, "mov   $%0.4x,a", opw);                         break;
-  case 0xc6:sprintf(t, "mov   (x),a");                                 break;
-  case 0xc7:sprintf(t, "mov   ($%0.3x+x),a", opdp0);                   break;
-  case 0xc8:sprintf(t, "cmp   x,#$%0.2x", op0);                        break;
-  case 0xc9:sprintf(t, "mov   $%0.4x,x", opw);                         break;
-  case 0xca:sprintf(t, "mov1  $%0.4x:%d,c", opw & 0x1fff, opw >> 13);  break;
-  case 0xcb:sprintf(t, "mov   $%0.3x,y", opdp0);                       break;
-  case 0xcc:sprintf(t, "mov   $%0.4x,y", opw);                         break;
-  case 0xcd:sprintf(t, "mov   x,#$%0.2x", op0);                        break;
-  case 0xce:sprintf(t, "pop   x");                                     break;
-  case 0xcf:sprintf(t, "mul   ya");                                    break;
-  case 0xd0:sprintf(t, "bne   $%0.4x", __relb(op0, 2));                break;
-  case 0xd1:sprintf(t, "tcall 13");                                    break;
-  case 0xd2:sprintf(t, "clr6  $%0.3x", opdp0);                         break;
-  case 0xd3:sprintf(t, "bbc6  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xd4:sprintf(t, "mov   $%0.3x+x,a", opdp0);                     break;
-  case 0xd5:sprintf(t, "mov   $%0.4x+x,a", opw);                       break;
-  case 0xd6:sprintf(t, "mov   $%0.4x+y,a", opw);                       break;
-  case 0xd7:sprintf(t, "mov   ($%0.3x)+y,a", opdp0);                   break;
-  case 0xd8:sprintf(t, "mov   $%0.3x,x", opdp0);                       break;
-  case 0xd9:sprintf(t, "mov   $%0.3x+y,x", opdp0);                     break;
-  case 0xda:sprintf(t, "movw  $%0.3x,ya", opdp0);                      break;
-  case 0xdb:sprintf(t, "mov   $%0.3x+x,y", opdp0);                     break;
-  case 0xdc:sprintf(t, "dec   y");                                     break;
-  case 0xdd:sprintf(t, "mov   a,y");                                   break;
-  case 0xde:sprintf(t, "cbne  $%0.3x+x,$%0.4x", opdp0, __relb(op1, 3));break;
-  case 0xdf:sprintf(t, "daa   a");                                     break;
-  case 0xe0:sprintf(t, "clrv");                                        break;
-  case 0xe1:sprintf(t, "tcall 14");                                    break;
-  case 0xe2:sprintf(t, "set7  $%0.3x", opdp0);                         break;
-  case 0xe3:sprintf(t, "bbs7  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xe4:sprintf(t, "mov   a,$%0.3x", opdp0);                       break;
-  case 0xe5:sprintf(t, "mov   a,$%0.4x", opw);                         break;
-  case 0xe6:sprintf(t, "mov   a,(x)");                                 break;
-  case 0xe7:sprintf(t, "mov   a,($%0.3x+x)", opdp0);                   break;
-  case 0xe8:sprintf(t, "mov   a,#$%0.2x", op0);                        break;
-  case 0xe9:sprintf(t, "mov   x,$%0.4x", opw);                         break;
-  case 0xea:sprintf(t, "not1  c,$%0.4x:%d", opw & 0x1fff, opw >> 13);  break;
-  case 0xeb:sprintf(t, "mov   y,$%0.3x", opdp0);                       break;
-  case 0xec:sprintf(t, "mov   y,$%0.4x", opw);                         break;
-  case 0xed:sprintf(t, "notc");                                        break;
-  case 0xee:sprintf(t, "pop   y");                                     break;
-  case 0xef:sprintf(t, "sleep");                                       break;
-  case 0xf0:sprintf(t, "beq   $%0.4x", __relb(op0, 2));                break;
-  case 0xf1:sprintf(t, "tcall 15");                                    break;
-  case 0xf2:sprintf(t, "clr7  $%0.3x", opdp0);                         break;
-  case 0xf3:sprintf(t, "bbc7  $%0.3x,$%0.4x", opdp0, __relb(op1, 3));  break;
-  case 0xf4:sprintf(t, "mov   a,$%0.3x+x", opdp0);                     break;
-  case 0xf5:sprintf(t, "mov   a,$%0.4x+x", opw);                       break;
-  case 0xf6:sprintf(t, "mov   a,$%0.4x+y", opw);                       break;
-  case 0xf7:sprintf(t, "mov   a,($%0.3x)+y", opdp0);                   break;
-  case 0xf8:sprintf(t, "mov   x,$%0.3x", opdp0);                       break;
-  case 0xf9:sprintf(t, "mov   x,$%0.3x+y", opdp0);                     break;
-  case 0xfa:sprintf(t, "mov   $%0.3x,$%0.3x", opdp1, opdp0);           break;
-  case 0xfb:sprintf(t, "mov   y,$%0.3x+x", opdp0);                     break;
-  case 0xfc:sprintf(t, "inc   y");                                     break;
-  case 0xfd:sprintf(t, "mov   y,a");                                   break;
-  case 0xfe:sprintf(t, "dbnz  y,$%0.4x", __relb(op0, 2));              break;
-  case 0xff:sprintf(t, "stop");                                        break;
-  }
-  t[strlen(t)] = ' ';
-  strcat(s, t);
-
-  sprintf(t, "A:%0.2x X:%0.2x Y:%0.2x SP:01%0.2x YA:%0.4x ",
-    regs.a, regs.x, regs.y, regs.sp, regs.ya);
-  strcat(s, t);
-
-  sprintf(t, "%c%c%c%c%c%c%c%c",
-    (regs.p.n)?'N':'n',
-    (regs.p.v)?'V':'v',
-    (regs.p.p)?'P':'p',
-    (regs.p.b)?'B':'b',
-    (regs.p.h)?'H':'h',
-    (regs.p.i)?'I':'i',
-    (regs.p.z)?'Z':'z',
-    (regs.p.c)?'C':'c');
-  strcat(s, t);
-}

src/base.h

@@ -1,65 +1,59 @@
-#define BSNES_VERSION "0.016"
-#define BSNES_TITLE "bsnes v" BSNES_VERSION
+#define BSNES_VERSION "0.024"
+#define BSNES_TITLE   "bsnes v" BSNES_VERSION
 
 #define MEMCORE bMemBus
-#define CPUCORE bCPU
-#define APUCORE bAPU
+#define CPUCORE sCPU
+#define SMPCORE sSMP
 #define DSPCORE bDSP
 #define PPUCORE bPPU
 
+//#define FAVOR_ACCURACY
+#define FAVOR_SPEED
+
 //game genie + pro action replay code support (~1-3% speed hit)
 #define CHEAT_SYSTEM
 
-//enable GZ, ZIP format support
-//#define GZIP_SUPPORT
-
-//enable JMA support
-//#define JMA_SUPPORT
-
-//debugging extensions (~10% speed hit)
-#define DEBUGGER
-
 //snes core polymorphism
-//(allow mem/cpu/apu/ppu overriding, ~10% speed hit)
+//(allow runtime cpu/smp/dsp/ppu/bus selection, ~10% speed hit)
 //#define POLYMORPHISM
 
-//this should be declared in the port-specific makefiles
-//#define ARCH_LSB
-//#define ARCH_MSB
-
-#ifndef ARCH_LSB
-  #ifndef ARCH_MSB
-    #define ARCH_LSB
-  #endif
-#endif
-
-#if defined(_WIN32)
-  #define _WIN32_
-  #undef _UNIX_
-#elif defined(__GNUC__)
-  #define _UNIX_
-  #undef _WIN32_
-#else
-  #error "unknown architecture"
-#endif
-
 #include "lib/libbase.h"
+
+#if defined(PROCESSOR_X86)
+  #define ARCH_LSB
+  #include "lib/libco_x86.h"
+#elif defined(PROCESSOR_X86_64)
+  #define ARCH_LSB
+  #include "lib/libco_x86_64.h"
+#elif defined(PROCESSOR_G5)
+  #define ARCH_MSB
+#else
+  #error "unsupported processor"
+#endif
+
+#include "lib/libfunctor.h"
+#include "lib/libsort.h"
+#include "lib/libarray.h"
 #include "lib/libvector.h"
 #include "lib/libstring.h"
 #include "lib/libconfig.h"
-#include "lib/libbpf.h"
-
-inline uint16 read16(uint8 *addr, uint pos) {
-#ifdef ARCH_LSB
-  return *((uint16*)(addr + pos));
-#else
-  return (addr[pos]) | (addr[pos + 1] << 8);
-#endif
-}
 
 //platform-specific global functions
-void alert(char *s, ...);
-void dprintf(char *s, ...);
+void alert(const char*, ...);
+void dprintf(const char*, ...);
+void dprintf(uint, const char*, ...);
+
+namespace source {
+  enum {
+    none = 0,
+    debug,
+    cpu,
+    ppu,
+    smp,
+    dsp,
+    bus,
+  };
+};
 
 //various class interfaces
 #include "interface.h"

src/cart/cart.cpp

@@ -1,329 +1,112 @@
 #include "../base.h"
+#include "database.cpp"
 
-void Cartridge::read_header() {
-  cart.srtc = false;
-  cart.sdd1 = false;
-  cart.c4   = false;
-  cart.dsp2 = false;
-  cart.obc1 = false;
+#include "cart_normal.cpp"
+#include "cart_st.cpp"
+#include "cart_stdual.cpp"
 
-  if(cart.header_index == 0x7fc0 && cart.rom_size >= 0x401000) {
-    cart.mapper = EXLOROM;
-  } else if(cart.header_index == 0x7fc0 && rom[cart.header_index + MAPPER] == 0x32) {
-    cart.mapper = EXLOROM;
-  } else if(cart.header_index == 0x7fc0) {
-    cart.mapper = LOROM;
-  } else if(cart.header_index == 0xffc0) {
-    cart.mapper = HIROM;
-  } else { //cart.header_index == 0x40ffc0
-    cart.mapper = EXHIROM;
-  }
+#include "cart_file.cpp"
+#include "cart_header.cpp"
 
-uint8 mapper   = rom[cart.header_index + MAPPER];
-uint8 rom_type = rom[cart.header_index + ROM_TYPE];
-  if(mapper == 0x35 && rom_type == 0x55) {
-    cart.srtc = true;
-  }
+Cartridge cartridge;
 
-  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
-    cart.sdd1 = true;
-  }
+void Cartridge::load_begin(uint cart_type) {
+  if(loaded() == true)return;
 
-  if(mapper == 0x20 && rom_type == 0xf3) {
-    cart.c4 = true;
-  }
+  info.type = cart_type;
 
-  if(mapper == 0x20 && rom_type == 0x05) {
-    cart.dsp2 = true;
-  }
+  info.srtc  = false;
+  info.sdd1  = false;
+  info.c4    = false;
+  info.dsp1  = false;
+  info.dsp2  = false;
+  info.obc1  = false;
+  info.st010 = false;
 
-  if(mapper == 0x30 && rom_type == 0x25) {
-    cart.obc1 = true;
-  }
+  info.dsp1_mapper = 0;
 
-  cart.cart_mmio = cart.c4 | cart.dsp2 | cart.obc1;
+  info.header_index = 0xffc0;
+  info.mapper = PCB;
+  strcpy(info.name, "");
+  strcpy(info.pcb,  "");
+  info.region = NTSC;
+  info.cart_mmio = false;
 
-  if(rom[cart.header_index + SRAM_SIZE] & 7) {
-    cart.sram_size = 1024 << (rom[cart.header_index + SRAM_SIZE] & 7);
-  } else {
-    cart.sram_size = 0;
-  }
+  info.rom_size = 0;
+  info.ram_size = 0;
 
-  cart.region = ((rom[cart.header_index + REGION] & 0x7f) < 2) ? NTSC : PAL;
-
-  memcpy(&cart.name, &rom[cart.header_index + CART_NAME], 21);
-  cart.name[21] = 0;
-
-  for(int i = 0; i < 22; i++) {
-    if(cart.name[i] & 0x80) {
-      cart.name[i] = '?';
-    }
+  file.count = 0;
+  for(int i = 0; i < 8; i++) {
+    strcpy(file.rom_name[i], "");
+    strcpy(file.ram_name[i], "");
+    file.rom_size[i] = 0;
+    file.ram_size[i] = 0;
+    file.rom_data[i] = 0;
+    file.ram_data[i] = 0;
   }
 }
 
-void Cartridge::find_header() {
-int32 score_lo = 0,
-      score_hi = 0,
-      score_ex = 0;
+void Cartridge::load(const char *rom_fn) {
+  if(!rom_fn || !*rom_fn)return;
 
-  if(rom_size < 0x010000) {
-  //cart too small to be anything else
-    cart.header_index = 0x007fc0;
-    return;
-  }
-
-  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20)score_lo++;
-  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21)score_hi++;
-
-  if(rom[0x7fc0 + ROM_TYPE] < 0x08)score_lo++;
-  if(rom[0xffc0 + ROM_TYPE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + ROM_SIZE] < 0x10)score_lo++;
-  if(rom[0xffc0 + ROM_SIZE] < 0x10)score_hi++;
-
-  if(rom[0x7fc0 + SRAM_SIZE] < 0x08)score_lo++;
-  if(rom[0xffc0 + SRAM_SIZE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + REGION] < 14)score_lo++;
-  if(rom[0xffc0 + REGION] < 14)score_hi++;
-
-  if(rom[0x7fc0 + LICENSE] < 3)score_lo++;
-  if(rom[0xffc0 + LICENSE] < 3)score_hi++;
-
-uint16 cksum, icksum;
-  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
-  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_lo += 8;
-  }
-
-  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
-  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_hi += 8;
-  }
-
-  if(rom_size < 0x401000) {
-    score_ex = 0;
-  } else {
-    if(rom[0x7fc0 + MAPPER] == 0x32)score_lo++;
-    else score_ex += 16;
-  }
-
-  if(score_lo >= score_hi && score_lo >= score_ex) {
-    cart.header_index = 0x007fc0;
-  } else if(score_hi >= score_ex) {
-    cart.header_index = 0x00ffc0;
-  } else {
-    cart.header_index = 0x40ffc0;
-  }
-}
-
-void Cartridge::load_sram() {
-  if(cart.sram_size == 0) {
-    sram = 0;
-    return;
-  }
-
-FileReader ff(sram_fn);
-  if(!ff.ready()) {
-    sram = (uint8*)malloc(cart.sram_size);
-    memset(sram, 0, cart.sram_size);
-    return;
-  }
-
-  sram = ff.read(cart.sram_size);
-}
-
-void Cartridge::save_sram() {
-  if(cart.sram_size == 0)return;
-
-FileWriter ff(sram_fn);
-  if(!ff.ready())return;
-
-  ff.write(sram, cart.sram_size);
-}
-
-void Cartridge::load_rom(Reader *rf) {
-  base_rom = rf->read();
-  rom_size = rf->size();
-
-  if((rom_size & 0x7fff) == 0x0200) {
-    rom = base_rom + 512;
-    rom_size -= 512;
-  } else {
-    rom = base_rom;
-  }
-
-  cart.rom_size = rom_size;
-
-  cart.crc32 = 0xffffffff;
-  for(int32 i = 0; i < cart.rom_size; i++) {
-    cart.crc32 = crc32_adjust(cart.crc32, rom[i]);
-  }
-  cart.crc32 = ~cart.crc32;
-}
-
-void Cartridge::patch_rom(Reader *rf) {
-uint8 *patch_data = rf->read();
-uint32 patch_size = rf->size();
-BPF bpf;
-  if(patch_size < 34)return;
-
-uint32 target;
-  target  = patch_data[BPF::INDEX_FORMAT + 0] <<  0;
-  target |= patch_data[BPF::INDEX_FORMAT + 1] <<  8;
-  target |= patch_data[BPF::INDEX_FORMAT + 2] << 16;
-  target |= patch_data[BPF::INDEX_FORMAT + 3] << 24;
-  if(target != BPF::FORMAT_SNES) {
-    alert("Warning: BPF patch file is not in SNES format!\n\n"
-      "The patch will still be applied, but it will not be "
-      "possible to determine whether the patch was created "
-      "against an image with a header or without a header.\n\n"
-      "bsnes is now forced to assume the patch was created "
-      "against a headerless source image. If this is not the "
-      "case, then patching will fail!\n\n"
-      "If you are the author of this patch, please recreate "
-      "the patch in SNES format.\n\n"
-      "If you are not the patch author, please contact the "
-      "author and ask them to create an SNES format BPF patch.");
-  }
-
-  if(bpf.apply_patch(patch_size, patch_data, rom_size, rom) == true) {
-    SafeFree(base_rom);
-  uint8 *temp = bpf.get_output_handle(rom_size);
-    base_rom = (uint8*)malloc(rom_size);
-    memcpy(base_rom, temp, rom_size);
-    rom = base_rom;
-    cart.rom_size = rom_size;
-  } else {
-    alert("Failed to apply patch.\n\nThis could be because the patch itself "
-      "does not match its internal checksum, because the ROM loaded does not "
-      "match the patch information for either the original or modified file, "
-      "or because the patched file does not match the checksum of either the "
-      "original or modified file that is stored inside the patch.\n\n"
-      "The original ROM image will be used instead.");
-  }
-  SafeFree(patch_data);
-}
-
-bool Cartridge::load(const char *fn) {
-  if(cart_loaded == true)return false;
-  if(strlen(fn) < 3)return false;
-
-  dprintf("* Loading \"%s\"...", fn);
-
-  strcpy(rom_fn, fn);
-
-  switch(Reader::detect(rom_fn)) {
-  case Reader::RF_NORMAL: {
-  FileReader ff(rom_fn);
-    if(!ff.ready()) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-    load_rom(static_cast<Reader*>(&ff));
-    break;
-  }
-#ifdef GZIP_SUPPORT
-  case Reader::RF_GZ: {
-  GZReader gf(rom_fn);
-    if(!gf.ready()) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-    load_rom(static_cast<Reader*>(&gf));
-    break;
-  }
-  case Reader::RF_ZIP: {
-  ZipReader zf(rom_fn);
-    load_rom(static_cast<Reader*>(&zf));
-    break;
-  }
-#endif
-#ifdef JMA_SUPPORT
-  case Reader::RF_JMA: {
-    try {
-    JMAReader jf(rom_fn);
-      load_rom(static_cast<Reader*>(&jf));
-    } catch(JMA::jma_errors jma_error) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-    break;
-  }
-#endif
-  }
-
-//remove ROM extension
-  strcpy(sram_fn, fn);
+char fn[4096], ram_fn[4096];
+  strcpy(fn, rom_fn);
+//correct folder slashes
   for(int i = strlen(fn) - 1; i >= 0; i--) {
-    if(sram_fn[i] == '.') {
-      sram_fn[i] = 0;
+    if(fn[i] == '\\')fn[i] = '/';
+  }
+
+uint i = file.count++;
+  strcpy(file.rom_name[i], fn);
+
+  strcpy(fn, rom_fn);
+//remove ROM extension
+  for(int i = strlen(fn) - 1; i >= 0; i--) {
+    if(fn[i] == '.') {
+      fn[i] = 0;
       break;
     }
   }
 
-//check for bpf patch
-#ifdef GZIP_SUPPORT
-  strcpy(patch_fn, sram_fn);
-  strcat(patch_fn, ".bpz");
-  if(fexists(patch_fn)) {
-  ZipReader zf(patch_fn);
-    patch_rom(static_cast<Reader*>(&zf));
-  } else {
-#endif
-    strcpy(patch_fn, sram_fn);
-    strcat(patch_fn, ".bpf");
-    if(fexists(patch_fn)) {
-    FileReader ff(patch_fn);
-      patch_rom(static_cast<Reader*>(&ff));
-    }
-#ifdef GZIP_SUPPORT
+  if(i == 0) {
+    strcpy(file.patch_name, fn);
+    strcat(file.patch_name, ".ups");
   }
-#endif
+  strcpy(fn, strptr(config::file_updatepath(fn, config::path.save)));
+  if(i == 0) {
+    strcpy(file.cheat_name, fn);
+    strcat(file.cheat_name, ".cht");
+  }
+  strcpy(file.ram_name[i], fn);
+  strcat(file.ram_name[i], ".");
+  strcat(file.ram_name[i], config::path.save_ext);
+}
 
-//add SRAM extension
-  strcat(sram_fn, ".");
-  strcat(sram_fn, config::fs.save_ext.sget());
-
-//override default path (current directory)?
-  if(strmatch(config::fs.save_path.sget(), "") == false) {
-  //remove path if fs.sram_path was specified
-  string new_fn, parts;
-    strcpy(new_fn, sram_fn);
-    replace(new_fn, "\\", "/");
-    split(parts, "/", new_fn);
-
-  //add new SRAM path
-    strcpy(new_fn, config::fs.save_path.sget());
-
-  //append fs.base_path if fs.sram_path is not fully-qualified path
-    if(strbegin(new_fn, "./") == true) {
-      strltrim(new_fn, "./");
-      strcpy(new_fn[1], new_fn[0]);
-      strcpy(new_fn[0], config::fs.base_path.sget());
-      strcat(new_fn[0], new_fn[1]);
-    }
-
-  //finally, append SRAM file name
-    strcat(new_fn, parts[count(parts) - 1]);
-    strcpy(sram_fn, strptr(new_fn));
+bool Cartridge::load_end() {
+  for(int i = 0; i < file.count; i++) {
+    load_file(file.rom_name[i], file.rom_data[i], file.rom_size[i]);
   }
 
-//load cheat file if it exists
-  strcpy(cheat_fn, sram_fn);
-  strrtrim(cheat_fn, config::fs.save_ext.sget());
-  strrtrim(cheat_fn, ".");
-  strcat(cheat_fn, ".cht");
-  if(fexists(cheat_fn) == true) {
-  FileReader ff(cheat_fn);
-    cheat.load(static_cast<Reader*>(&ff));
+  if(fexists(file.cheat_name) == true) {
+    cheat.clear();
+    cheat.load(file.cheat_name);
+  }
+
+  switch(info.type) {
+  case CART_NORMAL: {
+    load_rom_normal();
+    load_ram_normal();
+  } break;
+  case CART_ST: {
+    load_rom_st();
+    load_ram_st();
+  } break;
+  case CART_STDUAL: {
+    load_rom_stdual();
+    load_ram_stdual();
+  } break;
   }
 
-  find_header();
-  read_header();
-  load_sram();
   cart_loaded = true;
   r_mem->load_cart();
   return true;
@@ -334,18 +117,23 @@ bool Cartridge::unload() {
 
   r_mem->unload_cart();
 
-  if(base_rom) {
-    SafeFree(base_rom);
+  switch(info.type) {
+  case CART_NORMAL: {
+    save_ram_normal();
+  } break;
+  case CART_ST: {
+    save_ram_st();
+  } break;
+  case CART_STDUAL: {
+    save_ram_stdual();
+  } break;
   }
 
-  if(sram) {
-    save_sram();
-    SafeFree(sram);
-  }
+  safe_free(rom);
+  safe_free(ram);
 
-  if(cheat.count() > 0 || fexists(cheat_fn)) {
-  FileWriter ff(cheat_fn);
-    cheat.save(static_cast<Writer*>(&ff));
+  if(cheat.count() > 0 || fexists(file.cheat_name) == true) {
+    cheat.save(file.cheat_name);
     cheat.clear();
   }
 
@@ -354,12 +142,12 @@ bool Cartridge::unload() {
 }
 
 Cartridge::Cartridge() {
+  load_database();
+
   cart_loaded = false;
 
-  base_rom = 0;
-  rom      = 0;
-  sram     = 0;
-  rom_size = 0;
+  rom = 0;
+  ram = 0;
 }
 
 Cartridge::~Cartridge() {

src/cart/cart.h

@@ -1,10 +1,29 @@
 class Cartridge {
 public:
-bool cart_loaded;
-char rom_fn[4096], sram_fn[4096], cheat_fn[4096], patch_fn[4096];
 
-uint8 *base_rom, *rom, *sram;
-uint32 rom_size;
+/*****
+ * cart database
+ *****/
+
+#include "db/db.h"
+db_item dbi;
+  uint8 *database;
+  uint   database_size;
+  uint   database_blocksize;
+  void   load_database();
+  bool   read_database();
+
+//
+
+enum {
+  CART_NORMAL,
+  CART_ST,
+  CART_STDUAL,
+};
+
+bool cart_loaded;
+
+uint8 rom_header[512], *rom, *ram;
 
 enum {
 //header fields
@@ -12,34 +31,52 @@ enum {
   MAPPER    = 0x15,
   ROM_TYPE  = 0x16,
   ROM_SIZE  = 0x17,
-  SRAM_SIZE = 0x18,
+  RAM_SIZE  = 0x18,
   REGION    = 0x19,
   LICENSE   = 0x1a,
   VERSION   = 0x1b,
   ICKSUM    = 0x1c,
   CKSUM     = 0x1e,
+  RESL      = 0x3c,
+  RESH      = 0x3d,
 
 //regions
   NTSC = 0,
   PAL  = 1,
 
 //memory mappers
+  PCB     = 0x00,
   LOROM   = 0x20,
   HIROM   = 0x21,
   EXLOROM = 0x22,
   EXHIROM = 0x25,
+
+//special chip memory mappers
+  DSP1_LOROM_1MB = 1,
+  DSP1_LOROM_2MB = 2,
+  DSP1_HIROM     = 3,
 };
 
 struct {
+  uint   count;
+  char   cheat_name[4096], patch_name[4096];
+  char   rom_name[8][4096], ram_name[8][4096];
+  uint   rom_size[8],  ram_size[8];
+  uint8 *rom_data[8], *ram_data[8];
+} file;
+
+struct {
+  uint   type;
+
+//cart information
   uint32 crc32;
-  uint32 header_index;
+  char   name[128];
+  char   pcb[32];
 
-  char   name[32];
-  uint32 rom_size;
-  uint32 sram_size;
-  bool   region;
-
-  uint32 mapper;
+  uint   region;
+  uint   mapper;
+  uint   rom_size;
+  uint   ram_size;
 
 //set to true for games that need cart MMIO mapping (c4, dsp-n, ...),
 //for games that map outside the standard MMIO range of $2000-$5fff
@@ -47,18 +84,39 @@ struct {
   bool   srtc;
   bool   sdd1;
   bool   c4;
+  bool   dsp1;
   bool   dsp2;
   bool   obc1;
-} cart;
+  bool   st010;
+
+  uint   dsp1_mapper;
+
+//HiROM / LoROM specific code
+  uint   header_index;
+} info;
+
+  bool load_file(const char *fn, uint8 *&data, uint &size);
+  bool save_file(const char *fn, uint8 *data, uint size);
+
+  void load_rom_normal();
+  void load_ram_normal();
+  void save_ram_normal();
+
+  void load_rom_st();
+  void load_ram_st();
+  void save_ram_st();
+
+  void load_rom_stdual();
+  void load_ram_stdual();
+  void save_ram_stdual();
 
-  void load_rom(Reader *rf);
-  void patch_rom(Reader *rf);
-  void load_sram();
-  void save_sram();
   void find_header();
   void read_header();
+
   bool loaded() { return cart_loaded; }
-  bool load(const char *fn);
+  void load_begin(uint cart_type);
+  void load(const char *rom_fn);
+  bool load_end();
   bool unload();
 
   Cartridge();

src/cart/cart_file.cpp

@@ -0,0 +1,72 @@
+#include "../reader/filereader.h"
+
+#if defined(GZIP_SUPPORT)
+  #include "../reader/gzreader.h"
+  #include "../reader/zipreader.h"
+#endif
+
+#if defined(JMA_SUPPORT)
+  #include "../reader/jmareader.h"
+#endif
+
+bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size) {
+  dprintf("* Loading \"%s\"...", fn);
+
+  if(fexists(fn) == false) {
+    return false;
+  }
+
+  switch(Reader::detect(fn)) {
+
+  case Reader::RF_NORMAL: {
+  FileReader ff(fn);
+    if(!ff.ready()) {
+      alert("Error loading image file (%s)!", fn);
+      return false;
+    }
+    size = ff.size();
+    data = ff.read();
+  } break;
+
+#ifdef GZIP_SUPPORT
+  case Reader::RF_GZ: {
+  GZReader gf(fn);
+    if(!gf.ready()) {
+      alert("Error loading image file (%s)!", fn);
+      return false;
+    }
+    size = gf.size();
+    data = gf.read();
+  } break;
+
+  case Reader::RF_ZIP: {
+  ZipReader zf(fn);
+    size = zf.size();
+    data = zf.read();
+  } break;
+#endif
+
+#ifdef JMA_SUPPORT
+  case Reader::RF_JMA: {
+    try {
+    JMAReader jf(fn);
+      size = jf.size();
+      data = jf.read();
+    } catch(JMA::jma_errors jma_error) {
+      alert("Error loading image file (%s)!", fn);
+      return false;
+    }
+  } break;
+#endif
+
+  }
+
+  return true;
+}
+
+bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
+FileWriter ff(fn);
+  if(!ff.ready())return false;
+  ff.write(data, size);
+  return true;
+}

src/cart/cart_header.cpp

@@ -0,0 +1,153 @@
+void Cartridge::read_header() {
+  info.srtc = false;
+  info.sdd1 = false;
+  info.c4   = false;
+  info.dsp1 = false;
+  info.dsp2 = false;
+  info.obc1 = false;
+
+  info.dsp1_mapper = 0;
+
+  if(info.header_index == 0x7fc0 && info.rom_size >= 0x401000) {
+    info.mapper = EXLOROM;
+    strcpy(info.pcb, "UNL-EXLOROM");
+  } else if(info.header_index == 0x7fc0 && rom[info.header_index + MAPPER] == 0x32) {
+    info.mapper = EXLOROM;
+    strcpy(info.pcb, "UNL-EXLOROM");
+  } else if(info.header_index == 0x7fc0) {
+    info.mapper = LOROM;
+    strcpy(info.pcb, "UNL-LOROM");
+  } else if(info.header_index == 0xffc0) {
+    info.mapper = HIROM;
+    strcpy(info.pcb, "UNL-HIROM");
+  } else { //info.header_index == 0x40ffc0
+    info.mapper = EXHIROM;
+    strcpy(info.pcb, "UNL-EXHIROM");
+  }
+
+uint8 mapper   = rom[info.header_index + MAPPER];
+uint8 rom_type = rom[info.header_index + ROM_TYPE];
+  if(mapper == 0x35 && rom_type == 0x55) {
+    info.srtc = true;
+  }
+
+  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
+    info.sdd1 = true;
+  }
+
+  if(mapper == 0x20 && rom_type == 0xf3) {
+    info.c4 = true;
+  }
+
+  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
+    info.dsp1 = true;
+  }
+
+  if(info.dsp1 == true) {
+    if((mapper & 0x2f) == 0x20 && info.rom_size <= 0x100000) {
+      info.dsp1_mapper = DSP1_LOROM_1MB;
+    } else if((mapper & 0x2f) == 0x20) {
+      info.dsp1_mapper = DSP1_LOROM_2MB;
+    } else if((mapper & 0x2f) == 0x21) {
+      info.dsp1_mapper = DSP1_HIROM;
+    }
+  }
+
+  if(mapper == 0x20 && rom_type == 0x05) {
+    info.dsp2 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x25) {
+    info.obc1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6) {
+    info.st010 = true;
+  }
+
+  info.cart_mmio = info.c4 | info.dsp1 | info.dsp2 | info.obc1;
+
+  if(rom[info.header_index + RAM_SIZE] & 7) {
+    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
+  } else {
+    info.ram_size = 0;
+  }
+
+  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
+  info.name[21] = 0;
+
+  for(int i = 0; i < 22; i++) {
+    if(info.name[i] & 0x80) {
+      info.name[i] = '?';
+    }
+  }
+}
+
+void Cartridge::find_header() {
+int32 score_lo = 0,
+      score_hi = 0,
+      score_ex = 0;
+
+  if(info.rom_size < 0x010000) {
+  //cart too small to be anything but lorom
+    info.header_index = 0x007fc0;
+    return;
+  }
+
+  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20)score_lo++;
+  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21)score_hi++;
+
+  if(rom[0x7fc0 + ROM_TYPE] < 0x08)score_lo++;
+  if(rom[0xffc0 + ROM_TYPE] < 0x08)score_hi++;
+
+  if(rom[0x7fc0 + ROM_SIZE] < 0x10)score_lo++;
+  if(rom[0xffc0 + ROM_SIZE] < 0x10)score_hi++;
+
+  if(rom[0x7fc0 + RAM_SIZE] < 0x08)score_lo++;
+  if(rom[0xffc0 + RAM_SIZE] < 0x08)score_hi++;
+
+  if(rom[0x7fc0 + REGION] < 14)score_lo++;
+  if(rom[0xffc0 + REGION] < 14)score_hi++;
+
+  if(rom[0x7fc0 + LICENSE] < 3)score_lo++;
+  if(rom[0xffc0 + LICENSE] < 3)score_hi++;
+
+  if(rom[0x7fc0 + RESH] & 0x80)score_lo += 2;
+  if(rom[0xffc0 + RESH] & 0x80)score_hi += 2;
+
+uint16 cksum, icksum;
+  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
+  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_lo += 8;
+  }
+
+  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
+  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_hi += 8;
+  }
+
+  if(info.rom_size < 0x401000) {
+    score_ex = 0;
+  } else {
+    if(rom[0x7fc0 + MAPPER] == 0x32)score_lo++;
+    else score_ex += 16;
+  }
+
+  if(score_lo >= score_hi && score_lo >= score_ex) {
+    info.header_index = 0x007fc0;
+  } else if(score_hi >= score_ex) {
+    info.header_index = 0x00ffc0;
+  } else {
+    info.header_index = 0x40ffc0;
+  }
+}

src/cart/cart_normal.cpp

@@ -0,0 +1,66 @@
+void Cartridge::load_rom_normal() {
+uint size = 0;
+  for(int i = 0; i < file.count; i++) {
+    size += file.rom_size[i] - (((file.rom_size[i] & 0x7fff) == 512) ? 512 : 0);
+  }
+
+  info.rom_size = size;
+  rom = (uint8*)malloc(info.rom_size);
+  memset(rom, 0, info.rom_size);
+
+uint offset = 0;
+  for(int i = 0; i < file.count; i++) {
+  uint8 *data = file.rom_data[i] + (((file.rom_size[i] & 0x7fff) == 512) ? 512 : 0);
+  uint   size = file.rom_size[i] - (((file.rom_size[i] & 0x7fff) == 512) ? 512 : 0);
+    memcpy(rom + offset, data, size);
+    offset += size;
+    safe_free(file.rom_data[i]);
+  }
+
+  info.crc32 = crc32_calculate(rom, info.rom_size);
+
+  if(read_database() == true) {
+    info.srtc = false;
+    info.sdd1 = false;
+    info.c4   = false;
+    info.dsp1 = false;
+    info.dsp2 = false;
+    info.obc1 = false;
+
+    info.dsp1_mapper = 0;
+
+    info.header_index = 0xffc0;
+    info.mapper = PCB;
+    strcpy(info.name, dbi.name);
+    strcpy(info.pcb,  dbi.pcb);
+    info.region = NTSC;
+    info.cart_mmio = false;
+
+    info.rom_size = dbi.rom;
+    info.ram_size = dbi.ram;
+  } else {
+    find_header();
+    read_header();
+  }
+}
+
+void Cartridge::load_ram_normal() {
+  if(info.ram_size == 0) {
+    ram = 0;
+    return;
+  }
+
+  ram = (uint8*)malloc(info.ram_size);
+  memset(ram, 0xff, info.ram_size);
+
+  if(load_file(file.ram_name[0], file.ram_data[0], file.ram_size[0]) == true) {
+    memcpy(ram, file.ram_data[0], min(info.ram_size, file.ram_size[0]));
+    safe_free(file.ram_data[0]);
+  }
+}
+
+void Cartridge::save_ram_normal() {
+  if(info.ram_size == 0)return;
+
+  save_file(file.ram_name[0], ram, info.ram_size);
+}

src/cart/cart_st.cpp

@@ -0,0 +1,45 @@
+void Cartridge::load_rom_st() {
+uint8 *data;
+uint   size;
+string bios = config::file_updatepath("stbios.bin", config::path.bios);
+  info.rom_size = 0x200000;
+  rom = (uint8*)malloc(info.rom_size);
+  memset(rom, 0, info.rom_size);
+
+  load_file(strptr(bios), data, size);
+  memcpy(rom, data, min(size, 0x040000));
+  safe_free(data);
+
+  memcpy(rom + 0x100000, file.rom_data[0], min(file.rom_size[0], 0x100000));
+  safe_free(file.rom_data[0]);
+
+//
+  strcpy(info.name, "???");
+  strcpy(info.pcb,  "STC-SOLO");
+
+  info.mapper = PCB;
+  info.region = NTSC;
+
+  info.rom_size = 0x200000;
+  info.ram_size = 0x020000;
+//
+
+  info.crc32 = crc32_calculate(rom + 0x100000, file.rom_size[0]);
+  if(read_database() == true) {
+    strcpy(info.name, dbi.name);
+  }
+}
+
+void Cartridge::load_ram_st() {
+  ram = (uint8*)malloc(info.ram_size);
+  memset(ram, 0xff, info.ram_size);
+
+  if(load_file(file.ram_name[0], file.ram_data[0], file.ram_size[0]) == true) {
+    memcpy(ram, file.ram_data[0], min(file.ram_size[0], 0x020000));
+    safe_free(file.ram_data[0]);
+  }
+}
+
+void Cartridge::save_ram_st() {
+  save_file(file.ram_name[0], ram, 0x020000);
+}

src/cart/cart_stdual.cpp

@@ -0,0 +1,66 @@
+void Cartridge::load_rom_stdual() {
+uint8 *data;
+uint   size;
+string bios = config::file_updatepath("stbios.bin", config::path.bios);
+  info.rom_size = 0x300000;
+  rom = (uint8*)malloc(info.rom_size);
+  memset(rom, 0, info.rom_size);
+
+  load_file(strptr(bios), data, size);
+  memcpy(rom, data, min(size, 0x040000));
+  safe_free(data);
+
+  memcpy(rom + 0x100000, file.rom_data[0], min(file.rom_size[0], 0x100000));
+  safe_free(file.rom_data[0]);
+
+  memcpy(rom + 0x200000, file.rom_data[1], min(file.rom_size[1], 0x100000));
+  safe_free(file.rom_data[1]);
+
+char name_a[4096], name_b[4096];
+  strcpy(name_a, "???");
+  strcpy(name_b, "???");
+//
+  info.mapper = PCB;
+  info.region = NTSC;
+
+  info.rom_size = 0x300000;
+  info.ram_size = 0x040000;
+//
+
+  info.crc32 = crc32_calculate(rom + 0x100000, file.rom_size[0]);
+  if(read_database() == true) {
+    strcpy(name_a, dbi.name);
+  }
+
+  info.crc32 = crc32_calculate(rom + 0x200000, file.rom_size[1]);
+  if(read_database() == true) {
+    strcpy(name_b, dbi.name);
+  }
+
+//
+  info.crc32 = 0;
+  strcpy(info.name, name_a);
+  strcat(info.name, " + ");
+  strcat(info.name, name_b);
+  strcpy(info.pcb, "STC-DUAL");
+}
+
+void Cartridge::load_ram_stdual() {
+  ram = (uint8*)malloc(info.ram_size);
+  memset(ram, 0xff, info.ram_size);
+
+  if(load_file(file.ram_name[0], file.ram_data[0], file.ram_size[0]) == true) {
+    memcpy(ram + 0x000000, file.ram_data[0], min(file.ram_size[0], 0x020000));
+    safe_free(file.ram_data[0]);
+  }
+
+  if(load_file(file.ram_name[1], file.ram_data[1], file.ram_size[1]) == true) {
+    memcpy(ram + 0x020000, file.ram_data[1], min(file.ram_size[1], 0x020000));
+    safe_free(file.ram_data[1]);
+  }
+}
+
+void Cartridge::save_ram_stdual() {
+  save_file(file.ram_name[0], ram + 0x000000, 0x020000);
+  save_file(file.ram_name[1], ram + 0x020000, 0x020000);
+}

src/cart/database.cpp

@@ -0,0 +1,37 @@
+void Cartridge::load_database() {
+  database      = 0;
+  database_size = 0;
+
+FILE *fp;
+  fp = fopen("cart.db", "rb");
+  if(!fp)return;
+
+uint size = fsize(fp);
+  if(size < 8) {
+    fclose(fp);
+    return;
+  }
+
+  database = (uint8*)malloc(size);
+  fread(database, 1, size, fp);
+  fclose(fp);
+
+  database_blocksize = (database[6] << 0) | (database[7] << 8);
+  database_size      = (size - 8) / database_blocksize;
+}
+
+bool Cartridge::read_database() {
+uint i, crc32;
+  for(i = 0; i < database_size; i++) {
+  uint8 *p = database + 8 + (i * database_blocksize);
+    crc32  = *(p++) <<  0;
+    crc32 |= *(p++) <<  8;
+    crc32 |= *(p++) << 16;
+    crc32 |= *(p++) << 24;
+    if(crc32 == cartridge.info.crc32)break;
+  }
+  if(i >= database_size)return false;
+
+  db_read(dbi, database + 8 + (i * database_blocksize));
+  return true;
+}

src/cart/db/cartdb.txt

@@ -0,0 +1,113 @@
+[0xbb5c4238]
+name = "Bishoujo Senshi Sailor Moon Sailor Stars - Fuwa Fuwa Panic 2 (Japan)"
+pcb  = "STC-????"
+rom  =  8mbit
+ram  = 32kbit
+
+[0x8eb753f3]
+name = "Crayon Shin-chan - Nagagutsu Dobon!! (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x7aedd703]
+name = "Der Langrisser (Japan) [!]"
+pcb  = "SHVC-1A3M-30"
+rom  = 16mbit
+ram  = 64kbit
+
+[0x19bdcb19]
+name = "Derby Stallion '96 (Japan) [!]"
+pcb  = "BSC-1A5M-01"
+rom  =  24mbit
+ram  = 256kbit
+
+[0x4296500d]
+name = "Gegege no Kitarou - Youkai Donjara (Japan)"
+pcb  = "STC-????"
+rom  =  4mbit
+ram  = 16kbit
+
+[0x14c66fca]
+name = "Gekisou Sentai Car Rangers (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x32b2b3dd]
+name = "Poi Poi Ninja World (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x9684526d]
+name = "Romancing SaGa (Japan) (V1.1) [!]"
+pcb  = "SHVC-1A3B-12"
+rom  =  8mbit
+ram  = 64kbit
+
+[0xafd74dcb]
+name = "SD Gundam Generation A - Ichinen Sensouki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x48ecae44]
+name = "SD Gundam Generation B - Grips Senki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x72b4235f]
+name = "SD Gundam Generation C - Axis Senki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x792d884c]
+name = "SD Gundam Generation D - Babylonia Kenkoku Senki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0xefd3a865]
+name = "SD Gundam Generation E - Zanskar Senki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0xc5dfa8fd]
+name = "SD Gundam Generation F - Colony Kakutouki (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x43ad5a45]
+name = "SD Ultra Battle - Seven Densetsu (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0x04939d14]
+name = "SD Ultra Battle - Ultra Densetsu (Japan)"
+pcb  = "STC-????"
+rom  = 4mbit
+ram  = 8kbit
+
+[0xa5c0045e]
+name = "Secret of Evermore (USA) [!]"
+pcb  = "SHVC-1J3M-20"
+rom  = 32mbit
+ram  = 64kbit
+
+[0x5ebf7246]
+name = "Sound Novel Tsukuru (Japan) [!]"
+pcb  = "BSC-1A7M-10"
+rom  =  24mbit
+ram  = 512kbit
+
+[0x64a91e64]
+name = "Wanderers from Ys (USA) [!]"
+pcb  = "SHVC-1A3B-12"
+rom  =  8mbit
+ram  = 64kbit

src/cart/db/cc.bat

@@ -0,0 +1,3 @@
+cl /nologo /O2 dbcreate.cpp
+@pause
+@del *.obj

src/cart/db/clean.bat

@@ -0,0 +1 @@
+@del *.exe

src/cart/db/create.bat

@@ -0,0 +1,2 @@
+dbcreate
+@copy cart.db ..\..\..\cart.db

src/cart/db/db.h

@@ -0,0 +1,47 @@
+struct db_item {
+  uint32 crc32;
+  char   name[128];
+  char   pcb [32];
+  uint32 rom;
+  uint32 ram;
+};
+
+void db_write(FILE *fp, db_item &dbi) {
+  fputc(dbi.crc32 >>  0, fp);
+  fputc(dbi.crc32 >>  8, fp);
+  fputc(dbi.crc32 >> 16, fp);
+  fputc(dbi.crc32 >> 24, fp);
+
+  fwrite(dbi.name, 1, 128, fp);
+  fwrite(dbi.pcb,  1,  32, fp);
+
+  fputc(dbi.rom >>  0, fp);
+  fputc(dbi.rom >>  8, fp);
+  fputc(dbi.rom >> 16, fp);
+  fputc(dbi.rom >> 24, fp);
+
+  fputc(dbi.ram >>  0, fp);
+  fputc(dbi.ram >>  8, fp);
+  fputc(dbi.ram >> 16, fp);
+  fputc(dbi.ram >> 24, fp);
+}
+
+void db_read(db_item &dbi, uint8 *data) {
+  dbi.crc32  = (*data++) <<  0;
+  dbi.crc32 |= (*data++) <<  8;
+  dbi.crc32 |= (*data++) << 16;
+  dbi.crc32 |= (*data++) << 24;
+
+  memcpy(dbi.name, data, 128); dbi.name[127] = 0; data += 128;
+  memcpy(dbi.pcb,  data,  32); dbi.pcb [ 31] = 0; data +=  32;
+
+  dbi.rom  = (*data++) <<  0;
+  dbi.rom |= (*data++) <<  8;
+  dbi.rom |= (*data++) << 16;
+  dbi.rom |= (*data++) << 24;
+
+  dbi.ram  = (*data++) <<  0;
+  dbi.ram |= (*data++) <<  8;
+  dbi.ram |= (*data++) << 16;
+  dbi.ram |= (*data++) << 24;
+}

src/cart/db/dbcreate.cpp

@@ -0,0 +1,117 @@
+#include "../../lib/libbase.h"
+#include "../../lib/libvector.h"
+#include "../../lib/libstring.h"
+
+#include "../../lib/libstring.cpp"
+
+#include "db.h"
+
+FILE *fp;
+
+uint decode_size(string &str) {
+//hex encoding
+  if(strbegin(str, "0x")) {
+    strltrim(str, "0x");
+    return strhex(str);
+  }
+
+//mbit encoding
+  if(strend(str, "mbit")) {
+    strrtrim(str, "mbit");
+    return strdec(str) * 1024 * 1024 / 8;
+  }
+
+//kbit encoding
+  if(strend(str, "kbit")) {
+    strrtrim(str, "kbit");
+    return strdec(str) * 1024 / 8;
+  }
+
+//decimal encoding
+  return strdec(str);
+}
+
+void build_block(string &block) {
+stringarray line, hashpart, part;
+  split(line, "\n", block);
+
+  if(strbegin(line[0], "[") == false) {
+    printf("error: invalid block detected: '%s'\n", strptr(line[0]));
+    return;
+  }
+
+  strltrim(line[0], "[");
+  strrtrim(line[0], "]");
+  replace(line[0], "0x", "");
+  split(hashpart, ",", line[0]);
+
+db_item dbi;
+  dbi.crc32 = 0;
+ *dbi.name  = 0;
+ *dbi.pcb   = 0;
+  dbi.rom   = 0;
+  dbi.ram   = 0;
+
+  for(int i = 1; i < count(line); i++) {
+  uint pos;
+    if(strpos(line[i], ";", pos) == true) {
+      strset(line[i], pos, 0);
+    }
+
+    if(line[i] == "")continue;
+
+    split(part, "=", line[i]);
+    strunquote(part[1]);
+
+    if(part[0] == "name") {
+      strncpy(dbi.name, strptr(part[1]), 128);
+      dbi.name[128] = 0;
+    }
+
+    if(part[0] == "pcb") {
+      strncpy(dbi.pcb, strptr(part[1]), 32);
+      dbi.pcb[31] = 0;
+    }
+
+    if(part[0] == "rom") {
+      dbi.rom = decode_size(part[1]);
+    }
+
+    if(part[0] == "ram") {
+      dbi.ram = decode_size(part[1]);
+    }
+  }
+
+  for(int i = 0; i < count(hashpart); i++) {
+    dbi.crc32 = strhex(hashpart[i]);
+    db_write(fp, dbi);
+  }
+}
+
+void build_database() {
+stringarray data, block;
+  if(strfread(data, "cartdb.txt") == false)return;
+
+  fp = fopen("cart.db", "wb");
+  fprintf(fp, "SNESDB");
+
+uint blocksize = 4 + 128 + 32 + 4 + 4;
+  fputc(blocksize >> 0, fp);
+  fputc(blocksize >> 8, fp);
+
+  replace (data, "\r", "");
+  qreplace(data, " ",  "");
+  qreplace(data, "\t", "");
+  split(block, "\n\n", data);
+
+  for(int i = 0; i < count(block); i++) {
+    build_block(block[i]);
+  }
+
+  fclose(fp);
+}
+
+int main() {
+  build_database();
+  return 0;
+}

src/cc.bat

@@ -0,0 +1,4 @@
+::@make -r PLATFORM=win-visualc-lui
+@make -r PLATFORM=win-visualc-lui GZIP_SUPPORT=true JMA_SUPPORT=true
+@move bsnes.exe ../bsnes.exe>nul
+@pause

src/cc.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+make PLATFORM=x-gcc-lui

src/cheat/cheat.cpp

@@ -1,4 +1,7 @@
 #include "../base.h"
+#include "../reader/filereader.h"
+
+Cheat cheat;
 
 /*****
  * string <> binary code translation routines
@@ -7,7 +10,7 @@
  *****/
 
 bool Cheat::decode(char *str, uint32 &addr, uint8 &data, uint8 &type) {
-string t, part;
+stringarray t, part;
   strcpy(t, str);
   strlower(t);
   if(strlen(t) == 8 || (strlen(t) == 9 && strptr(t)[6] == ':')) {
@@ -266,19 +269,20 @@ void Cheat::disable(uint32 n) {
  * cheat file manipulation routines
  *****/
 
-bool Cheat::load(Reader *rf) {
-  if(!rf->ready())return false;
+bool Cheat::load(const char *fn) {
+FileReader rf(fn);
+  if(!rf.ready())return false;
 
-uint8 *raw_data = rf->read();
-string data;
-  raw_data[rf->size()] = 0;
+uint8 *raw_data = rf.read();
+stringarray data, line;
+  raw_data[rf.size()] = 0;
   strcpy(data, (char*)raw_data);
-  SafeFree(raw_data);
+  safe_free(raw_data);
   replace(data, "\r\n", "\n");
-string line;
+
   split(line, "\n", data);
   for(int i = 0; i < ::count(line); i++) {
-  string part;
+  stringarray part;
   uint8  en = *(strptr(line[i]));
     if(en == '+') {
       strltrim(line[i], "+");
@@ -297,8 +301,9 @@ string line;
   return true;
 }
 
-bool Cheat::save(Writer *wf) {
-  if(!wf->ready())return false;
+bool Cheat::save(const char *fn) {
+FileWriter wf(fn);
+  if(!wf.ready())return false;
 
 string data;
 char   t[4096];
@@ -308,7 +313,7 @@ char   t[4096];
     strcat(data, t);
   }
 
-  wf->write((uint8*)strptr(data), strlen(data));
+  wf.write((uint8*)strptr(data), strlen(data));
   return true;
 }
 

src/cheat/cheat.h

@@ -38,8 +38,8 @@ public:
   bool  enabled(uint32 n);
   void  enable (uint32 n);
   void  disable(uint32 n);
-  bool  load(Reader *rf);
-  bool  save(Writer *wf);
+  bool  load(const char *fn);
+  bool  save(const char *fn);
   void  clear();
 
   Cheat();

src/chip/c4/c4.cpp

@@ -7,6 +7,8 @@
 
 #include "../../base.h"
 
+C4 *c4;
+
 #include "c4data.cpp"
 #include "c4fn.cpp"
 #include "c4oam.cpp"

src/chip/c4/c4.h

@@ -92,3 +92,5 @@ public:
 
   C4();
 };
+
+extern C4 *c4;

src/chip/c4/c4oam.cpp

@@ -1,7 +1,7 @@
 //Build OAM
 void C4::op00_00() {
 uint32 oamptr = ram[0x626] << 2;
-  for(int32 i=0x1fd;i>oamptr && i>=0;i-=4) {
+  for(int32 i = 0x1fd; i > oamptr && i >= 0; i -= 4) {
   //clear oam-to-be
     if(i >= 0)ram[i] = 0xe0;
   }
@@ -19,58 +19,55 @@ uint8  sprcount;
 
   sprcount = 128 - ram[0x626];
 uint8 offset = (ram[0x626] & 3) * 2;
-  for(int pri=0x30;pri>=0;pri-=0x10) {
-  uint32 srcptr = 0x220;
-    for(int i=ram[0x620];i>0 && sprcount>0;i--, srcptr+=16) {
-      if((ram[srcptr + 4] & 0x30) != pri)continue;
-      sprx = readw(srcptr)     - globalx;
-      spry = readw(srcptr + 2) - globaly;
-      sprname = ram[srcptr + 5];
-      sprattr = ram[srcptr + 4] | ram[srcptr + 6];
+uint32 srcptr = 0x220;
+  for(int i = ram[0x620]; i > 0 && sprcount > 0; i--, srcptr += 16) {
+    sprx = readw(srcptr)     - globalx;
+    spry = readw(srcptr + 2) - globaly;
+    sprname = ram[srcptr + 5];
+    sprattr = ram[srcptr + 4] | ram[srcptr + 6];
 
-    uint32 spraddr = readl(srcptr + 7);
-      if(r_mem->read(spraddr)) {
-      int16 x, y;
-        for(int sprcnt=r_mem->read(spraddr++);sprcnt>0 && sprcount>0;sprcnt--, spraddr+=4) {
-          x = (int8)r_mem->read(spraddr + 1);
-          if(sprattr & 0x40) {
-            x = -x - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
+  uint32 spraddr = readl(srcptr + 7);
+    if(r_mem->read(spraddr)) {
+    int16 x, y;
+      for(int sprcnt = r_mem->read(spraddr++); sprcnt > 0 && sprcount > 0; sprcnt--, spraddr += 4) {
+        x = (int8)r_mem->read(spraddr + 1);
+        if(sprattr & 0x40) {
+          x = -x - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
+        }
+        x += sprx;
+        if(x >= -16 && x <= 272) {
+          y = (int8)r_mem->read(spraddr + 2);
+          if(sprattr & 0x80) {
+            y = -y - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
           }
-          x += sprx;
-          if(x >= -16 && x <= 272) {
-            y = (int8)r_mem->read(spraddr + 2);
-            if(sprattr & 0x80) {
-              y = -y - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
-            }
-            y += spry;
-            if(y >= -16 && y <= 224) {
-              ram[oamptr    ] = (uint8)x;
-              ram[oamptr + 1] = (uint8)y;
-              ram[oamptr + 2] = sprname + r_mem->read(spraddr + 3);
-              ram[oamptr + 3] = sprattr ^ (r_mem->read(spraddr) & 0xc0);
-              ram[oamptr2] &= ~(3 << offset);
-              if(x & 0x100)ram[oamptr2] |= 1 << offset;
-              if(r_mem->read(spraddr) & 0x20)ram[oamptr2] |= 2 << offset;
-              oamptr += 4;
-              sprcount--;
-              offset = (offset + 2) & 6;
-              if(!offset)oamptr2++;
-            }
+          y += spry;
+          if(y >= -16 && y <= 224) {
+            ram[oamptr    ] = (uint8)x;
+            ram[oamptr + 1] = (uint8)y;
+            ram[oamptr + 2] = sprname + r_mem->read(spraddr + 3);
+            ram[oamptr + 3] = sprattr ^ (r_mem->read(spraddr) & 0xc0);
+            ram[oamptr2] &= ~(3 << offset);
+            if(x & 0x100)ram[oamptr2] |= 1 << offset;
+            if(r_mem->read(spraddr) & 0x20)ram[oamptr2] |= 2 << offset;
+            oamptr += 4;
+            sprcount--;
+            offset = (offset + 2) & 6;
+            if(!offset)oamptr2++;
           }
         }
-      } else if(sprcount > 0) {
-        ram[oamptr    ] = (uint8)sprx;
-        ram[oamptr + 1] = (uint8)spry;
-        ram[oamptr + 2] = sprname;
-        ram[oamptr + 3] = sprattr;
-        ram[oamptr2] &= ~(3 << offset);
-        if(sprx & 0x100)ram[oamptr2] |= 3 << offset;
-        else ram[oamptr2] |= 2 << offset;
-        oamptr += 4;
-        sprcount--;
-        offset = (offset + 2) & 6;
-        if(!offset)oamptr2++;
       }
+    } else if(sprcount > 0) {
+      ram[oamptr    ] = (uint8)sprx;
+      ram[oamptr + 1] = (uint8)spry;
+      ram[oamptr + 2] = sprname;
+      ram[oamptr + 3] = sprattr;
+      ram[oamptr2] &= ~(3 << offset);
+      if(sprx & 0x100)ram[oamptr2] |= 3 << offset;
+      else ram[oamptr2] |= 2 << offset;
+      oamptr += 4;
+      sprcount--;
+      offset = (offset + 2) & 6;
+      if(!offset)oamptr2++;
     }
   }
 }
@@ -178,13 +175,11 @@ uint32 waveptr = read(0x1f83);
 uint16 mask1   = 0xc0c0;
 uint16 mask2   = 0x3f3f;
 
-int32 i, j;
-int16 height, temp;
-  for(j = 0; j < 0x10; j++) {
+  for(int j = 0; j < 0x10; j++) {
     do {
-      height = -((int8)ram[waveptr + 0xb00]) - 16;
-      for(i = 0; i < 40; i++) {
-        temp = readw(destptr + wave_data[i]) & mask2;
+    int16 height = -((int8)read(waveptr + 0xb00)) - 16;
+      for(int i = 0; i < 40; i++) {
+      uint16 temp = readw(destptr + wave_data[i]) & mask2;
         if(height >= 0) {
           if(height < 8) {
             temp |= mask1 & readw(0xa00 + height * 2);
@@ -202,22 +197,22 @@ int16 height, temp;
     destptr += 16;
 
     do {
-      height = -((int8)ram[waveptr + 0xb00]) - 16;
-      for(i = 0; i < 40; i++) {
-        temp = readw(destptr + wave_data[i]) & mask2;
+    int16 height = -((int8)read(waveptr + 0xb00)) - 16;
+      for(int i = 0; i < 40; i++) {
+      uint16 temp = readw(destptr + wave_data[i]) & mask2;
         if(height >= 0) {
           if(height < 8) {
             temp |= mask1 & readw(0xa10 + height * 2);
           } else {
             temp |= mask1 & 0xff00;
           }
-          writew(destptr + wave_data[i], temp);
-          height++;
         }
-        waveptr = (waveptr + 1) & 0x7f;
-        mask1   = (mask1 >> 2) | (mask1 << 6);
-        mask2   = (mask2 >> 2) | (mask2 << 6);
+        writew(destptr + wave_data[i], temp);
+        height++;
       }
+      waveptr = (waveptr + 1) & 0x7f;
+      mask1   = (mask1 >> 2) | (mask1 << 6);
+      mask2   = (mask2 >> 2) | (mask2 << 6);
     } while(mask1 != 0xc0c0);
     destptr += 16;
   }

src/chip/dsp1/dsp1.cpp

@@ -0,0 +1,57 @@
+#include "../../base.h"
+
+DSP1 *dsp1;
+
+#include "dsp1emu.cpp"
+
+void DSP1::init() {}
+void DSP1::enable() {}
+
+void DSP1::power() {
+  reset();
+}
+
+void DSP1::reset() {
+  dsp1.reset();
+}
+
+/*****
+ * addr_decode()
+ * determine whether address is accessing
+ * data register (DR) or status register (SR)
+ * -- 0 (false) = DR
+ * -- 1 (true ) = SR
+ *
+ * note: there is no need to bounds check addresses,
+ * as memory mapper will not allow DSP1 accesses outside
+ * of expected ranges
+ *****/
+bool DSP1::addr_decode(uint16 addr) {
+  switch(cartridge.info.dsp1_mapper) {
+
+  case Cartridge::DSP1_LOROM_1MB:
+  //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
+    return (addr >= 0xc000);
+
+  case Cartridge::DSP1_LOROM_2MB:
+  //$[60-6f]:[0000-3fff] = DR, $[60-6f]:[4000-7fff] = SR
+    return (addr >= 0x4000);
+
+  case Cartridge::DSP1_HIROM:
+  //$[00-1f]:[6000-6fff] = DR, $[00-1f]:[7000-7fff] = SR
+    return (addr >= 0x7000);
+
+  }
+
+  return 0;
+}
+
+uint8 DSP1::read(uint16 addr) {
+  return (addr_decode(addr) == 0) ? dsp1.getDr() : dsp1.getSr();
+}
+
+void DSP1::write(uint16 addr, uint8 data) {
+  if(addr_decode(addr) == 0) {
+    dsp1.setDr(data);
+  }
+}

src/chip/dsp1/dsp1.h

@@ -0,0 +1,18 @@
+#include "dsp1emu.h"
+
+class DSP1 {
+private:
+Dsp1 dsp1;
+
+public:
+  void   init();
+  void   enable();
+  void   power();
+  void   reset();
+
+  bool   addr_decode(uint16 addr);
+  uint8  read (uint16 addr);
+  void   write(uint16 addr, uint8 data);
+};
+
+extern DSP1 *dsp1;

src/chip/dsp1/dsp1emu.h

@@ -0,0 +1,127 @@
+// DSP-1's emulation code
+//
+// Based on research by Overload, The Dumper, Neviksti and Andreas Naive
+// Date: June 2006
+
+#ifndef __DSP1EMUL_H
+#define __DSP1EMUL_H
+
+#define DSP1_VERSION 0x0102
+
+class Dsp1
+{
+   public:
+      // The DSP-1 status register has 16 bits, but only
+      // the upper 8 bits can be accessed from an external device, so all these
+      // positions are referred to the upper byte (bits D8 to D15)
+      enum SrFlags {DRC=0x04, DRS=0x10, RQM=0x80};
+
+      // According to Overload's docs, these are the meanings of the flags:
+      // DRC: The Data Register Control (DRC) bit specifies the data transfer length to and from the host CPU.
+      //   0: Data transfer to and from the DSP-1 is 16 bits.
+      //   1: Data transfer to and from the DSP-1 is 8 bits.
+      // DRS: The Data Register Status (DRS) bit indicates the data transfer status in the case of transfering 16-bit data.
+      //   0: Data transfer has terminated.
+      //   1: Data transfer in progress.
+      // RQM: The Request for Master (RQM) indicates that the DSP1 is requesting host CPU for data read/write.
+      //   0: Internal Data Register Transfer.
+      //   1: External Data Register Transfer.
+
+      Dsp1();
+      uint8 getSr();            // return the status register's high byte
+      uint8 getDr();
+      void setDr(uint8 iDr);
+      void reset();
+
+   private:
+      enum FsmMajorState {WAIT_COMMAND, READ_DATA, WRITE_DATA};
+      enum MaxDataAccesses {MAX_READS=7, MAX_WRITES=1024};
+
+      struct Command {
+         void (Dsp1::*callback)(int16 *, int16 *);
+         unsigned int reads;
+         unsigned int writes;
+      };
+
+      static const Command mCommandTable[];
+      static const int16 MaxAZS_Exp[16];
+      static const int16 SinTable[];
+      static const int16 MulTable[];
+      static const uint16 DataRom[];
+
+      struct SharedData { // some RAM variables shared between commands
+         int16 MatrixA[3][3];          // attitude matrix A
+         int16 MatrixB[3][3];
+         int16 MatrixC[3][3];
+         int16 CentreX, CentreY, CentreZ;   // center of projection
+         int16 CentreZ_C, CentreZ_E;
+         int16 VOffset;                     // vertical offset of the screen with regard to the centre of projection
+         int16 Les, C_Les, E_Les;
+         int16 SinAas, CosAas;
+         int16 SinAzs, CosAzs;
+         int16 SinAZS, CosAZS;
+         int16 SecAZS_C1, SecAZS_E1;
+         int16 SecAZS_C2, SecAZS_E2;
+         int16 Nx, Ny, Nz;    // normal vector to the screen (norm 1, points toward the center of projection)
+         int16 Gx, Gy, Gz;    // center of the screen (global coordinates)
+         int16 Hx, Hy;        // horizontal vector of the screen (Hz=0, norm 1, points toward the right of the screen)
+         int16 Vx, Vy, Vz;    // vertical vector of the screen (norm 1, points toward the top of the screen) 
+
+      } shared;
+
+      uint8 mSr;            // status register
+      int mSrLowByteAccess;
+      uint16 mDr;           // "internal" representation of the data register
+      FsmMajorState mFsmMajorState;     // current major state of the FSM
+      uint8 mCommand;                  // current command processed by the FSM
+      uint8 mDataCounter;                 // #uint16 read/writes counter used by the FSM
+      int16 mReadBuffer[MAX_READS];
+      int16 mWriteBuffer[MAX_WRITES];
+      bool mFreeze;                   // need explanation?  ;)
+
+      void fsmStep(bool read, uint8 &data);            // FSM logic
+
+      // commands
+      void memoryTest(int16 *input, int16 *output);
+      void memoryDump(int16 *input, int16 *output);
+      void memorySize(int16 *input, int16 *output);
+      void multiply(int16* input, int16* output);
+      void multiply2(int16* input, int16* output);
+      void inverse(int16 *input, int16 *output);
+      void triangle(int16 *input, int16 *output);
+      void radius(int16 *input, int16 *output);
+      void range(int16 *input, int16 *output);
+      void range2(int16 *input, int16 *output);
+      void distance(int16 *input, int16 *output);
+      void rotate(int16 *input, int16 *output);
+      void polar(int16 *input, int16 *output);
+      void attitudeA(int16 *input, int16 *output);
+      void attitudeB(int16 *input, int16 *output);
+      void attitudeC(int16 *input, int16 *output);
+      void objectiveA(int16 *input, int16 *output);
+      void objectiveB(int16 *input, int16 *output);
+      void objectiveC(int16 *input, int16 *output);
+      void subjectiveA(int16 *input, int16 *output);
+      void subjectiveB(int16 *input, int16 *output);
+      void subjectiveC(int16 *input, int16 *output);
+      void scalarA(int16 *input, int16 *output);
+      void scalarB(int16 *input, int16 *output);
+      void scalarC(int16 *input, int16 *output);
+      void gyrate(int16 *input, int16 *output);
+      void parameter(int16 *input, int16 *output);
+      void raster(int16 *input, int16 *output);
+      void target(int16 *input, int16 *output);
+      void project(int16 *input, int16 *output);
+
+      // auxiliar functions
+      int16 sin(int16 Angle);
+      int16 cos(int16 Angle);
+      void inverse(int16 Coefficient, int16 Exponent, int16 &iCoefficient, int16 &iExponent);
+      int16 denormalizeAndClip(int16 C, int16 E);
+      void normalize(int16 m, int16 &Coefficient, int16 &Exponent);
+      void normalizeDouble(int32 Product, int16 &Coefficient, int16 &Exponent);
+      int16 shiftR(int16 C, int16 E);
+}; 
+
+#endif
+

src/chip/dsp2/dsp2.cpp

@@ -1,4 +1,7 @@
 #include "../../base.h"
+
+DSP2 *dsp2;
+
 #include "dsp2_op.cpp"
 
 void DSP2::init() {}

src/chip/dsp2/dsp2.h

@@ -1,13 +1,13 @@
 class DSP2 {
 public:
 struct {
-  bool waiting_for_command;
-  uint command;
-  uint in_count,  in_index;
-  uint out_count, out_index;
+  bool   waiting_for_command;
+  uint   command;
+  uint   in_count,  in_index;
+  uint   out_count, out_index;
 
-  uint8 parameters[512];
-  uint8 output[512];
+  uint8  parameters[512];
+  uint8  output[512];
 
   uint8  op05transparent;
   bool   op05haslen;
@@ -20,6 +20,7 @@ struct {
   int    op0doutlen;
   int    op0dinlen;
 } status;
+
   void   init();
   void   enable();
   void   power();
@@ -38,3 +39,5 @@ struct {
   DSP2();
   ~DSP2();
 };
+
+extern DSP2 *dsp2;

src/chip/obc1/obc1.cpp

@@ -1,5 +1,7 @@
 #include "../../base.h"
 
+OBC1 *obc1;
+
 void OBC1::init() {}
 void OBC1::enable() {}
 
@@ -8,34 +10,34 @@ void OBC1::power() {
 }
 
 void OBC1::reset() {
-  memset(cartridge.sram, 0xff, 0x2000);
-  status.baseptr = (cartridge.sram[0x1ff5] & 1) ? 0x1800 : 0x1c00;
-  status.address = (cartridge.sram[0x1ff6] & 0x7f);
-  status.shift   = (cartridge.sram[0x1ff6] & 3) << 1;
+  memset(cartridge.ram, 0xff, 0x2000);
+  status.baseptr = (cartridge.ram[0x1ff5] & 1) ? 0x1800 : 0x1c00;
+  status.address = (cartridge.ram[0x1ff6] & 0x7f);
+  status.shift   = (cartridge.ram[0x1ff6] & 3) << 1;
 }
 
 uint8 OBC1::read(uint16 addr) {
   addr &= 0x1fff;
 
   if((addr & 0x1ff8) != 0x1ff0) {
-    return cartridge.sram[addr];
+    return cartridge.ram[addr];
   }
 
   switch(addr) {
   case 0x1ff0:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 0];
+    return cartridge.ram[status.baseptr + (status.address << 2) + 0];
   case 0x1ff1:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 1];
+    return cartridge.ram[status.baseptr + (status.address << 2) + 1];
   case 0x1ff2:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 2];
+    return cartridge.ram[status.baseptr + (status.address << 2) + 2];
   case 0x1ff3:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 3];
+    return cartridge.ram[status.baseptr + (status.address << 2) + 3];
   case 0x1ff4:
-    return cartridge.sram[status.baseptr + (status.address >> 2) + 0x200];
+    return cartridge.ram[status.baseptr + (status.address >> 2) + 0x200];
   case 0x1ff5:
   case 0x1ff6:
   case 0x1ff7:
-    return cartridge.sram[addr];
+    return cartridge.ram[addr];
   }
 
 //never used, blocks compiler warning
@@ -46,40 +48,40 @@ void OBC1::write(uint16 addr, uint8 data) {
   addr &= 0x1fff;
 
   if((addr & 0x1ff8) != 0x1ff0) {
-    cartridge.sram[addr] = data;
+    cartridge.ram[addr] = data;
     return;
   }
 
   switch(addr) {
   case 0x1ff0:
-    cartridge.sram[status.baseptr + (status.address << 2) + 0] = data;
+    cartridge.ram[status.baseptr + (status.address << 2) + 0] = data;
     break;
   case 0x1ff1:
-    cartridge.sram[status.baseptr + (status.address << 2) + 1] = data;
+    cartridge.ram[status.baseptr + (status.address << 2) + 1] = data;
     break;
   case 0x1ff2:
-    cartridge.sram[status.baseptr + (status.address << 2) + 2] = data;
+    cartridge.ram[status.baseptr + (status.address << 2) + 2] = data;
     break;
   case 0x1ff3:
-    cartridge.sram[status.baseptr + (status.address << 2) + 3] = data;
+    cartridge.ram[status.baseptr + (status.address << 2) + 3] = data;
     break;
   case 0x1ff4: {
   uint8 temp;
-    temp = cartridge.sram[status.baseptr + (status.address >> 2) + 0x200];
+    temp = cartridge.ram[status.baseptr + (status.address >> 2) + 0x200];
     temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
-    cartridge.sram[status.baseptr + (status.address >> 2) + 0x200] = temp;
+    cartridge.ram[status.baseptr + (status.address >> 2) + 0x200] = temp;
   } break;
   case 0x1ff5:
     status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
-    cartridge.sram[addr] = data;
+    cartridge.ram[addr] = data;
     break;
   case 0x1ff6:
     status.address = (data & 0x7f);
     status.shift   = (data & 3) << 1;
-    cartridge.sram[addr] = data;
+    cartridge.ram[addr] = data;
     break;
   case 0x1ff7:
-    cartridge.sram[addr] = data;
+    cartridge.ram[addr] = data;
     break;
   }
 }

src/chip/obc1/obc1.h

@@ -16,3 +16,5 @@ struct {
   OBC1();
   ~OBC1();
 };
+
+extern OBC1 *obc1;

src/chip/sdd1/sdd1.cpp

@@ -1,4 +1,7 @@
 #include "../../base.h"
+
+SDD1 *sdd1;
+
 #include "sdd1emu.cpp"
 
 void SDD1::init() {}
@@ -40,10 +43,10 @@ uint8 b = (addr >> 16) & 0xff;
 uint8 SDD1::mmio_read(uint16 addr) {
   switch(addr) {
   //>>20 == 0x100000 == 1mb
-  case 0x4804:return (sdd1.index[0] >> 20) & 7;
-  case 0x4805:return (sdd1.index[1] >> 20) & 7;
-  case 0x4806:return (sdd1.index[2] >> 20) & 7;
-  case 0x4807:return (sdd1.index[3] >> 20) & 7;
+  case 0x4804: return (sdd1.index[0] >> 20) & 7;
+  case 0x4805: return (sdd1.index[1] >> 20) & 7;
+  case 0x4806: return (sdd1.index[2] >> 20) & 7;
+  case 0x4807: return (sdd1.index[3] >> 20) & 7;
   }
 
   return r_cpu->regs.mdr;
@@ -57,10 +60,10 @@ void SDD1::mmio_write(uint16 addr, uint8 data) {
     }
     break;
   //<<20 == 0x100000 == 1mb
-  case 0x4804:sdd1.index[0] = (data & 7) << 20;break;
-  case 0x4805:sdd1.index[1] = (data & 7) << 20;break;
-  case 0x4806:sdd1.index[2] = (data & 7) << 20;break;
-  case 0x4807:sdd1.index[3] = (data & 7) << 20;break;
+  case 0x4804: sdd1.index[0] = (data & 7) << 20; break;
+  case 0x4805: sdd1.index[1] = (data & 7) << 20; break;
+  case 0x4806: sdd1.index[2] = (data & 7) << 20; break;
+  case 0x4807: sdd1.index[3] = (data & 7) << 20; break;
   }
 }
 

src/chip/sdd1/sdd1.h

@@ -28,3 +28,5 @@ struct {
 
   SDD1();
 };
+
+extern SDD1 *sdd1;

src/chip/sdd1/sdd1emu.h

@@ -28,6 +28,7 @@ understood.
 
 ************************************************************************/
 
+typedef uint8_t bool8;
 
 class SDD1_IM {  //Input Manager
 

src/chip/srtc/srtc.cpp

@@ -52,6 +52,8 @@
 
 #include "../../base.h"
 
+SRTC *srtc;
+
 void SRTC::set_time() {
 time_t rawtime;
 tm *t;

src/chip/srtc/srtc.h

@@ -48,3 +48,5 @@ struct {
 
   SRTC();
 };
+
+extern SRTC *srtc;

src/chip/st010/st010.cpp

@@ -0,0 +1,86 @@
+#include "../../base.h"
+#include "st010_data.h"
+#include "st010_op.cpp"
+
+ST010 *st010;
+
+int16 ST010::sin(int16 theta) {
+  return sin_table[(theta >> 8) & 0xff];
+}
+
+int16 ST010::cos(int16 theta) {
+  return sin_table[((theta + 0x4000) >> 8) & 0xff];
+}
+
+uint8 ST010::readb(uint16 addr) {
+  return ram[addr & 0xfff];
+}
+
+uint16 ST010::readw(uint16 addr) {
+  return (readb(addr + 0) <<  0) |
+         (readb(addr + 1) <<  8);
+}
+
+uint32 ST010::readd(uint16 addr) {
+  return (readb(addr + 0) <<  0) |
+         (readb(addr + 1) <<  8) |
+         (readb(addr + 2) << 16) |
+         (readb(addr + 3) << 24);
+}
+
+void ST010::writeb(uint16 addr, uint8 data) {
+  ram[addr & 0xfff] = data;
+}
+
+void ST010::writew(uint16 addr, uint16 data) {
+  writeb(addr + 0, data);
+  writeb(addr + 1, data >> 8);
+}
+
+void ST010::writed(uint16 addr, uint32 data) {
+  writeb(addr + 0, data);
+  writeb(addr + 1, data >> 8);
+  writeb(addr + 2, data >> 16);
+  writeb(addr + 3, data >> 24);
+}
+
+//
+
+void ST010::init() {
+}
+
+void ST010::enable() {
+}
+
+void ST010::power() {
+  reset();
+}
+
+void ST010::reset() {
+  memset(ram, 0x00, sizeof ram);
+}
+
+//
+
+uint8 ST010::read(uint16 addr) {
+  return readb(addr);
+}
+
+void ST010::write(uint16 addr, uint8 data) {
+  writeb(addr, data);
+
+  if(addr == 0x0021 && data & 0x80) {
+    switch(ram[0x0020]) {
+    case 0x01: op_01(); break;
+    case 0x02: op_02(); break;
+    case 0x03: op_03(); break;
+    case 0x04: op_04(); break;
+    case 0x05: op_05(); break;
+    case 0x06: op_06(); break;
+    case 0x07: op_07(); break;
+    case 0x08: op_08(); break;
+    }
+
+    ram[0x0021] &= ~0x80;
+  }
+}

src/chip/st010/st010.h

@@ -0,0 +1,40 @@
+class ST010 { public:
+uint8 ram[0x1000];
+static const int16 sin_table[256];
+static const int16 mode7_scale[176];
+static const uint8 arctan[32][32];
+//interfaces to sin table
+  int16 sin(int16 theta);
+  int16 cos(int16 theta);
+
+//interfaces to ram buffer
+  uint8  readb (uint16 addr);
+  uint16 readw (uint16 addr);
+  uint32 readd (uint16 addr);
+  void   writeb(uint16 addr, uint8  data);
+  void   writew(uint16 addr, uint16 data);
+  void   writed(uint16 addr, uint32 data);
+
+//opcodes
+  void op_01();
+  void op_02();
+  void op_03();
+  void op_04();
+  void op_05();
+  void op_06();
+  void op_07();
+  void op_08();
+
+  void op_01(int16 x0, int16 y0, int16 &x1, int16 &y1, int16 &quadrant, int16 &theta);
+
+//base
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 read (uint16 addr);
+  void  write(uint16 addr, uint8 data);
+};
+
+extern ST010 *st010;

src/chip/st010/st010_data.h

@@ -0,0 +1,126 @@
+const int16 ST010::sin_table[256] = {
+   0x0000,  0x0324,  0x0648,  0x096a,  0x0c8c,  0x0fab,  0x12c8,  0x15e2,
+   0x18f9,  0x1c0b,  0x1f1a,  0x2223,  0x2528,  0x2826,  0x2b1f,  0x2e11,
+   0x30fb,  0x33df,  0x36ba,  0x398c,  0x3c56,  0x3f17,  0x41ce,  0x447a,
+   0x471c,  0x49b4,  0x4c3f,  0x4ebf,  0x5133,  0x539b,  0x55f5,  0x5842,
+   0x5a82,  0x5cb3,  0x5ed7,  0x60eb,  0x62f1,  0x64e8,  0x66cf,  0x68a6,
+   0x6a6d,  0x6c23,  0x6dc9,  0x6f5e,  0x70e2,  0x7254,  0x73b5,  0x7504,
+   0x7641,  0x776b,  0x7884,  0x7989,  0x7a7c,  0x7b5c,  0x7c29,  0x7ce3,
+   0x7d89,  0x7e1d,  0x7e9c,  0x7f09,  0x7f61,  0x7fa6,  0x7fd8,  0x7ff5,
+   0x7fff,  0x7ff5,  0x7fd8,  0x7fa6,  0x7f61,  0x7f09,  0x7e9c,  0x7e1d,
+   0x7d89,  0x7ce3,  0x7c29,  0x7b5c,  0x7a7c,  0x7989,  0x7884,  0x776b,
+   0x7641,  0x7504,  0x73b5,  0x7254,  0x70e2,  0x6f5e,  0x6dc9,  0x6c23,
+   0x6a6d,  0x68a6,  0x66cf,  0x64e8,  0x62f1,  0x60eb,  0x5ed7,  0x5cb3,
+   0x5a82,  0x5842,  0x55f5,  0x539b,  0x5133,  0x4ebf,  0x4c3f,  0x49b4,
+   0x471c,  0x447a,  0x41ce,  0x3f17,  0x3c56,  0x398c,  0x36ba,  0x33df,
+   0x30fb,  0x2e11,  0x2b1f,  0x2826,  0x2528,  0x2223,  0x1f1a,  0x1c0b,
+   0x18f8,  0x15e2,  0x12c8,  0x0fab,  0x0c8c,  0x096a,  0x0648,  0x0324,
+   0x0000, -0x0324, -0x0648, -0x096b, -0x0c8c, -0x0fab, -0x12c8, -0x15e2,
+  -0x18f9, -0x1c0b, -0x1f1a, -0x2223, -0x2528, -0x2826, -0x2b1f, -0x2e11,
+  -0x30fb, -0x33df, -0x36ba, -0x398d, -0x3c56, -0x3f17, -0x41ce, -0x447a,
+  -0x471c, -0x49b4, -0x4c3f, -0x4ebf, -0x5133, -0x539b, -0x55f5, -0x5842,
+  -0x5a82, -0x5cb3, -0x5ed7, -0x60ec, -0x62f1, -0x64e8, -0x66cf, -0x68a6,
+  -0x6a6d, -0x6c23, -0x6dc9, -0x6f5e, -0x70e2, -0x7254, -0x73b5, -0x7504,
+  -0x7641, -0x776b, -0x7884, -0x7989, -0x7a7c, -0x7b5c, -0x7c29, -0x7ce3,
+  -0x7d89, -0x7e1d, -0x7e9c, -0x7f09, -0x7f61, -0x7fa6, -0x7fd8, -0x7ff5,
+  -0x7fff, -0x7ff5, -0x7fd8, -0x7fa6, -0x7f61, -0x7f09, -0x7e9c, -0x7e1d,
+  -0x7d89, -0x7ce3, -0x7c29, -0x7b5c, -0x7a7c, -0x7989, -0x7883, -0x776b,
+  -0x7641, -0x7504, -0x73b5, -0x7254, -0x70e2, -0x6f5e, -0x6dc9, -0x6c23,
+  -0x6a6d, -0x68a6, -0x66cf, -0x64e8, -0x62f1, -0x60eb, -0x5ed7, -0x5cb3,
+  -0x5a82, -0x5842, -0x55f5, -0x539a, -0x5133, -0x4ebf, -0x4c3f, -0x49b3,
+  -0x471c, -0x447a, -0x41cd, -0x3f17, -0x3c56, -0x398c, -0x36b9, -0x33de,
+  -0x30fb, -0x2e10, -0x2b1f, -0x2826, -0x2527, -0x2223, -0x1f19, -0x1c0b,
+  -0x18f8, -0x15e2, -0x12c8, -0x0fab, -0x0c8b, -0x096a, -0x0647, -0x0324
+};
+
+const int16 ST010::mode7_scale[176] = {
+  0x0380,  0x0325,  0x02da,  0x029c,  0x0268,  0x023b,  0x0215,  0x01f3,
+  0x01d5,  0x01bb,  0x01a3,  0x018e,  0x017b,  0x016a,  0x015a,  0x014b,
+  0x013e,  0x0132,  0x0126,  0x011c,  0x0112,  0x0109,  0x0100,  0x00f8,
+  0x00f0,  0x00e9,  0x00e3,  0x00dc,  0x00d6,  0x00d1,  0x00cb,  0x00c6,
+  0x00c1,  0x00bd,  0x00b8,  0x00b4,  0x00b0,  0x00ac,  0x00a8,  0x00a5,
+  0x00a2,  0x009e,  0x009b,  0x0098,  0x0095,  0x0093,  0x0090,  0x008d,
+  0x008b,  0x0088,  0x0086,  0x0084,  0x0082,  0x0080,  0x007e,  0x007c,
+  0x007a,  0x0078,  0x0076,  0x0074,  0x0073,  0x0071,  0x006f,  0x006e,
+  0x006c,  0x006b,  0x0069,  0x0068,  0x0067,  0x0065,  0x0064,  0x0063,
+  0x0062,  0x0060,  0x005f,  0x005e,  0x005d,  0x005c,  0x005b,  0x005a,
+  0x0059,  0x0058,  0x0057,  0x0056,  0x0055,  0x0054,  0x0053,  0x0052,
+  0x0051,  0x0051,  0x0050,  0x004f,  0x004e,  0x004d,  0x004d,  0x004c,
+  0x004b,  0x004b,  0x004a,  0x0049,  0x0048,  0x0048,  0x0047,  0x0047,
+  0x0046,  0x0045,  0x0045,  0x0044,  0x0044,  0x0043,  0x0042,  0x0042,
+  0x0041,  0x0041,  0x0040,  0x0040,  0x003f,  0x003f,  0x003e,  0x003e,
+  0x003d,  0x003d,  0x003c,  0x003c,  0x003b,  0x003b,  0x003a,  0x003a,
+  0x003a,  0x0039,  0x0039,  0x0038,  0x0038,  0x0038,  0x0037,  0x0037,
+  0x0036,  0x0036,  0x0036,  0x0035,  0x0035,  0x0035,  0x0034,  0x0034,
+  0x0034,  0x0033,  0x0033,  0x0033,  0x0032,  0x0032,  0x0032,  0x0031,
+  0x0031,  0x0031,  0x0030,  0x0030,  0x0030,  0x0030,  0x002f,  0x002f,
+  0x002f,  0x002e,  0x002e,  0x002e,  0x002e,  0x002d,  0x002d,  0x002d,
+  0x002d,  0x002c,  0x002c,  0x002c,  0x002c,  0x002b,  0x002b,  0x002b
+};
+
+const uint8 ST010::arctan[32][32] = {
+  { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 },
+  { 0x80, 0xa0, 0xad, 0xb3, 0xb6, 0xb8, 0xb9, 0xba, 0xbb, 0xbb, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd,
+    0xbd, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbf, 0xbf, 0xbf, 0xbf },
+  { 0x80, 0x93, 0xa0, 0xa8, 0xad, 0xb0, 0xb3, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xbb,
+    0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd },
+  { 0x80, 0x8d, 0x98, 0xa0, 0xa6, 0xaa, 0xad, 0xb0, 0xb1, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb7, 0xb8,
+    0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc },
+  { 0x80, 0x8a, 0x93, 0x9a, 0xa0, 0xa5, 0xa8, 0xab, 0xad, 0xaf, 0xb0, 0xb2, 0xb3, 0xb4, 0xb5, 0xb5,
+    0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb },
+  { 0x80, 0x88, 0x90, 0x96, 0x9b, 0xa0, 0xa4, 0xa7, 0xa9, 0xab, 0xad, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3,
+    0xb4, 0xb4, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xb9, 0xb9 },
+  { 0x80, 0x87, 0x8d, 0x93, 0x98, 0x9c, 0xa0, 0xa3, 0xa6, 0xa8, 0xaa, 0xac, 0xad, 0xae, 0xb0, 0xb0,
+    0xb1, 0xb2, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8 },
+  { 0x80, 0x86, 0x8b, 0x90, 0x95, 0x99, 0x9d, 0xa0, 0xa3, 0xa5, 0xa7, 0xa9, 0xaa, 0xac, 0xad, 0xae,
+    0xaf, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7 },
+  { 0x80, 0x85, 0x8a, 0x8f, 0x93, 0x97, 0x9a, 0x9d, 0xa0, 0xa2, 0xa5, 0xa6, 0xa8, 0xaa, 0xab, 0xac,
+    0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb5, 0xb5 },
+  { 0x80, 0x85, 0x89, 0x8d, 0x91, 0x95, 0x98, 0x9b, 0x9e, 0xa0, 0xa0, 0xa4, 0xa6, 0xa7, 0xa9, 0xaa,
+    0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb4 },
+  { 0x80, 0x84, 0x88, 0x8c, 0x90, 0x93, 0x96, 0x99, 0x9b, 0x9e, 0xa0, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8,
+    0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb2, 0xb3, 0xb3 },
+  { 0x80, 0x84, 0x87, 0x8b, 0x8e, 0x91, 0x94, 0x97, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5, 0xa6,
+    0xa7, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2 },
+  { 0x80, 0x83, 0x87, 0x8a, 0x8d, 0x90, 0x93, 0x96, 0x98, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5,
+    0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb0, 0xb1 },
+  { 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x94, 0x96, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa2, 0xa3,
+    0xa4, 0xa5, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xaf, 0xb0 },
+  { 0x80, 0x83, 0x86, 0x89, 0x8b, 0x8e, 0x90, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa1,
+    0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac, 0xad, 0xad, 0xae, 0xae, 0xaf },
+  { 0x80, 0x83, 0x85, 0x88, 0x8b, 0x8d, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9b, 0x9d, 0x9f, 0xa0,
+    0xa1, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xab, 0xab, 0xac, 0xad, 0xad, 0xae },
+  { 0x80, 0x83, 0x85, 0x88, 0x8a, 0x8c, 0x8f, 0x91, 0x93, 0x95, 0x97, 0x99, 0x9a, 0x9c, 0x9d, 0x9f,
+    0xa0, 0xa1, 0xa2, 0xa3, 0xa5, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xab, 0xac, 0xad },
+  { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x97, 0x99, 0x9b, 0x9c, 0x9d,
+    0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac },
+  { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8b, 0x8d, 0x8f, 0x91, 0x93, 0x95, 0x96, 0x98, 0x99, 0x9b, 0x9c,
+    0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x9a, 0x9b,
+    0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x99, 0x9a,
+    0x9b, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9 },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8f, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x99,
+    0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8 },
+  { 0x80, 0x82, 0x84, 0x86, 0x87, 0x89, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x98,
+    0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7 },
+  { 0x80, 0x82, 0x84, 0x85, 0x87, 0x89, 0x8a, 0x8c, 0x8e, 0x8f, 0x91, 0x92, 0x94, 0x95, 0x96, 0x98,
+    0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6 },
+  { 0x80, 0x82, 0x83, 0x85, 0x87, 0x88, 0x8a, 0x8c, 0x8d, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x96, 0x97,
+    0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x94, 0x95, 0x96,
+    0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa4 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x89, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x95,
+    0x96, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x87, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93, 0x95,
+    0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2, 0xa3 },
+  { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x89, 0x8a, 0x8b, 0x8d, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94,
+    0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2 },
+  { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93,
+    0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1, 0xa1 },
+  { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8b, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93,
+    0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1 },
+  { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92,
+    0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0 }
+};

src/chip/st010/st010_op.cpp

@@ -0,0 +1,257 @@
+//ST-010 emulation code - Copyright (C) 2003 The Dumper, Matthew Kendora, Overload, Feather
+//bsnes port - Copyright (C) 2007 byuu
+
+void ST010::op_01(int16 x0, int16 y0, int16 &x1, int16 &y1, int16 &quadrant, int16 &theta) {
+  if((x0 < 0) && (y0 < 0)) {
+    x1 = -x0;
+    y1 = -y0;
+    quadrant = -0x8000;
+  } else if(x0 < 0) {
+    x1 = y0;
+    y1 = -x0;
+    quadrant = -0x4000;
+  } else if(y0 < 0) {
+    x1 = -y0;
+    y1 = x0;
+    quadrant = 0x4000;
+  } else {
+    x1 = x0;
+    y1 = y0;
+    quadrant = 0x0000;
+  }
+
+  while((x1 > 0x1f) || (y1 > 0x1f)) {
+    if(x1 > 1) { x1 >>= 1; }
+    if(y1 > 1) { y1 >>= 1; }
+  }
+
+  if(y1 == 0) { quadrant += 0x4000; }
+
+  theta = (arctan[y1][x1] << 8) ^ quadrant;
+}
+
+//
+
+void ST010::op_01() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 x1, y1, quadrant, theta;
+
+  op_01(x0, y0, x1, y1, quadrant, theta);
+
+  writew(0x0000, x1);
+  writew(0x0002, y1);
+  writew(0x0004, quadrant);
+//writew(0x0006, y0); //Overload's docs note this write occurs, SNES9x disagrees
+  writew(0x0010, theta);
+}
+
+void ST010::op_02() {
+int16 positions = readw(0x0024);
+uint16 *places  = (uint16*)(ram + 0x0040);
+uint16 *drivers = (uint16*)(ram + 0x0080);
+
+bool sorted;
+uint16 temp;
+  if(positions > 1) {
+    do {
+      sorted = true;
+      for(int i = 0; i < positions - 1; i++) {
+        if(places[i] < places[i + 1]) {
+          temp = places[i + 1];
+          places[i + 1] = places[i];
+          places[i] = temp;
+
+          temp = drivers[i + 1];
+          drivers[i + 1] = drivers[i];
+          drivers[i] = temp;
+
+          sorted = false;
+        }
+      }
+      positions--;
+    } while(!sorted);
+  }
+}
+
+void ST010::op_03() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 multiplier = readw(0x0004);
+int32 x1, y1;
+
+  x1 = x0 * multiplier << 1;
+  y1 = y0 * multiplier << 1;
+
+  writed(0x0010, x1);
+  writed(0x0014, y1);
+}
+
+void ST010::op_04() {
+int16 x = readw(0x0000);
+int16 y = readw(0x0002);
+int16 square;
+//calculate the vector length of (x,y)
+  square = (int16)sqrt((double)(y * y + x * x));
+
+  writew(0x0010, square);
+}
+
+void ST010::op_05() {
+int32 dx, dy;
+int16 a1, b1, c1;
+uint16 o1;
+bool wrap = false;
+
+//target (x,y) coordinates
+int16 ypos_max = readw(0x00c0);
+int16 xpos_max = readw(0x00c2);
+
+//current coordinates and direction
+int32 ypos = readd(0x00c4);
+int32 xpos = readd(0x00c8);
+uint16 rot = readw(0x00cc);
+
+//physics
+uint16 speed = readw(0x00d4);
+uint16 accel = readw(0x00d6);
+uint16 speed_max = readw(0x00d8);
+
+//special condition acknowledgement
+int16 system = readw(0x00da);
+int16 flags = readw(0x00dc);
+
+//new target coordinates
+int16 ypos_new = readw(0x00de);
+int16 xpos_new = readw(0x00e0);
+
+//mask upper bit
+  xpos_new &= 0x7fff;
+
+//get the current distance
+  dx = xpos_max - (xpos >> 16);
+  dy = ypos_max - (ypos >> 16);
+
+//quirk: clear and move in9
+  writew(0x00d2, 0xffff);
+  writew(0x00da, 0x0000);
+
+//grab the target angle
+  op_01(dy, dx, a1, b1, c1, (int16&)o1);
+
+//check for wrapping
+  if(abs(o1 - rot) > 0x8000) {
+    o1 += 0x8000;
+    rot += 0x8000;
+    wrap = true;
+  }
+
+uint16 old_speed = speed;
+
+//special case
+  if(abs(o1 - rot) == 0x8000) {
+    speed = 0x100;
+  }
+
+//slow down for sharp curves
+  else if(abs(o1 - rot) >= 0x1000) {
+  uint32 slow = abs(o1 - rot);
+    slow >>= 4; //scaling
+    speed -= slow;
+  }
+
+//otherwise accelerate
+  else {
+    speed += accel;
+    if(speed > speed_max) {
+      speed = speed_max; //clip speed
+    }
+  }
+
+//prevent negative/positive overflow
+  if(abs(old_speed - speed) > 0x8000) {
+    if(old_speed < speed) { speed = 0; }
+    else speed = 0xff00;
+  }
+
+//adjust direction by so many degrees
+//be careful of negative adjustments
+  if((o1 > rot && (o1 - rot) > 0x80) || (o1 < rot && (rot - o1) >= 0x80)) {
+    if(o1 < rot) { rot -= 0x280; }
+    else if(o1 > rot) { rot += 0x280; }
+  }
+
+//turn of wrapping
+  if(wrap) { rot -= 0x8000; }
+
+//now check the distances (store for later)
+  dx = (xpos_max << 16) - xpos;
+  dy = (ypos_max << 16) - ypos;
+  dx >>= 16;
+  dy >>= 16;
+
+//if we're in so many units of the target, signal it
+  if((system && (dy <= 6 && dy >= -8) && (dx <= 126 && dx >= -128)) || (!system && (dx <= 6 && dx >= -8) && (dy <= 126 && dy >= -128))) {
+  //announce our new destination and flag it
+    xpos_max = xpos_new & 0x7fff;
+    ypos_max = ypos_new;
+    flags |= 0x08;
+  }
+
+//update position
+  xpos -= (cos(rot) * 0x400 >> 15) * (speed >> 8) << 1;
+  ypos -= (sin(rot) * 0x400 >> 15) * (speed >> 8) << 1;
+
+//quirk: mask upper byte
+  xpos &= 0x1fffffff;
+  ypos &= 0x1fffffff;
+
+  writew(0x00c0, ypos_max);
+  writew(0x00c2, xpos_max);
+  writed(0x00c4, ypos);
+  writed(0x00c8, xpos);
+  writew(0x00cc, rot);
+  writew(0x00d4, speed);
+  writew(0x00dc, flags);
+}
+
+void ST010::op_06() {
+int16 multiplicand = readw(0x0000);
+int16 multiplier = readw(0x0002);
+int32 product;
+
+  product = multiplicand * multiplier << 1;
+
+  writed(0x0010, product);
+}
+
+void ST010::op_07() {
+int16 theta = readw(0x0000);
+
+int16 data;
+  for(int i = 0, offset = 0; i < 176; i++) {
+    data = mode7_scale[i] * cos(theta) >> 15;
+    writew(0x00f0 + offset, data);
+    writew(0x0510 + offset, data);
+
+    data = mode7_scale[i] * sin(theta) >> 15;
+    writew(0x0250 + offset, data);
+    if(data) { data = ~data; }
+    writew(0x03b0 + offset, data);
+
+    offset += 2;
+  }
+}
+
+void ST010::op_08() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 theta = readw(0x0004);
+int16 x1, y1;
+
+  x1 = (y0 * sin(theta) >> 15) + (x0 * cos(theta) >> 15);
+  y1 = (y0 * cos(theta) >> 15) - (x0 * sin(theta) >> 15);
+
+  writew(0x0010, x1);
+  writew(0x0012, y1);
+}

src/clean.bat

@@ -0,0 +1 @@
+@make PLATFORM=win-visualc-lui clean

src/clean.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+make PLATFORM=x-gcc-lui clean

src/config/config.cpp

@@ -1,80 +1,125 @@
-Config config_file;
-
 namespace config {
 
-FS::Path FS::base_path(0, "fs.base_path", "Directory that bsnes resides in", "");
-
-FS::Path FS::rom_path(&config_file, "fs.rom_path",
-  "Default path to look for ROM files in (\"\" = use default directory)", "");
-FS::Path FS::save_path(&config_file, "fs.save_path",
-  "Default path for all save RAM and cheat files (\"\" = use current directory)", "");
-
-void FS::Path::sset(const char *_data) {
-string path;
-  strcpy(path, _data);
-  strunquote(path);
-  replace(path, "\\", "/");
-
-//blank path?
-  if(strlen(path) == 0) {
-    Setting::sset(strptr(path));
-    return;
-  }
-
-//missing final directory marker?
-  if(strptr(path)[strlen(path) - 1] != '/') {
-    strcat(path, "/");
-  }
-
-  Setting::sset(strptr(path));
+Config& config() {
+static Config config;
+  return config;
 }
 
-Setting FS::save_ext(&config_file, "fs.save_ext",
+string file_updatepath(const char *req_file, const char *req_path) {
+string file(req_file);
+  replace(file, "\\", "/");
+  if(!req_path || strlen(req_path) == 0) { return file; }
+
+string path(req_path);
+  replace(path, "\\", "/");
+  if(!strend(path, "/")) { strcat(path, "/"); }
+
+  if(strbegin(path, "./")) {
+    strltrim(path, "./");
+  string temp;
+    strcpy(temp, config::path.base);
+    strcat(temp, path);
+    strcpy(path, temp);
+  }
+
+stringarray part;
+  split(part, "/", file);
+  strcat(path, part[count(part) - 1]);
+  return path;
+}
+
+StringSetting Path::base(0, "fs.base_path",
+  "Path that bsnes resides in", "");
+StringSetting Path::rom(&config(), "path.rom",
+  "Default path to look for ROM files in (\"\" = use default directory)", "");
+StringSetting Path::save(&config(), "path.save",
+  "Default path for all save RAM and cheat files (\"\" = use current directory)", "");
+StringSetting Path::bios(&config(), "path.bios",
+  "Path where BIOS file(s) are located\n"
+  "Supported BIOS files:\n"
+  "stbios.bin - Bandai Sufami Turbo"
+  "", "./bios");
+
+StringSetting Path::save_ext(&config(), "path.save_ext",
   "Extension to be used for all save RAM files", "srm");
 
-SNES::VideoColorAdjust SNES::gamma_ramp(&config_file, "snes.colorfilter.gamma_ramp",
-  "Use precalculated TV-style gamma ramp", true, Setting::TRUE_FALSE);
-SNES::VideoColorAdjust SNES::sepia(&config_file, "snes.colorfilter.sepia",
-  "Convert color to sepia tone", false, Setting::TRUE_FALSE);
-SNES::VideoColorAdjust SNES::grayscale(&config_file, "snes.colorfilter.grayscale",
-  "Convert color to grayscale tone", false, Setting::TRUE_FALSE);
-SNES::VideoColorAdjust SNES::invert(&config_file, "snes.colorfilter.invert",
-  "Invert output image colors", false, Setting::TRUE_FALSE);
-SNES::VideoColorAdjust SNES::contrast(&config_file, "snes.colorfilter.contrast",
-  "", 0,  Setting::DEC);
-SNES::VideoColorAdjust SNES::brightness(&config_file, "snes.colorfilter.brightness",
-  "", 0, Setting::DEC);
-SNES::VideoColorAdjust SNES::gamma(&config_file, "snes.colorfilter.gamma",
-  "", 100, Setting::DEC);
+IntegerSetting SNES::gamma_ramp(&config(), "snes.colorfilter.gamma_ramp",
+  "Use precalculated TV-style gamma ramp", IntegerSetting::Boolean, true);
+IntegerSetting SNES::sepia(&config(), "snes.colorfilter.sepia",
+  "Convert color to sepia tone", IntegerSetting::Boolean, false);
+IntegerSetting SNES::grayscale(&config(), "snes.colorfilter.grayscale",
+  "Convert color to grayscale tone", IntegerSetting::Boolean, false);
+IntegerSetting SNES::invert(&config(), "snes.colorfilter.invert",
+  "Invert output image colors", IntegerSetting::Boolean, false);
+IntegerSetting SNES::contrast(&config(), "snes.colorfilter.contrast",
+  "Contrast", IntegerSetting::Decimal, 0);
+IntegerSetting SNES::brightness(&config(), "snes.colorfilter.brightness",
+  "Brightness", IntegerSetting::Decimal, 0);
+IntegerSetting SNES::gamma(&config(), "snes.colorfilter.gamma",
+  "Gamma", IntegerSetting::Decimal, 80);
 
-void SNES::VideoColorAdjust::set(uint32 _data) {
-  Setting::set(_data);
-  ::snes->update_color_lookup_table();
-}
+IntegerSetting SNES::ntsc_merge_fields(&config(), "snes.ntsc_merge_fields",
+  "Merge fields in NTSC video filter\n"
+  "Set to true if using filter at any refresh rate other than 60hz\n"
+  "", IntegerSetting::Boolean, true);
 
-Setting SNES::ntsc_merge_fields(&config_file, "snes.ntsc_merge_fields",
-"Merge fields in NTSC video filter\n"
-"Set to true if using filter at any refresh rate other than 60hz\n"
-"", false, Setting::TRUE_FALSE);
+IntegerSetting SNES::mute(&config(), "snes.mute", "Mutes SNES audio output when enabled",
+  IntegerSetting::Boolean, false);
 
-Setting SNES::mute(&config_file, "snes.mute", "Mutes SNES audio output when enabled",
-  false, Setting::TRUE_FALSE);
+IntegerSetting SNES::controller_port0(&config(), "snes.controller_port_1",
+  "Controller attached to SNES port 1", IntegerSetting::Decimal, ::SNES::DEVICEID_JOYPAD1);
+IntegerSetting SNES::controller_port1(&config(), "snes.controller_port_2",
+  "Controller attached to SNES port 2", IntegerSetting::Decimal, ::SNES::DEVICEID_JOYPAD2);
 
-//do not save these settings to config_file
-Setting CPU::hdma_enable(0, "cpu.hdma_enable", "Enable HDMA effects", true, Setting::TRUE_FALSE);
-Setting PPU::opt_enable(0, "ppu.opt_enable", "Enable offset-per-tile effects", true, Setting::TRUE_FALSE);
+IntegerSetting CPU::ntsc_clock_rate(&config(), "cpu.ntsc_clock_rate",
+  "NTSC S-CPU clock rate (in hz)", IntegerSetting::Decimal, 21477272);
+IntegerSetting CPU::pal_clock_rate(&config(), "cpu.pal_clock_rate",
+  "PAL S-CPU clock rate (in hz)", IntegerSetting::Decimal, 21281370);
 
-Setting PPU::bg1_pri0_enable(0, "ppu.bg1_pri0_enable", "Enable BG1 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg1_pri1_enable(0, "ppu.bg1_pri1_enable", "Enable BG1 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg2_pri0_enable(0, "ppu.bg2_pri0_enable", "Enable BG2 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg2_pri1_enable(0, "ppu.bg2_pri1_enable", "Enable BG2 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg3_pri0_enable(0, "ppu.bg3_pri0_enable", "Enable BG3 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg3_pri1_enable(0, "ppu.bg3_pri1_enable", "Enable BG3 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg4_pri0_enable(0, "ppu.bg4_pri0_enable", "Enable BG4 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg4_pri1_enable(0, "ppu.bg4_pri1_enable", "Enable BG4 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri0_enable(0, "ppu.oam_pri0_enable", "Enable OAM Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri1_enable(0, "ppu.oam_pri1_enable", "Enable OAM Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri2_enable(0, "ppu.oam_pri2_enable", "Enable OAM Priority 2", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri3_enable(0, "ppu.oam_pri3_enable", "Enable OAM Priority 3", true, Setting::TRUE_FALSE);
+IntegerSetting CPU::hdma_enable(0, "cpu.hdma_enable",
+  "Enable HDMA effects", IntegerSetting::Boolean, true);
+
+IntegerSetting SMP::ntsc_clock_rate(&config(), "smp.ntsc_clock_rate",
+  "NTSC S-SMP clock rate (in hz)", IntegerSetting::Decimal, 24606720);
+IntegerSetting SMP::pal_clock_rate(&config(), "smp.pal_clock_rate",
+  "PAL S-SMP clock rate (in hz)", IntegerSetting::Decimal, 24606720);
+
+IntegerSetting PPU::Hack::render_scanline_position(&config(), "ppu.hack.render_scanline_position",
+  "Approximate HCLOCK position to render at for scanline-based renderers",
+  IntegerSetting::Decimal, 512);
+IntegerSetting PPU::Hack::obj_cache(&config(), "ppu.hack.obj_cache",
+  "Cache OAM OBJ attributes one scanline before rendering\n"
+  "This is technically closer to the actual operation of the SNES,\n"
+  "but can cause problems in some games if enabled",
+  IntegerSetting::Boolean, false);
+IntegerSetting PPU::Hack::oam_address_invalidation(&config(), "ppu.hack.oam_address_invalidation",
+  "OAM access address changes during active display, as the S-PPU reads\n"
+  "data to render the display. Thusly, the address retrieved when accessing\n"
+  "OAM during active display is unpredictable. Unfortunately, the exact\n"
+  "algorithm for this is completely unknown at this time. It is more hardware\n"
+  "accurate to enable this setting, but one must *not* rely on the actual\n"
+  "address to match hardware under emulation.",
+  IntegerSetting::Boolean, true);
+IntegerSetting PPU::Hack::cgram_address_invalidation(&config(), "ppu.hack.cgram_address_invalidation",
+  "CGRAM access address changes during active display (excluding hblank), as\n"
+  "the S-PPU reads data to render the display. Thusly, as with OAM, the access\n"
+  "address is unpredictable. Again, enabling this setting is more hardware\n"
+  "accurate, but one must *not* rely on the actual address to match hardware\n"
+  "under emulation.",
+  IntegerSetting::Boolean, true);
+
+IntegerSetting PPU::opt_enable(0, "ppu.opt_enable", "Enable offset-per-tile effects", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg1_pri0_enable(0, "ppu.bg1_pri0_enable", "Enable BG1 Priority 0", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg1_pri1_enable(0, "ppu.bg1_pri1_enable", "Enable BG1 Priority 1", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg2_pri0_enable(0, "ppu.bg2_pri0_enable", "Enable BG2 Priority 0", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg2_pri1_enable(0, "ppu.bg2_pri1_enable", "Enable BG2 Priority 1", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg3_pri0_enable(0, "ppu.bg3_pri0_enable", "Enable BG3 Priority 0", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg3_pri1_enable(0, "ppu.bg3_pri1_enable", "Enable BG3 Priority 1", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg4_pri0_enable(0, "ppu.bg4_pri0_enable", "Enable BG4 Priority 0", IntegerSetting::Boolean, true);
+IntegerSetting PPU::bg4_pri1_enable(0, "ppu.bg4_pri1_enable", "Enable BG4 Priority 1", IntegerSetting::Boolean, true);
+IntegerSetting PPU::oam_pri0_enable(0, "ppu.oam_pri0_enable", "Enable OAM Priority 0", IntegerSetting::Boolean, true);
+IntegerSetting PPU::oam_pri1_enable(0, "ppu.oam_pri1_enable", "Enable OAM Priority 1", IntegerSetting::Boolean, true);
+IntegerSetting PPU::oam_pri2_enable(0, "ppu.oam_pri2_enable", "Enable OAM Priority 2", IntegerSetting::Boolean, true);
+IntegerSetting PPU::oam_pri3_enable(0, "ppu.oam_pri3_enable", "Enable OAM Priority 3", IntegerSetting::Boolean, true);
 
 };

src/config/config.h

@@ -1,40 +1,46 @@
-extern Config config_file;
-
 namespace config {
 
-extern struct FS {
-  static class Path : public Setting {
-  public:
-    void sset(const char *_data);
-    SettingOperators(Path);
-  } base_path, rom_path, save_path;
-  static Setting save_ext;
-} fs;
+extern Config& config();
+
+string file_updatepath(const char *, const char *);
+
+extern struct Path {
+  static StringSetting base, rom, save, bios;
+  static StringSetting save_ext;
+} path;
 
 extern struct SNES {
-  static class VideoColorAdjust : public Setting {
-  public:
-    void set(uint32 _data);
-    SettingOperators(VideoColorAdjust);
-  } gamma_ramp, sepia, grayscale, invert, contrast, brightness, gamma;
-
-  static Setting ntsc_merge_fields;
-  static Setting mute;
+  static IntegerSetting gamma_ramp, sepia, grayscale, invert, contrast, brightness, gamma;
+  static IntegerSetting ntsc_merge_fields;
+  static IntegerSetting mute;
+  static IntegerSetting controller_port0;
+  static IntegerSetting controller_port1;
 } snes;
 
 extern struct CPU {
-  static Setting hdma_enable;
+  static IntegerSetting ntsc_clock_rate, pal_clock_rate;
+  static IntegerSetting hdma_enable;
 } cpu;
 
-extern struct PPU {
-  static Setting opt_enable;
+extern struct SMP {
+  static IntegerSetting ntsc_clock_rate, pal_clock_rate;
+} smp;
 
-  static Setting bg1_pri0_enable, bg1_pri1_enable;
-  static Setting bg2_pri0_enable, bg2_pri1_enable;
-  static Setting bg3_pri0_enable, bg3_pri1_enable;
-  static Setting bg4_pri0_enable, bg4_pri1_enable;
-  static Setting oam_pri0_enable, oam_pri1_enable;
-  static Setting oam_pri2_enable, oam_pri3_enable;
+extern struct PPU {
+  struct Hack {
+    static IntegerSetting render_scanline_position;
+    static IntegerSetting obj_cache;
+    static IntegerSetting oam_address_invalidation;
+    static IntegerSetting cgram_address_invalidation;
+  } hack;
+
+  static IntegerSetting opt_enable;
+  static IntegerSetting bg1_pri0_enable, bg1_pri1_enable;
+  static IntegerSetting bg2_pri0_enable, bg2_pri1_enable;
+  static IntegerSetting bg3_pri0_enable, bg3_pri1_enable;
+  static IntegerSetting bg4_pri0_enable, bg4_pri1_enable;
+  static IntegerSetting oam_pri0_enable, oam_pri1_enable;
+  static IntegerSetting oam_pri2_enable, oam_pri3_enable;
 } ppu;
 
 };

src/cpu/bcpu/bcpu.cpp

@@ -1,130 +0,0 @@
-#include "../../base.h"
-
-#include "core/core.cpp"
-#include "memory/memory.cpp"
-#include "dma/dma.cpp"
-#include "timing/timing.cpp"
-
-#include "bcpu_exec.cpp"
-#include "bcpu_mmio.cpp"
-#include "bcpu_int.cpp"
-
-uint8 bCPU::pio_status() { return status.pio; }
-
-void bCPU::run() {
-  if(run_state.hdma) {
-    exec_hdma();
-    return;
-  }
-
-  if(run_state.dma) {
-    exec_dma();
-    return;
-  }
-
-  if(status.cycle_pos == 0) {
-  //interrupts only trigger on opcode edges
-    if(!run_state.irq && !run_state.stp) {
-      if(time.nmi_pending == true) {
-        time.nmi_pending = false;
-        aa.w = 0xffea;
-        run_state.irq = true;
-      } else if(time.irq_pending == true) {
-        time.irq_pending = false;
-        aa.w = 0xffee;
-        run_state.irq = true;
-      }
-    }
-  }
-
-  exec_cycle();
-}
-
-void bCPU::scanline() {
-  time.hdma_triggered = false;
-
-  if(vcounter() == (overscan() == false ? 227 : 242) && status.auto_joypad_poll == true) {
-    snes->poll_input(SNES::DEV_JOYPAD1);
-    snes->poll_input(SNES::DEV_JOYPAD2);
-  //When the SNES auto-polls the joypads, it writes 1, then 0 to
-  //$4016, then reads from each 16 times to get the joypad state
-  //information. As a result, the joypad read positions are set
-  //to 16 after such a poll. Position 16 is the controller
-  //connected status bit.
-    status.joypad1_read_pos = 16;
-    status.joypad2_read_pos = 16;
-  }
-}
-
-void bCPU::frame() {
-  time.nmi_read = 1;
-  time.nmi_line = 1;
-  time.nmi_transition = 0;
-
-  if(cpu_version == 2) {
-    time.hdmainit_trigger_pos = 12 + dma_counter();
-  } else {
-    time.hdmainit_trigger_pos = 12 + 8 - dma_counter();
-  }
-  time.hdmainit_triggered = false;
-}
-
-void bCPU::power() {
-  region = snes->region();
-
-  regs.a = regs.x = regs.y = 0x0000;
-  regs.s = 0x01ff;
-  reset();
-}
-
-void bCPU::reset() {
-//reset vector location
-  regs.pc.d = 0;
-  regs.pc.l = r_mem->read(0xfffc);
-  regs.pc.h = r_mem->read(0xfffd);
-
-//registers are not fully reset by SNES
-  regs.x.h = 0x00;
-  regs.y.h = 0x00;
-  regs.s.h = 0x01;
-  regs.d   = 0x0000;
-  regs.db  = 0x00;
-  regs.p   = 0x34;
-  regs.e   = 1;
-  regs.mdr = 0x00;
-
-//simulate pbr:pc push during reset irq vector
-  regs.s.l -= 3;
-
-  time_reset();
-  mmio_reset();
-  dma_reset();
-
-  run_state.hdma = false;
-  run_state.dma  = false;
-  run_state.irq  = false;
-  run_state.wai  = false;
-  run_state.stp  = false;
-
-  status.cycle_pos       = 0;
-  status.cycle_count     = 0;
-  status.cycles_executed = 0;
-
-  apu_port[0] = 0x00;
-  apu_port[1] = 0x00;
-  apu_port[2] = 0x00;
-  apu_port[3] = 0x00;
-
-  frame();
-
-//initial latch values for $213c/$213d
-//[x]0035 : [y]0000 (53.0 -> 212) [lda $2137]
-//[x]0038 : [y]0000 (56.5 -> 226) [nop : lda $2137]
-  add_cycles(186);
-}
-
-bCPU::bCPU() {
-  init_op_tables();
-}
-
-bCPU::~bCPU() {}

src/cpu/bcpu/bcpu.h

@@ -1,167 +0,0 @@
-class bCPU : public CPU {
-public:
-#include "core/core.h"
-#include "memory/memory.h"
-#include "dma/dma.h"
-#include "timing/timing.h"
-
-enum { NTSC = 0, PAL = 1 };
-uint8 region;
-
-enum {
-  DMASTATE_DMASYNC,
-  DMASTATE_DMASYNC2,
-  DMASTATE_DMASYNC3,
-  DMASTATE_RUN,
-  DMASTATE_CPUSYNC,
-
-  HDMASTATE_IDMASYNC,
-  HDMASTATE_IDMASYNC2,
-  HDMASTATE_IDMASYNC3,
-  HDMASTATE_ICPUSYNC,
-
-  HDMASTATE_DMASYNC,
-  HDMASTATE_DMASYNC2,
-  HDMASTATE_DMASYNC3,
-  HDMASTATE_RUN,
-  HDMASTATE_CPUSYNC
-};
-
-struct {
-  bool hdma;
-  bool dma;
-  bool irq;
-  bool stp;
-  bool wai;
-} run_state;
-
-struct {
-  uint8  cycle_pos, cycle_count;
-  uint8  opcode;
-  uint32 cycles_executed;
-
-  uint8  dma_state, hdma_state;
-  uint32 dma_cycle_count, hdma_cycle_count;
-
-//$4207-$420a
-  uint16 virq_trigger, hirq_trigger;
-
-//$2181-$2183
-  uint32 wram_addr;
-
-//$4016-$4017
-  bool   joypad_strobe_latch;
-  uint8  joypad1_read_pos, joypad2_read_pos;
-
-//$4200
-  bool   nmi_enabled;
-  bool   hirq_enabled, virq_enabled;
-  bool   auto_joypad_poll;
-
-//$4201
-  uint8  pio;
-
-//$4202-$4203
-  uint8  mul_a, mul_b;
-
-//$4204-$4206
-  uint16 div_a;
-  uint8  div_b;
-
-//$4207-$420a
-  uint16 hirq_pos, virq_pos;
-
-//$4214-$4216
-  uint16 r4214;
-  uint16 r4216;
-} status;
-
-  inline bool   hdma_test();
-  inline bool   nmi_test();
-  inline bool   irq_test();
-
-  inline uint8  pio_status();
-  inline void   run();
-  inline uint32 cycles_executed();
-  inline void   scanline();
-  inline void   frame();
-  inline void   power();
-  inline void   reset();
-
-  inline void   irq_run();
-
-//mmio commands
-  void  mmio_reset();
-  uint8 mmio_r2180();
-  uint8 mmio_r4016();
-  uint8 mmio_r4017();
-  uint8 mmio_r4210();
-  uint8 mmio_r4211();
-  uint8 mmio_r4212();
-  uint8 mmio_r4213();
-  uint8 mmio_r4214();
-  uint8 mmio_r4215();
-  uint8 mmio_r4216();
-  uint8 mmio_r4217();
-  uint8 mmio_r4218();
-  uint8 mmio_r4219();
-  uint8 mmio_r421a();
-  uint8 mmio_r421b();
-  uint8 mmio_r43x0(uint8 i);
-  uint8 mmio_r43x1(uint8 i);
-  uint8 mmio_r43x2(uint8 i);
-  uint8 mmio_r43x3(uint8 i);
-  uint8 mmio_r43x4(uint8 i);
-  uint8 mmio_r43x5(uint8 i);
-  uint8 mmio_r43x6(uint8 i);
-  uint8 mmio_r43x7(uint8 i);
-  uint8 mmio_r43x8(uint8 i);
-  uint8 mmio_r43x9(uint8 i);
-  uint8 mmio_r43xa(uint8 i);
-  uint8 mmio_r43xb(uint8 i);
-  void  mmio_w2180(uint8 value);
-  void  mmio_w2181(uint8 value);
-  void  mmio_w2182(uint8 value);
-  void  mmio_w2183(uint8 value);
-  void  mmio_w4016(uint8 value);
-  void  mmio_w4200(uint8 value);
-  void  mmio_w4201(uint8 value);
-  void  mmio_w4202(uint8 value);
-  void  mmio_w4203(uint8 value);
-  void  mmio_w4204(uint8 value);
-  void  mmio_w4205(uint8 value);
-  void  mmio_w4206(uint8 value);
-  void  mmio_w4207(uint8 value);
-  void  mmio_w4208(uint8 value);
-  void  mmio_w4209(uint8 value);
-  void  mmio_w420a(uint8 value);
-  void  mmio_w420b(uint8 value);
-  void  mmio_w420c(uint8 value);
-  void  mmio_w420d(uint8 value);
-  void  mmio_w43x0(uint8 value, uint8 i);
-  void  mmio_w43x1(uint8 value, uint8 i);
-  void  mmio_w43x2(uint8 value, uint8 i);
-  void  mmio_w43x3(uint8 value, uint8 i);
-  void  mmio_w43x4(uint8 value, uint8 i);
-  void  mmio_w43x5(uint8 value, uint8 i);
-  void  mmio_w43x6(uint8 value, uint8 i);
-  void  mmio_w43x7(uint8 value, uint8 i);
-  void  mmio_w43x8(uint8 value, uint8 i);
-  void  mmio_w43x9(uint8 value, uint8 i);
-  void  mmio_w43xa(uint8 value, uint8 i);
-  void  mmio_w43xb(uint8 value, uint8 i);
-
-  uint8 mmio_read (uint16 addr);
-  void  mmio_write(uint16 addr, uint8 data);
-
-enum { CYCLE_OPREAD, CYCLE_READ, CYCLE_WRITE, CYCLE_IO };
-  inline void pre_exec_cycle();
-  inline void exec_hdma();
-  inline void exec_dma();
-  inline void exec_cycle();
-  inline void last_cycle();
-  inline bool in_opcode();
-
-  bCPU();
-  ~bCPU();
-};

src/cpu/bcpu/bcpu_exec.cpp

@@ -1,174 +0,0 @@
-void bCPU::last_cycle() {
-//DMV27: keep previous nmi value,
-//to allow wai and irq to work properly
-  time.nmi_pending = nmi_test() || time.nmi_pending;
-  time.irq_pending = irq_test();
-}
-
-void bCPU::pre_exec_cycle() {
-  if(!run_state.dma && !run_state.hdma)return;
-
-int c, z;
-  if(run_state.hdma) {
-    switch(status.hdma_state) {
-    case HDMASTATE_ICPUSYNC:
-    case HDMASTATE_CPUSYNC:
-      c = status.cycle_count;
-      z = c - (status.hdma_cycle_count % c);
-      if(!z)z = c;
-      add_cycles(z);
-      run_state.hdma = false;
-      break;
-    }
-  }
-
-  if(run_state.dma) {
-    switch(status.dma_state) {
-    case DMASTATE_CPUSYNC:
-      c = status.cycle_count;
-      z = c - (status.dma_cycle_count % c);
-      if(!z)z = c;
-      add_cycles(z);
-      run_state.dma = false;
-      break;
-    }
-  }
-}
-
-void bCPU::exec_hdma() {
-int n;
-static int z;
-  switch(status.hdma_state) {
-  case HDMASTATE_IDMASYNC:
-    status.hdma_cycle_count = 0;
-    z = 0;
-    if(!run_state.dma) {
-      exec_cycle();
-      status.hdma_state = HDMASTATE_IDMASYNC2;
-    } else {
-      status.hdma_state = HDMASTATE_IDMASYNC3;
-    }
-    break;
-  case HDMASTATE_IDMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.hdma_cycle_count += n;
-    status.hdma_state = HDMASTATE_IDMASYNC3;
-    break;
-  case HDMASTATE_IDMASYNC3:
-    channel[z].hdma_active = channel[z].hdma_enabled;
-    if(channel[z].hdma_enabled) {
-      channel[z].hdma_addr = channel[z].srcaddr;
-      hdma_update(z); //updates status.hdma_cycle_count
-    }
-    if(++z < 8)break;
-    if(!run_state.dma) {
-      status.hdma_state = HDMASTATE_ICPUSYNC;
-    } else {
-      run_state.hdma = false;
-    }
-    break;
-  case HDMASTATE_ICPUSYNC:
-    exec_cycle();
-    break;
-
-  case HDMASTATE_DMASYNC:
-    status.hdma_cycle_count = 0;
-    z = 0;
-    if(!run_state.dma) {
-      exec_cycle();
-      status.hdma_state = HDMASTATE_DMASYNC2;
-    } else {
-      status.hdma_state = HDMASTATE_DMASYNC3;
-    }
-    break;
-  case HDMASTATE_DMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.hdma_cycle_count += n;
-    status.hdma_state = HDMASTATE_DMASYNC3;
-    break;
-  case HDMASTATE_DMASYNC3:
-    if(channel[z].hdma_active) {
-      add_cycles(8);
-      status.hdma_cycle_count += 8;
-    }
-    if(++z < 8)break;
-    status.hdma_state = HDMASTATE_RUN;
-    break;
-  case HDMASTATE_RUN:
-    hdma_run(); //updates status.hdma_cycle_count
-    if(!run_state.dma) {
-      status.hdma_state = HDMASTATE_CPUSYNC;
-    } else {
-      run_state.hdma = false;
-    }
-    break;
-  case HDMASTATE_CPUSYNC:
-    exec_cycle();
-    break;
-  }
-}
-
-void bCPU::exec_dma() {
-int n;
-static int z;
-  switch(status.dma_state) {
-  case DMASTATE_DMASYNC:
-    exec_cycle();
-    status.dma_state = DMASTATE_DMASYNC2;
-    break;
-  case DMASTATE_DMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.dma_cycle_count = n;
-    z = 0;
-    status.dma_state = DMASTATE_DMASYNC3;
-    break;
-  case DMASTATE_DMASYNC3:
-    if(channel[z].active == true) {
-      add_cycles(8);
-      status.dma_cycle_count += 8;
-    }
-    if(++z < 8)break;
-    status.dma_state = DMASTATE_RUN;
-    break;
-  case DMASTATE_RUN:
-    dma_run(); //updates status.dma_cycle_count
-    cycle_edge();
-    break;
-  case DMASTATE_CPUSYNC:
-    exec_cycle();
-    break;
-  }
-}
-
-void bCPU::exec_cycle() {
-//irq active? run one bus cycle of the irq event and return
-  if(run_state.irq) {
-    irq_run();
-    return;
-  }
-
-  if(status.cycle_pos) {
-    (this->*optbl[status.opcode])();
-  #ifdef DEBUGGER
-    if(status.cycle_pos == 0) {
-      snes->notify(SNES::CPU_EXEC_OPCODE_END);
-    }
-  #endif
-    return;
-  }
-
-//on first cycle?
-#ifdef DEBUGGER
-  snes->notify(SNES::CPU_EXEC_OPCODE_BEGIN);
-#endif
-  status.opcode = op_read();
-  status.cycle_pos = 1;
-}
-
-//only return true when we are on an opcode edge
-bool bCPU::in_opcode() {
-  return (status.cycle_pos != 0);
-}

src/cpu/bcpu/bcpu_int.cpp

@@ -1,88 +0,0 @@
-/*
-[IRQ cycles]
-  [0] pbr,pc ; opcode
-  [1] pbr,pc ; io
-  [2] 0,s    ; pbr
-  [3] 0,s-1  ; pch
-  [4] 0,s-2  ; pcl
-  [5] 0,s-3  ; p
-  [6] 0,va   ; aavl
-  [7] 0,va+1 ; aavh
-*/
-void bCPU::irq_run() {
-//WDC documentation is incorrect, first cycle
-//is a memory read fetch from PBR:PC
-  switch(status.cycle_pos++) {
-  case 0:
-  //read from PBR:PC, but do not increment PC counter
-    mem_read(regs.pc.d);
-    break;
-  case 1:
-    cpu_io();
-    if(regs.e)status.cycle_pos++;
-    break;
-  case 2:
-    stack_write(regs.pc.b);
-    break;
-  case 3:
-    stack_write(regs.pc.h);
-    break;
-  case 4:
-    stack_write(regs.pc.l);
-    break;
-  case 5:
-  //emulation-mode irqs clear brk bit 0x10
-    stack_write((regs.e) ? (regs.p & ~0x10) : regs.p);
-    break;
-  case 6:
-  //todo: test if NMI can override IRQ here...
-    rd.l = op_read(OPMODE_ADDR, aa.w);
-    regs.pc.b = 0x00;
-    regs.p.i  = 1;
-    regs.p.d  = 0;
-    break;
-  case 7:
-    rd.h = op_read(OPMODE_ADDR, aa.w + 1);
-    regs.pc.w = rd.w;
-  #ifdef DEBUGGER
-  //let debugger know the new IRQ opcode address
-    snes->notify(SNES::CPU_EXEC_OPCODE_END);
-  #endif
-    status.cycle_pos = 0;
-    run_state.irq = false;
-    break;
-  }
-}
-
-bool bCPU::nmi_test() {
-  if(time.nmi_transition == 0)return false;
-  time.nmi_transition = 0;
-
-  run_state.wai = false;
-  return true;
-}
-
-bool bCPU::irq_test() {
-  if(time.irq_transition == 1)goto _true;
-
-  if(time.irq_read == 0) {
-    if(time.irq_line == 1 && (irq_trigger_pos_match(0) || irq_trigger_pos_match(2))) {
-      return false;
-    }
-    goto _true;
-  }
-
-  if(time.irq_line == 0) {
-    time.irq_line = 1;
-    goto _true;
-  }
-
-  return false;
-
-_true:
-  time.irq_transition = 0;
-
-  run_state.wai = false;
-  if(regs.p.i)return false;
-  return true;
-}

src/cpu/bcpu/bcpu_mmio.cpp

@@ -1,652 +0,0 @@
-void bCPU::mmio_reset() {
-//$2181-$2183
-  status.wram_addr = 0x000000;
-
-//$4016-$4017
-  status.joypad_strobe_latch = 0;
-  status.joypad1_read_pos    = 0;
-  status.joypad2_read_pos    = 0;
-
-//$4200
-  status.nmi_enabled      = false;
-  status.hirq_enabled     = false;
-  status.virq_enabled     = false;
-  status.auto_joypad_poll = false;
-
-//$4201
-  status.pio = 0xff;
-
-//$4202-$4203
-  status.mul_a = 0xff;
-  status.mul_b = 0xff;
-
-//$4204-$4206
-  status.div_a = 0xffff;
-  status.div_b = 0xff;
-
-//$4207-$420a
-  status.hirq_pos = 0x01ff;
-  status.virq_pos = 0x01ff;
-
-//$4214-$4217
-  status.r4214 = 0x0000;
-  status.r4216 = 0x0000;
-}
-
-//WMDATA
-uint8 bCPU::mmio_r2180() {
-uint8 r;
-  r = r_mem->read(0x7e0000 | status.wram_addr);
-  status.wram_addr++;
-  status.wram_addr &= 0x01ffff;
-  return r;
-}
-
-//JOYSER0
-//7-2 = MDR
-//1-0 = Joypad serial data
-/* The joypad contains a small bit shifter that has 16 bits.
- * Reading from 4016 reads one bit from this buffer, then moves
- * the buffer left one, and adds a '1' to the rightmost bit.
- * Writing a one to $4016 will fill the buffer with the current
- * joypad button states, and lock the bit shifter at position
- * zero. All reads will be the first buffer state, or 'B'.
- * A zero must be written back to $4016 to unlock the buffer,
- * so that reads will increment the bit shifting position.
- */
-uint8 bCPU::mmio_r4016() {
-uint8 r;
-  r = regs.mdr & 0xfc;
-
-  if(status.joypad_strobe_latch == 1) {
-    r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_B);
-  } else {
-    switch(status.joypad1_read_pos) {
-    case  0: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_B);      break;
-    case  1: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_Y);      break;
-    case  2: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_SELECT); break;
-    case  3: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_START);  break;
-    case  4: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_UP);     break;
-    case  5: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_DOWN);   break;
-    case  6: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_LEFT);   break;
-    case  7: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_RIGHT);  break;
-    case  8: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_A);      break;
-    case  9: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_X);      break;
-    case 10: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_L);      break;
-    case 11: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_R);      break;
-    case 12: break;
-    case 13: break;
-    case 14: break;
-    case 15: break; //bits 12-15 always return 0
-  //all subsequent reads return joypad connection status
-    case 16: r |= 1; break; //joypad connected bit
-    }
-    if(++status.joypad1_read_pos > 16)status.joypad1_read_pos = 16;
-  }
-
-  return r;
-}
-
-//JOYSER1
-//7-5 = MDR
-//4-2 = Always 1 (pins are connected to GND)
-//1-0 = Joypad serial data
-uint8 bCPU::mmio_r4017() {
-uint8 r;
-  r  = regs.mdr & 0xe0;
-  r |= 0x1c;
-
-  if(status.joypad_strobe_latch == 1) {
-    r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_B);
-  } else {
-    switch(status.joypad2_read_pos) {
-    case  0: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_B);      break;
-    case  1: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_Y);      break;
-    case  2: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_SELECT); break;
-    case  3: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_START);  break;
-    case  4: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_UP);     break;
-    case  5: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_DOWN);   break;
-    case  6: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_LEFT);   break;
-    case  7: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_RIGHT);  break;
-    case  8: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_A);      break;
-    case  9: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_X);      break;
-    case 10: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_L);      break;
-    case 11: r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_R);      break;
-    case 12: break;
-    case 13: break;
-    case 14: break;
-    case 15: break; //bits 12-15 always return 0
-  //all subsequent reads return joypad connection status
-    case 16: r |= 1; break; //joypad connected bit
-    }
-    if(++status.joypad2_read_pos > 16)status.joypad2_read_pos = 16;
-  }
-
-  return r;
-}
-
-//RDNMI
-//7   = NMI acknowledge
-//6-4 = MDR
-//3-0 = CPU (5a22) version
-uint8 bCPU::mmio_r4210() {
-uint8 r;
-  r  = regs.mdr & 0x70;
-  r |= uint8(!time.nmi_read) << 7;
-
-  if(!nmi_trigger_pos_match(0) && !nmi_trigger_pos_match(2)) {
-    time.nmi_read = 1;
-  }
-
-  r |= (cpu_version & 0x0f);
-  return r;
-}
-
-//TIMEUP
-//7   = IRQ acknowledge
-//6-0 = MDR
-uint8 bCPU::mmio_r4211() {
-uint8 r;
-  r  = regs.mdr & 0x7f;
-  r |= uint8(!time.irq_read) << 7;
-
-  if(!irq_trigger_pos_match(0) && !irq_trigger_pos_match(2)) {
-    time.irq_read = 1;
-    time.irq_line = 1;
-    time.irq_transition = 0;
-  }
-
-  return r;
-}
-
-//HVBJOY
-//7   = in vblank
-//6   = in hblank
-//5-1 = MDR
-//0   = joypad ready
-uint8 bCPU::mmio_r4212() {
-uint8 r;
-  r = regs.mdr & 0x3e;
-
-uint16 vs = overscan() ? 240 : 225;
-
-//auto joypad polling
-  if(time.v >= vs && time.v <= (vs + 2))r |= 0x01;
-
-//hblank
-  if(time.hc <= 2 || time.hc >= 1096)r |= 0x40;
-
-//vblank
-  if(time.v >= vs)r |= 0x80;
-
-  return r;
-}
-
-//RDIO
-uint8 bCPU::mmio_r4213() {
-  return status.pio;
-}
-
-//RDDIVL
-uint8 bCPU::mmio_r4214() {
-  return status.r4214;
-}
-
-//RDDIVH
-uint8 bCPU::mmio_r4215() {
-  return status.r4214 >> 8;
-}
-
-//RDMPYL
-uint8 bCPU::mmio_r4216() {
-  return status.r4216;
-}
-
-//RDMPYH
-uint8 bCPU::mmio_r4217() {
-  return status.r4216 >> 8;
-}
-
-//JOY1L
-uint8 bCPU::mmio_r4218() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_A) << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_X) << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_L) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_R) << 4;
-  return r;
-}
-
-//JOY1H
-uint8 bCPU::mmio_r4219() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_B)      << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_Y)      << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_SELECT) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_START)  << 4;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_UP)     << 3;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_DOWN)   << 2;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_LEFT)   << 1;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD1, SNES::JOYPAD_RIGHT);
-  return r;
-}
-
-//JOY2L
-uint8 bCPU::mmio_r421a() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_A) << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_X) << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_L) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_R) << 4;
-  return r;
-}
-
-//JOY2H
-uint8 bCPU::mmio_r421b() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_B)      << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_Y)      << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_SELECT) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_START)  << 4;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_UP)     << 3;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_DOWN)   << 2;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_LEFT)   << 1;
-  r |= (uint8)snes->get_input_status(SNES::DEV_JOYPAD2, SNES::JOYPAD_RIGHT);
-  return r;
-}
-
-//DMAPx
-uint8 bCPU::mmio_r43x0(uint8 i) {
-  return channel[i].dmap;
-}
-
-//BBADx
-uint8 bCPU::mmio_r43x1(uint8 i) {
-  return channel[i].destaddr;
-}
-
-//A1TxL
-uint8 bCPU::mmio_r43x2(uint8 i) {
-  return channel[i].srcaddr;
-}
-
-//A1TxH
-uint8 bCPU::mmio_r43x3(uint8 i) {
-  return channel[i].srcaddr >> 8;
-}
-
-//A1Bx
-uint8 bCPU::mmio_r43x4(uint8 i) {
-  return channel[i].srcbank;
-}
-
-//DASxL
-uint8 bCPU::mmio_r43x5(uint8 i) {
-  return channel[i].xfersize;
-}
-
-//DASxH
-uint8 bCPU::mmio_r43x6(uint8 i) {
-  return channel[i].xfersize >> 8;
-}
-
-//DASBx
-uint8 bCPU::mmio_r43x7(uint8 i) {
-  return channel[i].hdma_ibank;
-}
-
-//A2AxL
-uint8 bCPU::mmio_r43x8(uint8 i) {
-  return channel[i].hdma_addr;
-}
-
-//A2AxH
-uint8 bCPU::mmio_r43x9(uint8 i) {
-  return channel[i].hdma_addr >> 8;
-}
-
-//NTRLx
-uint8 bCPU::mmio_r43xa(uint8 i) {
-  return channel[i].hdma_line_counter;
-}
-
-//???
-uint8 bCPU::mmio_r43xb(uint8 i) {
-  return channel[i].hdma_unknown;
-}
-
-uint8 bCPU::mmio_read(uint16 addr) {
-//APU
-  if(addr >= 0x2140 && addr <= 0x217f) {
-    return r_apu->port_read(addr & 3);
-  }
-
-//HDMA
-  if(addr >= 0x4300 && addr <= 0x437f) {
-  uint i = (addr >> 4) & 7;
-    switch(addr & 0xf) {
-    case 0x0: return mmio_r43x0(i);
-    case 0x1: return mmio_r43x1(i);
-    case 0x2: return mmio_r43x2(i);
-    case 0x3: return mmio_r43x3(i);
-    case 0x4: return mmio_r43x4(i);
-    case 0x5: return mmio_r43x5(i);
-    case 0x6: return mmio_r43x6(i);
-    case 0x7: return mmio_r43x7(i);
-    case 0x8: return mmio_r43x8(i);
-    case 0x9: return mmio_r43x9(i);
-    case 0xa: return mmio_r43xa(i);
-    case 0xb: return mmio_r43xb(i);
-    case 0xc: return regs.mdr; //unmapped
-    case 0xd: return regs.mdr; //unmapped
-    case 0xe: return regs.mdr; //unmapped
-    case 0xf: return mmio_r43xb(i); //mirror of 43xb
-    }
-  }
-
-  switch(addr) {
-  case 0x2180: return mmio_r2180(); //WMDATA
-  case 0x4016: return mmio_r4016(); //JOYSER0
-  case 0x4017: return mmio_r4017(); //JOYSER1
-  case 0x4210: return mmio_r4210(); //RDNMI
-  case 0x4211: return mmio_r4211(); //TIMEUP
-  case 0x4212: return mmio_r4212(); //HVBJOY
-  case 0x4213: return mmio_r4213(); //RDIO
-  case 0x4214: return mmio_r4214(); //RDDIVL
-  case 0x4215: return mmio_r4215(); //RDDIVH
-  case 0x4216: return mmio_r4216(); //RDMPYL
-  case 0x4217: return mmio_r4217(); //RDMPYH
-  case 0x4218: return mmio_r4218(); //JOY1L
-  case 0x4219: return mmio_r4219(); //JOY1H
-  case 0x421a: return mmio_r421a(); //JOY2L
-  case 0x421b: return mmio_r421b(); //JOY2H
-  case 0x421c: return 0x00;
-  case 0x421d: return 0x00;
-  case 0x421e: return 0x00;
-  case 0x421f: return 0x00;
-  }
-
-  return regs.mdr;
-}
-
-//WMDATA
-void bCPU::mmio_w2180(uint8 value) {
-  r_mem->write(0x7e0000 | status.wram_addr, value);
-  status.wram_addr++;
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDL
-void bCPU::mmio_w2181(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0xffff00) | value;
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDM
-void bCPU::mmio_w2182(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0xff00ff) | (value << 8);
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDH
-void bCPU::mmio_w2183(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0x00ffff) | (value << 16);
-  status.wram_addr &= 0x01ffff;
-}
-
-//JOYSER0
-//bit 0 is shared between JOYSER0 and JOYSER1, therefore
-//strobing $4016.d0 affects both controller port latches.
-//$4017 bit 0 writes are ignored.
-void bCPU::mmio_w4016(uint8 value) {
-  status.joypad_strobe_latch = bool(value & 1);
-
-  if(status.joypad_strobe_latch == 1) {
-    snes->poll_input(SNES::DEV_JOYPAD1);
-    snes->poll_input(SNES::DEV_JOYPAD2);
-    status.joypad1_read_pos = 0;
-    status.joypad2_read_pos = 0;
-  }
-}
-
-//NMITIMEN
-void bCPU::mmio_w4200(uint8 value) {
-  status.nmi_enabled      = bool(value & 0x80);
-  status.virq_enabled     = bool(value & 0x20);
-  status.hirq_enabled     = bool(value & 0x10);
-  status.auto_joypad_poll = bool(value & 0x01);
-
-  if(time.nmi_read == 0) {
-    if(time.nmi_line == 1 && !status.nmi_enabled == 0) {
-      time.nmi_transition = 1;
-    }
-    time.nmi_line = !status.nmi_enabled;
-  }
-
-  if(status.virq_enabled == false && status.hirq_enabled == false) {
-    time.irq_line = 1;
-    time.irq_read = 1;
-    time.irq_transition = 0;
-  }
-
-  update_interrupts();
-}
-
-//WRIO
-void bCPU::mmio_w4201(uint8 value) {
-  if((status.pio & 0x80) && !(value & 0x80)) {
-    r_ppu->latch_counters();
-  }
-  status.pio = value;
-}
-
-//WRMPYA
-void bCPU::mmio_w4202(uint8 value) {
-  status.mul_a = value;
-}
-
-void bCPU::mmio_w4203(uint8 value) {
-  status.mul_b = value;
-  status.r4216 = status.mul_a * status.mul_b;
-}
-
-//WRDIVL
-void bCPU::mmio_w4204(uint8 value) {
-  status.div_a = (status.div_a & 0xff00) | value;
-}
-
-//WRDIVH
-void bCPU::mmio_w4205(uint8 value) {
-  status.div_a = (status.div_a & 0x00ff) | (value << 8);
-}
-
-//WRDIVB
-void bCPU::mmio_w4206(uint8 value) {
-  status.div_b = value;
-  status.r4214 = (status.div_b) ? status.div_a / status.div_b : 0xffff;
-  status.r4216 = (status.div_b) ? status.div_a % status.div_b : status.div_a;
-}
-
-//HTIMEL
-void bCPU::mmio_w4207(uint8 value) {
-  status.hirq_pos = (status.hirq_pos & 0xff00) | value;
-  update_interrupts();
-}
-
-//HTIMEH
-void bCPU::mmio_w4208(uint8 value) {
-  status.hirq_pos = (status.hirq_pos & 0x00ff) | (value << 8);
-  update_interrupts();
-}
-
-//VTIMEL
-void bCPU::mmio_w4209(uint8 value) {
-  status.virq_pos = (status.virq_pos & 0xff00) | value;
-  update_interrupts();
-}
-
-//VTIMEH
-void bCPU::mmio_w420a(uint8 value) {
-  status.virq_pos = (status.virq_pos & 0x00ff) | (value << 8);
-  update_interrupts();
-}
-
-//DMAEN
-void bCPU::mmio_w420b(uint8 value) {
-  if(value != 0x00) {
-    run_state.dma = true;
-    status.dma_state = DMASTATE_DMASYNC;
-  }
-
-  for(int i = 0; i < 8; i++) {
-    if(value & (1 << i)) {
-    //DMA enable does not disable active HDMA channels
-      channel[i].active     = true;
-      channel[i].read_index = 0;
-    }
-  }
-}
-
-//HDMAEN
-void bCPU::mmio_w420c(uint8 value) {
-  for(int i = 0; i < 8; i++) {
-    channel[i].hdma_enabled = bool(value & (1 << i));
-    channel[i].hdma_active  = bool(value & (1 << i));
-  }
-}
-
-//MEMSEL
-void bCPU::mmio_w420d(uint8 value) {
-  r_mem->set_speed(value & 1);
-}
-
-//DMAPx
-void bCPU::mmio_w43x0(uint8 value, uint8 i) {
-  channel[i].dmap          = value;
-  channel[i].direction     = bool(value & 0x80);
-  channel[i].hdma_indirect = bool(value & 0x40);
-  channel[i].incmode       = (value & 0x10) ? -1 : 1;
-  channel[i].fixedxfer     = bool(value & 0x08);
-  channel[i].xfermode      = value & 7;
-}
-
-//BBADx
-void bCPU::mmio_w43x1(uint8 value, uint8 i) {
-  channel[i].destaddr = value;
-}
-
-//A1TxL
-void bCPU::mmio_w43x2(uint8 value, uint8 i) {
-  channel[i].srcaddr = (channel[i].srcaddr & 0xff00) | value;
-}
-
-//A1TxH
-void bCPU::mmio_w43x3(uint8 value, uint8 i) {
-  channel[i].srcaddr = (channel[i].srcaddr & 0x00ff) | (value << 8);
-}
-
-//A1Bx
-void bCPU::mmio_w43x4(uint8 value, uint8 i) {
-  channel[i].srcbank = value;
-}
-
-//DASxL
-void bCPU::mmio_w43x5(uint8 value, uint8 i) {
-  channel[i].xfersize = (channel[i].xfersize & 0xff00) | value;
-}
-
-//DASxH
-void bCPU::mmio_w43x6(uint8 value, uint8 i) {
-  channel[i].xfersize = (channel[i].xfersize & 0x00ff) | (value << 8);
-}
-
-//DASBx
-void bCPU::mmio_w43x7(uint8 value, uint8 i) {
-  channel[i].hdma_ibank = value;
-}
-
-//A2AxL
-void bCPU::mmio_w43x8(uint8 value, uint8 i) {
-  channel[i].hdma_addr = (channel[i].hdma_addr & 0xff00) | value;
-}
-
-//A2AxH
-void bCPU::mmio_w43x9(uint8 value, uint8 i) {
-  channel[i].hdma_addr = (channel[i].hdma_addr & 0x00ff) | (value << 8);
-}
-
-//NTRLx
-void bCPU::mmio_w43xa(uint8 value, uint8 i) {
-  channel[i].hdma_line_counter = value;
-}
-
-//???
-void bCPU::mmio_w43xb(uint8 value, uint8 i) {
-  channel[i].hdma_unknown = value;
-}
-
-void bCPU::mmio_write(uint16 addr, uint8 data) {
-//APU
-  if(addr >= 0x2140 && addr <= 0x217f) {
-    port_write(addr & 3, data);
-    return;
-  }
-
-//HDMA
-  if(addr >= 0x4300 && addr <= 0x437f) {
-  uint i = (addr >> 4) & 7;
-    switch(addr & 0xf) {
-    case 0x0: mmio_w43x0(data, i); return;
-    case 0x1: mmio_w43x1(data, i); return;
-    case 0x2: mmio_w43x2(data, i); return;
-    case 0x3: mmio_w43x3(data, i); return;
-    case 0x4: mmio_w43x4(data, i); return;
-    case 0x5: mmio_w43x5(data, i); return;
-    case 0x6: mmio_w43x6(data, i); return;
-    case 0x7: mmio_w43x7(data, i); return;
-    case 0x8: mmio_w43x8(data, i); return;
-    case 0x9: mmio_w43x9(data, i); return;
-    case 0xa: mmio_w43xa(data, i); return;
-    case 0xb: mmio_w43xb(data, i); return;
-    case 0xc: return; //unmapped
-    case 0xd: return; //unmapped
-    case 0xe: return; //unmapped
-    case 0xf: mmio_w43xb(data, i); return; //mirror of 43xb
-    }
-  }
-
-  switch(addr) {
-  case 0x2180: mmio_w2180(data); return; //WMDATA
-  case 0x2181: mmio_w2181(data); return; //WMADDL
-  case 0x2182: mmio_w2182(data); return; //WMADDM
-  case 0x2183: mmio_w2183(data); return; //WMADDH
-  case 0x4016: mmio_w4016(data); return; //JOYSER0
-  case 0x4017: return; //unmapped
-  case 0x4200: mmio_w4200(data); return; //NMITIMEN
-  case 0x4201: mmio_w4201(data); return; //WRIO
-  case 0x4202: mmio_w4202(data); return; //WRMPYA
-  case 0x4203: mmio_w4203(data); return; //WRMPYB
-  case 0x4204: mmio_w4204(data); return; //WRDIVL
-  case 0x4205: mmio_w4205(data); return; //WRDIVH
-  case 0x4206: mmio_w4206(data); return; //WRDIVB
-  case 0x4207: mmio_w4207(data); return; //HTIMEL
-  case 0x4208: mmio_w4208(data); return; //HTIMEH
-  case 0x4209: mmio_w4209(data); return; //VTIMEL
-  case 0x420a: mmio_w420a(data); return; //VTIMEH
-  case 0x420b: mmio_w420b(data); return; //DMAEN
-  case 0x420c: mmio_w420c(data); return; //HDMAEN
-  case 0x420d: mmio_w420d(data); return; //MEMSEL
-  }
-}

src/cpu/bcpu/core/cc.bat

@@ -1,3 +0,0 @@
-cl /O2 /wd4996 bcpugen.cpp
-@pause
-@del *.obj

src/cpu/bcpu/core/clean.bat

@@ -1,8 +0,0 @@
-@del *.exe
-@del op_misc.cpp
-@del op_pc.cpp
-@del op_read.cpp
-@del op_rmw.cpp
-@del op_write.cpp
-@del optable.cpp
-@del op.h

src/cpu/bcpu/core/core.cpp

@@ -1,90 +0,0 @@
-#include "opfn.cpp"
-#include "op_read.cpp"
-#include "op_rmw.cpp"
-#include "op_write.cpp"
-#include "op_pc.cpp"
-#include "op_misc.cpp"
-
-void bCPU::cpu_c2() {
-  if(regs.d.l != 0x00) {
-    cpu_io();
-  }
-}
-
-void bCPU::cpu_c4(uint16 x, uint16 y) {
-  if(!regs.p.x && (x & 0xff00) != (y & 0xff00)) {
-    cpu_io();
-  }
-}
-
-void bCPU::cpu_c6(uint16 addr) {
-  if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
-    cpu_io();
-  }
-}
-
-uint32 bCPU::op_addr(uint8 mode, uint32 addr) {
-  switch(mode) {
-  case OPMODE_ADDR:
-    addr &= 0xffff;
-    break;
-  case OPMODE_LONG:
-    addr &= 0xffffff;
-    break;
-  case OPMODE_DBR:
-    addr = ((regs.db << 16) + addr) & 0xffffff;
-    break;
-  case OPMODE_PBR:
-    addr &= 0xffff;
-    addr = (regs.pc.b << 16) + addr;
-    break;
-  case OPMODE_DP:
-    addr &= 0xffff;
-    addr = (regs.d + addr) & 0xffff;
-    break;
-  case OPMODE_SP:
-    addr &= 0xffff;
-    addr = (regs.s + addr) & 0xffff;
-    break;
-  }
-  return addr;
-}
-
-uint8 bCPU::op_read() {
-uint8 r;
-  r = mem_read(regs.pc.d);
-  regs.pc.w++;
-  return r;
-}
-
-uint8 bCPU::op_read(uint8 mode, uint32 addr) {
-  addr = op_addr(mode, addr);
-  return mem_read(addr);
-}
-
-void bCPU::op_write(uint8 mode, uint32 addr, uint8 value) {
-  addr = op_addr(mode, addr);
-  mem_write(addr, value);
-}
-
-uint8 bCPU::stack_read() {
-  if(regs.e) {
-    regs.s.l++;
-  } else {
-    regs.s.w++;
-  }
-  return mem_read(regs.s);
-}
-
-void bCPU::stack_write(uint8 value) {
-  mem_write(regs.s, value);
-  if(regs.e) {
-    regs.s.l--;
-  } else {
-    regs.s.w--;
-  }
-}
-
-void bCPU::init_op_tables() {
-  #include "optable.cpp"
-}

src/cpu/bcpu/core/core.h

@@ -1,74 +0,0 @@
-/* External functions:
- *   void   last_cycle();
- *   void   cpu_io();
- *   uint8  mem_read(uint32 addr);
- *   void   mem_write(uint32 addr, uint8 value);
- */
-
-void (bCPU::*optbl[256])();
-
-CPUReg24 aa, rd;
-uint8    dp, sp;
-
-//op_read
-  inline void   op_adc_b();
-  inline void   op_adc_w();
-  inline void   op_and_b();
-  inline void   op_and_w();
-  inline void   op_bit_b();
-  inline void   op_bit_w();
-  inline void   op_cmp_b();
-  inline void   op_cmp_w();
-  inline void   op_cpx_b();
-  inline void   op_cpx_w();
-  inline void   op_cpy_b();
-  inline void   op_cpy_w();
-  inline void   op_eor_b();
-  inline void   op_eor_w();
-  inline void   op_lda_b();
-  inline void   op_lda_w();
-  inline void   op_ldx_b();
-  inline void   op_ldx_w();
-  inline void   op_ldy_b();
-  inline void   op_ldy_w();
-  inline void   op_ora_b();
-  inline void   op_ora_w();
-  inline void   op_sbc_b();
-  inline void   op_sbc_w();
-//op_rmw
-  inline void   op_inc_b();
-  inline void   op_inc_w();
-  inline void   op_dec_b();
-  inline void   op_dec_w();
-  inline void   op_asl_b();
-  inline void   op_asl_w();
-  inline void   op_lsr_b();
-  inline void   op_lsr_w();
-  inline void   op_rol_b();
-  inline void   op_rol_w();
-  inline void   op_ror_b();
-  inline void   op_ror_w();
-  inline void   op_trb_b();
-  inline void   op_trb_w();
-  inline void   op_tsb_b();
-  inline void   op_tsb_w();
-
-  inline void   cpu_c2();
-  inline void   cpu_c4(uint16 x, uint16 y);
-  inline void   cpu_c6(uint16 addr);
-
-enum {
-  OPMODE_ADDR, OPMODE_LONG,
-  OPMODE_DBR,  OPMODE_PBR,
-  OPMODE_DP,   OPMODE_SP
-};
-  inline uint32 op_addr(uint8 mode, uint32 addr);
-  inline uint8  op_read();
-  inline uint8  op_read(uint8 mode, uint32 addr);
-  inline void   op_write(uint8 mode, uint32 addr, uint8 value);
-  inline uint8  stack_read();
-  inline void   stack_write(uint8 value);
-
-  inline void   init_op_tables();
-
-#include "op.h"

src/cpu/bcpu/core/op_misc.cpp

@@ -1,864 +0,0 @@
-void bCPU::op_nop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_wdm() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    op_read();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_xba() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.a.l ^= regs.a.h;
-    regs.a.h ^= regs.a.l;
-    regs.a.l ^= regs.a.h;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_mvn() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    sp = op_read();
-    } break;
-  case 3: {
-    regs.db = dp;
-    rd.l = op_read(OPMODE_LONG, (sp << 16) | regs.x.w);
-    } break;
-  case 4: {
-    op_write(OPMODE_LONG, (dp << 16) | regs.y.w, rd.l);
-    } break;
-  case 5: {
-    cpu_io();
-    if(regs.p.x) { regs.x.l++; regs.y.l++; }
-    else         { regs.x.w++; regs.y.w++; }
-    } break;
-  case 6: {
-    last_cycle();
-    cpu_io();
-    if(regs.a.w--)regs.pc.w -= 3;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_mvp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    sp = op_read();
-    } break;
-  case 3: {
-    regs.db = dp;
-    rd.l = op_read(OPMODE_LONG, (sp << 16) | regs.x.w);
-    } break;
-  case 4: {
-    op_write(OPMODE_LONG, (dp << 16) | regs.y.w, rd.l);
-    } break;
-  case 5: {
-    cpu_io();
-    if(regs.p.x) { regs.x.l--; regs.y.l--; }
-    else         { regs.x.w--; regs.y.w--; }
-    } break;
-  case 6: {
-    last_cycle();
-    cpu_io();
-    if(regs.a.w--)regs.pc.w -= 3;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_brk() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    op_read();
-    if(regs.e)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.pc.b);
-    } break;
-  case 3: {
-    stack_write(regs.pc.h);
-    } break;
-  case 4: {
-    stack_write(regs.pc.l);
-    } break;
-  case 5: {
-    stack_write(regs.p);
-    } break;
-  case 6: {
-    rd.l = op_read(OPMODE_LONG, (regs.e) ? 0xfffe : 0xffe6);
-    regs.pc.b = 0x00;
-    regs.p.i  = 1;
-    regs.p.d  = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_read(OPMODE_LONG, (regs.e) ? 0xffff : 0xffe7);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    op_read();
-    if(regs.e)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.pc.b);
-    } break;
-  case 3: {
-    stack_write(regs.pc.h);
-    } break;
-  case 4: {
-    stack_write(regs.pc.l);
-    } break;
-  case 5: {
-    stack_write(regs.p);
-    } break;
-  case 6: {
-    rd.l = op_read(OPMODE_LONG, (regs.e) ? 0xfff4 : 0xffe4);
-    regs.pc.b = 0x00;
-    regs.p.i  = 1;
-    regs.p.d  = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_read(OPMODE_LONG, (regs.e) ? 0xfff5 : 0xffe5);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    run_state.stp = true;
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w--;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_wai() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    run_state.wai = true;
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-  //no wakeup delay if last_cycle() cancelled wai
-    if(run_state.wai == false)status.cycle_pos = 0;
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-  //sleep another i/o cycle
-  //note: this should alert the debugger that wai is continuing...
-    if(run_state.wai == true)status.cycle_pos--;
-  //wai wakeup delay (one i/o cycle)
-    } break;
-  case 4: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_xce() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-  bool c = regs.p.c;
-    regs.p.c = regs.e;
-    regs.e = c;
-    if(regs.e) {
-      regs.p  |= 0x30;
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-      regs.s.h = 0x01;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_clc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.c = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cld() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.d = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cli() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.i = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_clv() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.v = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sec() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.c = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sed() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.d = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sei() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.i = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rep() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.p &=~ rd.l;
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sep() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.p |= rd.l;
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tax() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.a.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.a.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tay() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.y.l = regs.a.l;
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-    } else {
-      regs.y.w = regs.a.w;
-      regs.p.n = !!(regs.y.w & 0x8000);
-      regs.p.z = (regs.y.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txa() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.m) {
-      regs.a.l = regs.x.l;
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.a.w = regs.x.w;
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.y.l = regs.x.l;
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-    } else {
-      regs.y.w = regs.x.w;
-      regs.p.n = !!(regs.y.w & 0x8000);
-      regs.p.z = (regs.y.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tya() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.m) {
-      regs.a.l = regs.y.l;
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.a.w = regs.y.w;
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tyx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.y.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.y.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tcd() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.d.w = regs.a.w;
-    regs.p.n = !!(regs.d.w & 0x8000);
-    regs.p.z = (regs.d.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tcs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.s.w = regs.a.w;
-    if(regs.e)regs.s.h = 0x01;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tdc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.a.w = regs.d.w;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tsc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.a.w = regs.s.w;
-    if(regs.e) {
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tsx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.s.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.s.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.e) {
-      regs.s.l = regs.x.l;
-    } else {
-      regs.s.w = regs.x.w;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pha() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.m)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.a.h);
-    } break;
-  case 3: {
-    last_cycle();
-    stack_write(regs.a.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.x)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.x.h);
-    } break;
-  case 3: {
-    last_cycle();
-    stack_write(regs.x.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.x)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.y.h);
-    } break;
-  case 3: {
-    last_cycle();
-    stack_write(regs.y.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phd() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(0)status.cycle_pos++;
-    } break;
-  case 2: {
-    stack_write(regs.       d.h);
-    } break;
-  case 3: {
-    last_cycle();
-    stack_write(regs.       d.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phb() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    stack_write(regs.db);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phk() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    stack_write(regs.pc.b);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_php() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    stack_write(regs.p);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pla() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    regs.a.l = stack_read();
-    if(regs.p.m) {
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.a.h = stack_read();
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    regs.x.l = stack_read();
-    if(regs.p.x) {
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.x.h = stack_read();
-    regs.p.n = !!(regs.x.w & 0x8000);
-    regs.p.z = (regs.x.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_ply() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    regs.y.l = stack_read();
-    if(regs.p.x) {
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.y.h = stack_read();
-    regs.p.n = !!(regs.y.w & 0x8000);
-    regs.p.z = (regs.y.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pld() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(0)last_cycle();
-    regs.       d.l = stack_read();
-    if(0) {
-      regs.p.n = !!(regs.       d.l & 0x80);
-      regs.p.z = (regs.       d.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.       d.h = stack_read();
-    regs.p.n = !!(regs.       d.w & 0x8000);
-    regs.p.z = (regs.       d.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plb() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    last_cycle();
-    regs.db = stack_read();
-    regs.p.n = !!(regs.db & 0x80);
-    regs.p.z = (regs.db == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    last_cycle();
-    regs.p = stack_read();
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pea() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    stack_write(aa.h);
-    } break;
-  case 4: {
-    last_cycle();
-    stack_write(aa.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pei() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_DP, dp + 1);
-    } break;
-  case 5: {
-    stack_write(aa.h);
-    } break;
-  case 6: {
-    last_cycle();
-    stack_write(aa.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_per() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_io();
-    rd.w = regs.pc.d + (int16)aa.w;
-    } break;
-  case 4: {
-    stack_write(rd.h);
-    } break;
-  case 5: {
-    last_cycle();
-    stack_write(rd.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/cpu/bcpu/core/op_pc.b

@@ -1,160 +0,0 @@
-bcc(0x90, !regs.p.c),
-bcs(0xb0, regs.p.c),
-bne(0xd0, !regs.p.z),
-beq(0xf0, regs.p.z),
-bpl(0x10, !regs.p.n),
-bmi(0x30, regs.p.n),
-bvc(0x50, !regs.p.v),
-bvs(0x70, regs.p.v) {
-1:if(!$1)last_cycle();
-  rd.l = op_read();
-  if($1) {
-    aa.w = regs.pc.d + (int8)rd.l;
-    regs.pc.w = aa.w;
-  } else {
-    end;
-  }
-2:cpu_c6(aa.w);
-3:last_cycle();
-  cpu_io();
-}
-
-bra(0x80) {
-1:rd.l = op_read();
-  aa.w = regs.pc.d + (int8)rd.l;
-  regs.pc.w = aa.w;
-2:cpu_c6(aa.w);
-3:last_cycle();
-  cpu_io();
-}
-
-brl(0x82) {
-1:rd.l = op_read();
-2:rd.h = op_read();
-3:last_cycle();
-  cpu_io();
-  regs.pc.w = regs.pc.d + (int16)rd.w;
-}
-
-jmp_addr(0x4c) {
-1:rd.l = op_read();
-2:last_cycle();
-  rd.h = op_read();
-  regs.pc.w = rd.w;
-}
-
-jmp_long(0x5c) {
-1:rd.l = op_read();
-2:rd.h = op_read();
-3:last_cycle();
-  rd.b = op_read();
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-jmp_iaddr(0x6c) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:rd.l = op_read(OPMODE_ADDR, aa.w);
-4:last_cycle();
-  rd.h = op_read(OPMODE_ADDR, aa.w + 1);
-  regs.pc.w = rd.w;
-}
-
-jmp_iaddrx(0x7c) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:cpu_io();
-4:rd.l = op_read(OPMODE_PBR, aa.w + regs.x.w);
-5:last_cycle();
-  rd.h = op_read(OPMODE_PBR, aa.w + regs.x.w + 1);
-  regs.pc.w = rd.w;
-}
-
-jmp_iladdr(0xdc) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:rd.l = op_read(OPMODE_ADDR, aa.w);
-4:rd.h = op_read(OPMODE_ADDR, aa.w + 1);
-5:last_cycle();
-  rd.b = op_read(OPMODE_ADDR, aa.w + 2);
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-jsr_addr(0x20) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:cpu_io();
-4:regs.pc.w--;
-  stack_write(regs.pc.h);
-5:last_cycle();
-  stack_write(regs.pc.l);
-  regs.pc.w = aa.w;
-}
-
-jsr_long(0x22) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:stack_write(regs.pc.b);
-4:cpu_io();
-5:aa.b = op_read();
-6:regs.pc.w--;
-  stack_write(regs.pc.h);
-7:last_cycle();
-  stack_write(regs.pc.l);
-  regs.pc.d = aa.d & 0xffffff;
-}
-
-jsr_iaddrx(0xfc) {
-1:aa.l = op_read();
-2:stack_write(regs.pc.h);
-3:stack_write(regs.pc.l);
-4:aa.h = op_read();
-5:cpu_io();
-6:rd.l = op_read(OPMODE_PBR, aa.w + regs.x.w);
-7:last_cycle();
-  rd.h = op_read(OPMODE_PBR, aa.w + regs.x.w + 1);
-  regs.pc.w = rd.w;
-}
-
-rti(0x40) {
-1:cpu_io();
-2:cpu_io();
-3:regs.p = stack_read();
-  if(regs.e)regs.p |= 0x30;
-  if(regs.p.x) {
-    regs.x.h = 0x00;
-    regs.y.h = 0x00;
-  }
-4:rd.l = stack_read();
-5:if(regs.e)last_cycle();
-  rd.h = stack_read();
-  if(regs.e) {
-    regs.pc.w = rd.w;
-    end;
-  }
-6:last_cycle();
-  rd.b = stack_read();
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-rts(0x60) {
-1:cpu_io();
-2:cpu_io();
-3:rd.l = stack_read();
-4:rd.h = stack_read();
-5:last_cycle();
-  cpu_io();
-  regs.pc.w = rd.w;
-  regs.pc.w++;
-}
-
-rtl(0x6b) {
-1:cpu_io();
-2:cpu_io();
-3:rd.l = stack_read();
-4:rd.h = stack_read();
-5:last_cycle();
-  rd.b = stack_read();
-  regs.pc.d = rd.d & 0xffffff;
-  regs.pc.w++;
-}

src/cpu/bcpu/core/op_pc.cpp

@@ -1,483 +0,0 @@
-void bCPU::op_bcc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.c)last_cycle();
-    rd.l = op_read();
-    if(!regs.p.c) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bcs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.c)last_cycle();
-    rd.l = op_read();
-    if(regs.p.c) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bne() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.z)last_cycle();
-    rd.l = op_read();
-    if(!regs.p.z) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_beq() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.z)last_cycle();
-    rd.l = op_read();
-    if(regs.p.z) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bpl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.n)last_cycle();
-    rd.l = op_read();
-    if(!regs.p.n) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bmi() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.n)last_cycle();
-    rd.l = op_read();
-    if(regs.p.n) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bvc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.v)last_cycle();
-    rd.l = op_read();
-    if(!regs.p.v) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bvs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.v)last_cycle();
-    rd.l = op_read();
-    if(regs.p.v) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bra() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    aa.w = regs.pc.d + (int8)rd.l;
-    regs.pc.w = aa.w;
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_brl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    } break;
-  case 2: {
-    rd.h = op_read();
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w = regs.pc.d + (int16)rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    } break;
-  case 2: {
-    last_cycle();
-    rd.h = op_read();
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_read();
-    } break;
-  case 2: {
-    rd.h = op_read();
-    } break;
-  case 3: {
-    last_cycle();
-    rd.b = op_read();
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iaddr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    rd.l = op_read(OPMODE_ADDR, aa.w);
-    } break;
-  case 4: {
-    last_cycle();
-    rd.h = op_read(OPMODE_ADDR, aa.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iaddrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    rd.l = op_read(OPMODE_PBR, aa.w + regs.x.w);
-    } break;
-  case 5: {
-    last_cycle();
-    rd.h = op_read(OPMODE_PBR, aa.w + regs.x.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iladdr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    rd.l = op_read(OPMODE_ADDR, aa.w);
-    } break;
-  case 4: {
-    rd.h = op_read(OPMODE_ADDR, aa.w + 1);
-    } break;
-  case 5: {
-    last_cycle();
-    rd.b = op_read(OPMODE_ADDR, aa.w + 2);
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    regs.pc.w--;
-    stack_write(regs.pc.h);
-    } break;
-  case 5: {
-    last_cycle();
-    stack_write(regs.pc.l);
-    regs.pc.w = aa.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    stack_write(regs.pc.b);
-    } break;
-  case 4: {
-    cpu_io();
-    } break;
-  case 5: {
-    aa.b = op_read();
-    } break;
-  case 6: {
-    regs.pc.w--;
-    stack_write(regs.pc.h);
-    } break;
-  case 7: {
-    last_cycle();
-    stack_write(regs.pc.l);
-    regs.pc.d = aa.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_iaddrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    stack_write(regs.pc.h);
-    } break;
-  case 3: {
-    stack_write(regs.pc.l);
-    } break;
-  case 4: {
-    aa.h = op_read();
-    } break;
-  case 5: {
-    cpu_io();
-    } break;
-  case 6: {
-    rd.l = op_read(OPMODE_PBR, aa.w + regs.x.w);
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_read(OPMODE_PBR, aa.w + regs.x.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rti() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    regs.p = stack_read();
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    } break;
-  case 4: {
-    rd.l = stack_read();
-    } break;
-  case 5: {
-    if(regs.e)last_cycle();
-    rd.h = stack_read();
-    if(regs.e) {
-      regs.pc.w = rd.w;
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 6: {
-    last_cycle();
-    rd.b = stack_read();
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rts() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    rd.l = stack_read();
-    } break;
-  case 4: {
-    rd.h = stack_read();
-    } break;
-  case 5: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w = rd.w;
-    regs.pc.w++;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rtl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    rd.l = stack_read();
-    } break;
-  case 4: {
-    rd.h = stack_read();
-    } break;
-  case 5: {
-    last_cycle();
-    rd.b = stack_read();
-    regs.pc.d = rd.d & 0xffffff;
-    regs.pc.w++;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/cpu/bcpu/core/op_write.b

@@ -1,181 +0,0 @@
-sta_addr(0x8d, regs.p.m, regs.a.w),
-stx_addr(0x8e, regs.p.x, regs.x.w),
-sty_addr(0x8c, regs.p.x, regs.y.w),
-stz_addr(0x9c, regs.p.m, 0x0000) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:if($1)last_cycle();
-  op_write(OPMODE_DBR, aa.w,     $2);
-  if($1)end;
-4:last_cycle();
-  op_write(OPMODE_DBR, aa.w + 1, $2 >> 8);
-}
-
-sta_addrx(0x9d, regs.p.m, regs.a.w),
-stz_addrx(0x9e, regs.p.m, 0x0000) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:cpu_c4(aa.w, aa.w + regs.x.w);
-4:if($1)last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.x.w,     $2);
-  if($1)end;
-5:last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.x.w + 1, $2 >> 8);
-}
-
-sta_addry(0x99) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:cpu_c4(aa.w, aa.w + regs.y.w);
-4:if(regs.p.m)last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-}
-
-sta_long(0x8f) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:aa.b = op_read();
-4:if(regs.p.m)last_cycle();
-  op_write(OPMODE_LONG, aa.d,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_write(OPMODE_LONG, aa.d + 1, regs.a.h);
-}
-
-sta_longx(0x9f) {
-1:aa.l = op_read();
-2:aa.h = op_read();
-3:aa.b = op_read();
-4:if(regs.p.m)last_cycle();
-  op_write(OPMODE_LONG, aa.d + regs.x.w,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_write(OPMODE_LONG, aa.d + regs.x.w + 1, regs.a.h);
-}
-
-sta_dp(0x85, regs.p.m, regs.a.w),
-stx_dp(0x86, regs.p.x, regs.x.w),
-sty_dp(0x84, regs.p.x, regs.y.w),
-stz_dp(0x64, regs.p.m, 0x0000) {
-1:dp = op_read();
-2:cpu_c2();
-3:if($1)last_cycle();
-  op_write(OPMODE_DP, dp,     $2);
-  if($1)end;
-4:last_cycle();
-  op_write(OPMODE_DP, dp + 1, $2 >> 8);
-}
-
-sta_dpx(0x95, regs.p.m, regs.a.w),
-sty_dpx(0x94, regs.p.x, regs.y.w),
-stz_dpx(0x74, regs.p.m, 0x0000) {
-1:dp = op_read();
-2:cpu_c2();
-3:cpu_io();
-4:if($1)last_cycle();
-  op_write(OPMODE_DP, dp + regs.x.w,     $2);
-  if($1)end;
-5:last_cycle();
-  op_write(OPMODE_DP, dp + regs.x.w + 1, $2 >> 8);
-}
-
-stx_dpy(0x96) {
-1:dp = op_read();
-2:cpu_c2();
-3:cpu_io();
-4:if(regs.p.x)last_cycle();
-  op_write(OPMODE_DP, dp + regs.y.w,     regs.x.l);
-  if(regs.p.x)end;
-5:last_cycle();
-  op_write(OPMODE_DP, dp + regs.y.w + 1, regs.x.h);
-}
-
-sta_idp(0x92) {
-1:dp = op_read();
-2:cpu_c2();
-3:aa.l = op_read(OPMODE_DP, dp);
-4:aa.h = op_read(OPMODE_DP, dp + 1);
-5:if(regs.p.m)last_cycle();
-  op_write(OPMODE_DBR, aa.w,     regs.a.l);
-  if(regs.p.m)end;
-6:last_cycle();
-  op_write(OPMODE_DBR, aa.w + 1, regs.a.h);
-}
-
-sta_ildp(0x87) {
-1:dp = op_read();
-2:cpu_c2();
-3:aa.l = op_read(OPMODE_DP, dp);
-4:aa.h = op_read(OPMODE_DP, dp + 1);
-5:aa.b = op_read(OPMODE_DP, dp + 2);
-6:if(regs.p.m)last_cycle();
-  op_write(OPMODE_LONG, aa.d,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_write(OPMODE_LONG, aa.d + 1, regs.a.h);
-}
-
-sta_idpx(0x81) {
-1:dp = op_read();
-2:cpu_c2();
-3:cpu_io();
-4:aa.l = op_read(OPMODE_DP, dp + regs.x.w);
-5:aa.h = op_read(OPMODE_DP, dp + regs.x.w + 1);
-6:if(regs.p.m)last_cycle();
-  op_write(OPMODE_DBR, aa.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_write(OPMODE_DBR, aa.w + 1, regs.a.h);
-}
-
-sta_idpy(0x91) {
-1:dp = op_read();
-2:cpu_c2();
-3:aa.l = op_read(OPMODE_DP, dp);
-4:aa.h = op_read(OPMODE_DP, dp + 1);
-5:cpu_c4(aa.w, aa.w + regs.y.w);
-6:if(regs.p.m)last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-}
-
-sta_ildpy(0x97) {
-1:dp = op_read();
-2:cpu_c2();
-3:aa.l = op_read(OPMODE_DP, dp);
-4:aa.h = op_read(OPMODE_DP, dp + 1);
-5:aa.b = op_read(OPMODE_DP, dp + 2);
-6:if(regs.p.m)last_cycle();
-  op_write(OPMODE_LONG, aa.d + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_write(OPMODE_LONG, aa.d + regs.y.w + 1, regs.a.h);
-}
-
-sta_sr(0x83) {
-1:sp = op_read();
-2:cpu_io();
-3:if(regs.p.m)last_cycle();
-  op_write(OPMODE_SP, sp,     regs.a.l);
-  if(regs.p.m)end;
-4:last_cycle();
-  op_write(OPMODE_SP, sp + 1, regs.a.h);
-}
-
-sta_isry(0x93) {
-1:sp = op_read();
-2:cpu_io();
-3:aa.l = op_read(OPMODE_SP, sp);
-4:aa.h = op_read(OPMODE_SP, sp + 1);
-5:cpu_io();
-6:if(regs.p.m)last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-}

src/cpu/bcpu/core/op_write.cpp

@@ -1,582 +0,0 @@
-void bCPU::op_sta_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     regs.x.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, regs.x.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_addrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.x.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.x.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.x.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_addrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.x.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.x.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.x.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_addry() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.y.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    aa.b = op_read();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_LONG, aa.d,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_LONG, aa.d + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_longx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_read();
-    } break;
-  case 2: {
-    aa.h = op_read();
-    } break;
-  case 3: {
-    aa.b = op_read();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_LONG, aa.d + regs.x.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_LONG, aa.d + regs.x.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DP, dp,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DP, dp,     regs.x.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + 1, regs.x.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DP, dp,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DP, dp,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + regs.x.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_dpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.x)last_cycle();
-    op_write(OPMODE_DP, dp + regs.y.w,     regs.x.l);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_write(OPMODE_DP, dp + regs.y.w + 1, regs.x.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_DP, dp + 1);
-    } break;
-  case 5: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 6: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_ildp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_DP, dp + 1);
-    } break;
-  case 5: {
-    aa.b = op_read(OPMODE_DP, dp + 2);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_LONG, aa.d,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_write(OPMODE_LONG, aa.d + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    aa.l = op_read(OPMODE_DP, dp + regs.x.w);
-    } break;
-  case 5: {
-    aa.h = op_read(OPMODE_DP, dp + regs.x.w + 1);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_DP, dp + 1);
-    } break;
-  case 5: {
-    cpu_c4(aa.w, aa.w + regs.y.w);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_ildpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_read();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_DP, dp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_DP, dp + 1);
-    } break;
-  case 5: {
-    aa.b = op_read(OPMODE_DP, dp + 2);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_LONG, aa.d + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_write(OPMODE_LONG, aa.d + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_sr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_SP, sp,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_write(OPMODE_SP, sp + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_isry() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_read();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    aa.l = op_read(OPMODE_SP, sp);
-    } break;
-  case 4: {
-    aa.h = op_read(OPMODE_SP, sp + 1);
-    } break;
-  case 5: {
-    cpu_io();
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_write(OPMODE_DBR, aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-

src/cpu/bcpu/core/optable.cpp

@@ -1,256 +0,0 @@
-optbl[0x69] = &bCPU::op_adc_const;
-optbl[0x29] = &bCPU::op_and_const;
-optbl[0xc9] = &bCPU::op_cmp_const;
-optbl[0xe0] = &bCPU::op_cpx_const;
-optbl[0xc0] = &bCPU::op_cpy_const;
-optbl[0x49] = &bCPU::op_eor_const;
-optbl[0xa9] = &bCPU::op_lda_const;
-optbl[0xa2] = &bCPU::op_ldx_const;
-optbl[0xa0] = &bCPU::op_ldy_const;
-optbl[0x09] = &bCPU::op_ora_const;
-optbl[0xe9] = &bCPU::op_sbc_const;
-optbl[0x6d] = &bCPU::op_adc_addr;
-optbl[0x2d] = &bCPU::op_and_addr;
-optbl[0x2c] = &bCPU::op_bit_addr;
-optbl[0xcd] = &bCPU::op_cmp_addr;
-optbl[0xec] = &bCPU::op_cpx_addr;
-optbl[0xcc] = &bCPU::op_cpy_addr;
-optbl[0x4d] = &bCPU::op_eor_addr;
-optbl[0xad] = &bCPU::op_lda_addr;
-optbl[0xae] = &bCPU::op_ldx_addr;
-optbl[0xac] = &bCPU::op_ldy_addr;
-optbl[0x0d] = &bCPU::op_ora_addr;
-optbl[0xed] = &bCPU::op_sbc_addr;
-optbl[0x7d] = &bCPU::op_adc_addrx;
-optbl[0x3d] = &bCPU::op_and_addrx;
-optbl[0x3c] = &bCPU::op_bit_addrx;
-optbl[0xdd] = &bCPU::op_cmp_addrx;
-optbl[0x5d] = &bCPU::op_eor_addrx;
-optbl[0xbd] = &bCPU::op_lda_addrx;
-optbl[0xbc] = &bCPU::op_ldy_addrx;
-optbl[0x1d] = &bCPU::op_ora_addrx;
-optbl[0xfd] = &bCPU::op_sbc_addrx;
-optbl[0x79] = &bCPU::op_adc_addry;
-optbl[0x39] = &bCPU::op_and_addry;
-optbl[0xd9] = &bCPU::op_cmp_addry;
-optbl[0x59] = &bCPU::op_eor_addry;
-optbl[0xb9] = &bCPU::op_lda_addry;
-optbl[0xbe] = &bCPU::op_ldx_addry;
-optbl[0x19] = &bCPU::op_ora_addry;
-optbl[0xf9] = &bCPU::op_sbc_addry;
-optbl[0x6f] = &bCPU::op_adc_long;
-optbl[0x2f] = &bCPU::op_and_long;
-optbl[0xcf] = &bCPU::op_cmp_long;
-optbl[0x4f] = &bCPU::op_eor_long;
-optbl[0xaf] = &bCPU::op_lda_long;
-optbl[0x0f] = &bCPU::op_ora_long;
-optbl[0xef] = &bCPU::op_sbc_long;
-optbl[0x7f] = &bCPU::op_adc_longx;
-optbl[0x3f] = &bCPU::op_and_longx;
-optbl[0xdf] = &bCPU::op_cmp_longx;
-optbl[0x5f] = &bCPU::op_eor_longx;
-optbl[0xbf] = &bCPU::op_lda_longx;
-optbl[0x1f] = &bCPU::op_ora_longx;
-optbl[0xff] = &bCPU::op_sbc_longx;
-optbl[0x65] = &bCPU::op_adc_dp;
-optbl[0x25] = &bCPU::op_and_dp;
-optbl[0x24] = &bCPU::op_bit_dp;
-optbl[0xc5] = &bCPU::op_cmp_dp;
-optbl[0xe4] = &bCPU::op_cpx_dp;
-optbl[0xc4] = &bCPU::op_cpy_dp;
-optbl[0x45] = &bCPU::op_eor_dp;
-optbl[0xa5] = &bCPU::op_lda_dp;
-optbl[0xa6] = &bCPU::op_ldx_dp;
-optbl[0xa4] = &bCPU::op_ldy_dp;
-optbl[0x05] = &bCPU::op_ora_dp;
-optbl[0xe5] = &bCPU::op_sbc_dp;
-optbl[0x75] = &bCPU::op_adc_dpx;
-optbl[0x35] = &bCPU::op_and_dpx;
-optbl[0x34] = &bCPU::op_bit_dpx;
-optbl[0xd5] = &bCPU::op_cmp_dpx;
-optbl[0x55] = &bCPU::op_eor_dpx;
-optbl[0xb5] = &bCPU::op_lda_dpx;
-optbl[0xb4] = &bCPU::op_ldy_dpx;
-optbl[0x15] = &bCPU::op_ora_dpx;
-optbl[0xf5] = &bCPU::op_sbc_dpx;
-optbl[0xb6] = &bCPU::op_ldx_dpy;
-optbl[0x72] = &bCPU::op_adc_idp;
-optbl[0x32] = &bCPU::op_and_idp;
-optbl[0xd2] = &bCPU::op_cmp_idp;
-optbl[0x52] = &bCPU::op_eor_idp;
-optbl[0xb2] = &bCPU::op_lda_idp;
-optbl[0x12] = &bCPU::op_ora_idp;
-optbl[0xf2] = &bCPU::op_sbc_idp;
-optbl[0x61] = &bCPU::op_adc_idpx;
-optbl[0x21] = &bCPU::op_and_idpx;
-optbl[0xc1] = &bCPU::op_cmp_idpx;
-optbl[0x41] = &bCPU::op_eor_idpx;
-optbl[0xa1] = &bCPU::op_lda_idpx;
-optbl[0x01] = &bCPU::op_ora_idpx;
-optbl[0xe1] = &bCPU::op_sbc_idpx;
-optbl[0x71] = &bCPU::op_adc_idpy;
-optbl[0x31] = &bCPU::op_and_idpy;
-optbl[0xd1] = &bCPU::op_cmp_idpy;
-optbl[0x51] = &bCPU::op_eor_idpy;
-optbl[0xb1] = &bCPU::op_lda_idpy;
-optbl[0x11] = &bCPU::op_ora_idpy;
-optbl[0xf1] = &bCPU::op_sbc_idpy;
-optbl[0x67] = &bCPU::op_adc_ildp;
-optbl[0x27] = &bCPU::op_and_ildp;
-optbl[0xc7] = &bCPU::op_cmp_ildp;
-optbl[0x47] = &bCPU::op_eor_ildp;
-optbl[0xa7] = &bCPU::op_lda_ildp;
-optbl[0x07] = &bCPU::op_ora_ildp;
-optbl[0xe7] = &bCPU::op_sbc_ildp;
-optbl[0x77] = &bCPU::op_adc_ildpy;
-optbl[0x37] = &bCPU::op_and_ildpy;
-optbl[0xd7] = &bCPU::op_cmp_ildpy;
-optbl[0x57] = &bCPU::op_eor_ildpy;
-optbl[0xb7] = &bCPU::op_lda_ildpy;
-optbl[0x17] = &bCPU::op_ora_ildpy;
-optbl[0xf7] = &bCPU::op_sbc_ildpy;
-optbl[0x63] = &bCPU::op_adc_sr;
-optbl[0x23] = &bCPU::op_and_sr;
-optbl[0xc3] = &bCPU::op_cmp_sr;
-optbl[0x43] = &bCPU::op_eor_sr;
-optbl[0xa3] = &bCPU::op_lda_sr;
-optbl[0x03] = &bCPU::op_ora_sr;
-optbl[0xe3] = &bCPU::op_sbc_sr;
-optbl[0x73] = &bCPU::op_adc_isry;
-optbl[0x33] = &bCPU::op_and_isry;
-optbl[0xd3] = &bCPU::op_cmp_isry;
-optbl[0x53] = &bCPU::op_eor_isry;
-optbl[0xb3] = &bCPU::op_lda_isry;
-optbl[0x13] = &bCPU::op_ora_isry;
-optbl[0xf3] = &bCPU::op_sbc_isry;
-optbl[0x89] = &bCPU::op_bit_const;
-optbl[0x1a] = &bCPU::op_inc;
-optbl[0xe8] = &bCPU::op_inx;
-optbl[0xc8] = &bCPU::op_iny;
-optbl[0x3a] = &bCPU::op_dec;
-optbl[0xca] = &bCPU::op_dex;
-optbl[0x88] = &bCPU::op_dey;
-optbl[0x0a] = &bCPU::op_asl;
-optbl[0x4a] = &bCPU::op_lsr;
-optbl[0x2a] = &bCPU::op_rol;
-optbl[0x6a] = &bCPU::op_ror;
-optbl[0xee] = &bCPU::op_inc_addr;
-optbl[0xce] = &bCPU::op_dec_addr;
-optbl[0x0e] = &bCPU::op_asl_addr;
-optbl[0x4e] = &bCPU::op_lsr_addr;
-optbl[0x2e] = &bCPU::op_rol_addr;
-optbl[0x6e] = &bCPU::op_ror_addr;
-optbl[0x1c] = &bCPU::op_trb_addr;
-optbl[0x0c] = &bCPU::op_tsb_addr;
-optbl[0xfe] = &bCPU::op_inc_addrx;
-optbl[0xde] = &bCPU::op_dec_addrx;
-optbl[0x1e] = &bCPU::op_asl_addrx;
-optbl[0x5e] = &bCPU::op_lsr_addrx;
-optbl[0x3e] = &bCPU::op_rol_addrx;
-optbl[0x7e] = &bCPU::op_ror_addrx;
-optbl[0xe6] = &bCPU::op_inc_dp;
-optbl[0xc6] = &bCPU::op_dec_dp;
-optbl[0x06] = &bCPU::op_asl_dp;
-optbl[0x46] = &bCPU::op_lsr_dp;
-optbl[0x26] = &bCPU::op_rol_dp;
-optbl[0x66] = &bCPU::op_ror_dp;
-optbl[0x14] = &bCPU::op_trb_dp;
-optbl[0x04] = &bCPU::op_tsb_dp;
-optbl[0xf6] = &bCPU::op_inc_dpx;
-optbl[0xd6] = &bCPU::op_dec_dpx;
-optbl[0x16] = &bCPU::op_asl_dpx;
-optbl[0x56] = &bCPU::op_lsr_dpx;
-optbl[0x36] = &bCPU::op_rol_dpx;
-optbl[0x76] = &bCPU::op_ror_dpx;
-optbl[0x8d] = &bCPU::op_sta_addr;
-optbl[0x8e] = &bCPU::op_stx_addr;
-optbl[0x8c] = &bCPU::op_sty_addr;
-optbl[0x9c] = &bCPU::op_stz_addr;
-optbl[0x9d] = &bCPU::op_sta_addrx;
-optbl[0x9e] = &bCPU::op_stz_addrx;
-optbl[0x99] = &bCPU::op_sta_addry;
-optbl[0x8f] = &bCPU::op_sta_long;
-optbl[0x9f] = &bCPU::op_sta_longx;
-optbl[0x85] = &bCPU::op_sta_dp;
-optbl[0x86] = &bCPU::op_stx_dp;
-optbl[0x84] = &bCPU::op_sty_dp;
-optbl[0x64] = &bCPU::op_stz_dp;
-optbl[0x95] = &bCPU::op_sta_dpx;
-optbl[0x94] = &bCPU::op_sty_dpx;
-optbl[0x74] = &bCPU::op_stz_dpx;
-optbl[0x96] = &bCPU::op_stx_dpy;
-optbl[0x92] = &bCPU::op_sta_idp;
-optbl[0x87] = &bCPU::op_sta_ildp;
-optbl[0x81] = &bCPU::op_sta_idpx;
-optbl[0x91] = &bCPU::op_sta_idpy;
-optbl[0x97] = &bCPU::op_sta_ildpy;
-optbl[0x83] = &bCPU::op_sta_sr;
-optbl[0x93] = &bCPU::op_sta_isry;
-optbl[0x90] = &bCPU::op_bcc;
-optbl[0xb0] = &bCPU::op_bcs;
-optbl[0xd0] = &bCPU::op_bne;
-optbl[0xf0] = &bCPU::op_beq;
-optbl[0x10] = &bCPU::op_bpl;
-optbl[0x30] = &bCPU::op_bmi;
-optbl[0x50] = &bCPU::op_bvc;
-optbl[0x70] = &bCPU::op_bvs;
-optbl[0x80] = &bCPU::op_bra;
-optbl[0x82] = &bCPU::op_brl;
-optbl[0x4c] = &bCPU::op_jmp_addr;
-optbl[0x5c] = &bCPU::op_jmp_long;
-optbl[0x6c] = &bCPU::op_jmp_iaddr;
-optbl[0x7c] = &bCPU::op_jmp_iaddrx;
-optbl[0xdc] = &bCPU::op_jmp_iladdr;
-optbl[0x20] = &bCPU::op_jsr_addr;
-optbl[0x22] = &bCPU::op_jsr_long;
-optbl[0xfc] = &bCPU::op_jsr_iaddrx;
-optbl[0x40] = &bCPU::op_rti;
-optbl[0x60] = &bCPU::op_rts;
-optbl[0x6b] = &bCPU::op_rtl;
-optbl[0xea] = &bCPU::op_nop;
-optbl[0x42] = &bCPU::op_wdm;
-optbl[0xeb] = &bCPU::op_xba;
-optbl[0x54] = &bCPU::op_mvn;
-optbl[0x44] = &bCPU::op_mvp;
-optbl[0x00] = &bCPU::op_brk;
-optbl[0x02] = &bCPU::op_cop;
-optbl[0xdb] = &bCPU::op_stp;
-optbl[0xcb] = &bCPU::op_wai;
-optbl[0xfb] = &bCPU::op_xce;
-optbl[0x18] = &bCPU::op_clc;
-optbl[0xd8] = &bCPU::op_cld;
-optbl[0x58] = &bCPU::op_cli;
-optbl[0xb8] = &bCPU::op_clv;
-optbl[0x38] = &bCPU::op_sec;
-optbl[0xf8] = &bCPU::op_sed;
-optbl[0x78] = &bCPU::op_sei;
-optbl[0xc2] = &bCPU::op_rep;
-optbl[0xe2] = &bCPU::op_sep;
-optbl[0xaa] = &bCPU::op_tax;
-optbl[0xa8] = &bCPU::op_tay;
-optbl[0x8a] = &bCPU::op_txa;
-optbl[0x9b] = &bCPU::op_txy;
-optbl[0x98] = &bCPU::op_tya;
-optbl[0xbb] = &bCPU::op_tyx;
-optbl[0x5b] = &bCPU::op_tcd;
-optbl[0x1b] = &bCPU::op_tcs;
-optbl[0x7b] = &bCPU::op_tdc;
-optbl[0x3b] = &bCPU::op_tsc;
-optbl[0xba] = &bCPU::op_tsx;
-optbl[0x9a] = &bCPU::op_txs;
-optbl[0x48] = &bCPU::op_pha;
-optbl[0xda] = &bCPU::op_phx;
-optbl[0x5a] = &bCPU::op_phy;
-optbl[0x0b] = &bCPU::op_phd;
-optbl[0x8b] = &bCPU::op_phb;
-optbl[0x4b] = &bCPU::op_phk;
-optbl[0x08] = &bCPU::op_php;
-optbl[0x68] = &bCPU::op_pla;
-optbl[0xfa] = &bCPU::op_plx;
-optbl[0x7a] = &bCPU::op_ply;
-optbl[0x2b] = &bCPU::op_pld;
-optbl[0xab] = &bCPU::op_plb;
-optbl[0x28] = &bCPU::op_plp;
-optbl[0xf4] = &bCPU::op_pea;
-optbl[0xd4] = &bCPU::op_pei;
-optbl[0x62] = &bCPU::op_per;

src/cpu/bcpu/dma/dma.cpp

@@ -1,265 +0,0 @@
-/* used by both DMA and HDMA
- * prevents transfer across same bus (a->a or b->b)
- */
-void bCPU::dma_transfer_byte(bool direction, uint8 bbus, uint32 abus) {
-uint8 r;
-  if(direction == 0) {
-  //read from address bus a, write to address bus b
-
-  //DMA address bus a cannot read from or write to the following addresses:
-  //$[00-3f|80-bf]:21[00-ff] <address bus b>
-  //$[00-3f|80-bf]:43[00-7f] <DMA control registers>
-  //$[00-3f|80-bf]:420b      <DMA enable register>
-  //$[00-3f|80-bf]:420c      <HDMA enable register>
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c) {
-    //these invalid reads will return open bus
-      r = r_cpu->regs.mdr;
-    } else {
-      r = r_mem->read(abus);
-    }
-
-    r_mem->write(0x2100 | bbus, r);
-  } else {
-  //read from address bus b, write to address bus a
-
-  //block invalid writes, see comments above
-    r = (bbus == 0x80) ? r_cpu->regs.mdr : r_mem->read(0x2100 | bbus);
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c)return;
-    r_mem->write(abus, r);
-  }
-}
-
-void bCPU::dma_add_cycles(uint32 cycles) {
-  status.dma_cycle_count += cycles;
-}
-
-void bCPU::hdma_add_cycles(uint32 cycles) {
-  if(run_state.dma) {
-    status.dma_cycle_count += cycles;
-  }
-  status.hdma_cycle_count += cycles;
-}
-
-uint32 bCPU::dma_addr(uint8 i) {
-uint32 r;
-  r = (channel[i].srcbank << 16) | (channel[i].srcaddr);
-
-  if(channel[i].fixedxfer == false) {
-    channel[i].srcaddr += channel[i].incmode;
-  }
-
-  return r;
-}
-
-void bCPU::dma_cputommio(uint8 i, uint8 index) {
-  if(sdd1->dma_active() == true) {
-    r_mem->write(0x2100 | ((channel[i].destaddr + index) & 0xff), sdd1->dma_read());
-  } else {
-    dma_transfer_byte(0, ((channel[i].destaddr + index) & 0xff), dma_addr(i));
-  }
-
-  add_cycles(8);
-  channel[i].xfersize--;
-}
-
-void bCPU::dma_mmiotocpu(uint8 i, uint8 index) {
-  dma_transfer_byte(1, ((channel[i].destaddr + index) & 0xff), dma_addr(i));
-
-  add_cycles(8);
-  channel[i].xfersize--;
-}
-
-void bCPU::dma_write(uint8 i, uint8 index) {
-  if(channel[i].direction == 0) {
-    dma_cputommio(i, index);
-  } else {
-    dma_mmiotocpu(i, index);
-  }
-}
-
-void bCPU::dma_run() {
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].active == false)continue;
-
-  //first byte transferred?
-    if(channel[i].read_index == 0) {
-      sdd1->dma_begin(i, (channel[i].srcbank << 16) | (channel[i].srcaddr),
-        channel[i].xfersize);
-    }
-
-    switch(channel[i].xfermode) {
-    case 0: dma_write(i, 0);                                break; //0
-    case 1: dma_write(i, channel[i].read_index & 1);        break; //0,1
-    case 2: dma_write(i, 0);                                break; //0,0
-    case 3: dma_write(i, (channel[i].read_index >> 1) & 1); break; //0,0,1,1
-    case 4: dma_write(i, channel[i].read_index & 3);        break; //0,1,2,3
-    case 5: dma_write(i, channel[i].read_index & 1);        break; //0,1,0,1
-    case 6: dma_write(i, 0);                                break; //0,0     [2]
-    case 7: dma_write(i, (channel[i].read_index >> 1) & 1); break; //0,0,1,1 [3]
-    }
-
-    channel[i].read_index++;
-    dma_add_cycles(8);
-
-    if(channel[i].xfersize == 0) {
-      channel[i].active = false;
-    }
-
-    return;
-  }
-
-  status.dma_state = DMASTATE_CPUSYNC;
-}
-
-uint32 bCPU::hdma_addr(uint8 i) {
-  return (channel[i].srcbank << 16) | (channel[i].hdma_addr++);
-}
-
-uint32 bCPU::hdma_iaddr(uint8 i) {
-  return (channel[i].hdma_ibank << 16) | (channel[i].hdma_iaddr++);
-}
-
-uint16 bCPU::hdma_mmio(uint8 i) {
-uint8  l = channel[i].read_index;
-uint16 index;
-  switch(channel[i].xfermode) {
-  case 0: index = 0;            break; //0
-  case 1: index = l & 1;        break; //0,1
-  case 2: index = 0;            break; //0,0
-  case 3: index = (l >> 1) & 1; break; //0,0,1,1
-  case 4: index = l & 3;        break; //0,1,2,3
-  case 5: index = l & 1;        break; //0,1,0,1
-  case 6: index = 0;            break; //0,0     [2]
-  case 7: index = (l >> 1) & 1; break; //0,0,1,1 [3]
-  }
-
-  return (0x2100 | ((channel[i].destaddr + index) & 0xff));
-}
-
-void bCPU::hdma_update(uint8 i) {
-  channel[i].hdma_line_counter = r_mem->read(hdma_addr(i));
-  add_cycles(8);
-  hdma_add_cycles(8);
-
-  if(channel[i].hdma_indirect) {
-    channel[i].hdma_iaddr = r_mem->read(hdma_addr(i)) << 8;
-    add_cycles(8);
-    hdma_add_cycles(8);
-  }
-
-  if(channel[i].hdma_line_counter == 0) {
-    channel[i].hdma_active      = false;
-    channel[i].hdma_do_transfer = false;
-    return;
-  }
-
-  channel[i].hdma_do_transfer = true;
-
-  if(channel[i].hdma_indirect) {
-    channel[i].hdma_iaddr >>= 8;
-    channel[i].hdma_iaddr  |= r_mem->read(hdma_addr(i)) << 8;
-    add_cycles(8);
-    hdma_add_cycles(8);
-  }
-}
-
-void bCPU::hdma_run() {
-static uint8 hdma_xferlen[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
-  for(int i = 0; i < 8; i++) {
-    if(!channel[i].hdma_enabled || !channel[i].hdma_active)continue;
-
-    if(channel[i].hdma_do_transfer) {
-    int xferlen = hdma_xferlen[channel[i].xfermode];
-      for(channel[i].read_index = 0; channel[i].read_index < xferlen; channel[i].read_index++) {
-        if(bool(config::cpu.hdma_enable) == true) {
-          dma_transfer_byte(channel[i].direction, hdma_mmio(i),
-            channel[i].hdma_indirect ? hdma_iaddr(i) : hdma_addr(i));
-        }
-        add_cycles(8);
-        hdma_add_cycles(8);
-      }
-    }
-
-    channel[i].hdma_line_counter--;
-    channel[i].hdma_do_transfer = bool(channel[i].hdma_line_counter & 0x80);
-    if((channel[i].hdma_line_counter & 0x7f) == 0) {
-      hdma_update(i);
-    }
-  }
-}
-
-uint8 bCPU::hdma_enabled_channels() {
-int r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].hdma_enabled)r++;
-  }
-  return r;
-}
-
-uint8 bCPU::hdma_active_channels() {
-int r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].hdma_enabled && channel[i].hdma_active)r++;
-  }
-  return r;
-}
-
-/* hdmainit_activate()
- * hdma_activate()
- *
- * Functions are called by CPU timing routine
- * when an HDMA event (init or run) occurs.
- */
-
-void bCPU::hdmainit_activate() {
-  for(int i = 0; i < 8; i++) {
-    channel[i].hdma_active      = false;
-    channel[i].hdma_do_transfer = false;
-  }
-
-  if(hdma_enabled_channels() != 0) {
-    status.hdma_state = HDMASTATE_IDMASYNC;
-    run_state.hdma = true;
-  }
-}
-
-void bCPU::hdma_activate() {
-  if(hdma_active_channels() != 0) {
-    status.hdma_state = HDMASTATE_DMASYNC;
-    run_state.hdma = true;
-  }
-}
-
-void bCPU::dma_reset() {
-  status.dma_state        = DMASTATE_CPUSYNC;
-  status.hdma_state       = HDMASTATE_CPUSYNC;
-  status.dma_cycle_count  = 0;
-  status.hdma_cycle_count = 0;
-
-  for(int i = 0; i < 8; i++) {
-    channel[i].read_index        = 0;
-    channel[i].active            = false;
-    channel[i].hdma_enabled      = false;
-    channel[i].dmap              = 0xff;
-    channel[i].direction         = 1;
-    channel[i].hdma_indirect     = 1;
-    channel[i].incmode           = -1;
-    channel[i].fixedxfer         = 1;
-    channel[i].xfermode          = 7;
-    channel[i].destaddr          = 0xff;
-    channel[i].srcaddr           = 0xffff;
-    channel[i].srcbank           = 0xff;
-    channel[i].xfersize          = 0xffff;
-  //xfersize and hdma_iaddr are of union { uint16 };
-  //channel[i].hdma_iaddr        = 0xffff;
-    channel[i].hdma_ibank        = 0xff;
-    channel[i].hdma_addr         = 0xffff;
-    channel[i].hdma_line_counter = 0xff;
-    channel[i].hdma_unknown      = 0xff;
-
-    channel[i].hdma_active       = false;
-    channel[i].hdma_do_transfer  = false;
-  }
-}

src/cpu/bcpu/dma/dma.h

@@ -1,60 +0,0 @@
-struct {
-  uint32 read_index; //set to 0 at beginning of DMA/HDMA
-
-//$420b
-  bool   active;
-//$420c
-  bool   hdma_enabled;
-//$43x0
-  uint8  dmap;
-  bool   direction;
-  bool   hdma_indirect;
-  int8   incmode;
-  bool   fixedxfer;
-  uint8  xfermode;
-//$43x1
-  uint8  destaddr;
-//$43x2-$43x3
-  uint16 srcaddr;
-//$43x4
-  uint8  srcbank;
-//$43x5-$43x6
-  union {
-    uint16 xfersize;
-    uint16 hdma_iaddr;
-  };
-//$43x7
-  uint8  hdma_ibank;
-//$43x8-$43x9
-  uint16 hdma_addr;
-//$43xa
-  uint8  hdma_line_counter;
-//$43xb/$43xf
-  uint8  hdma_unknown;
-
-//hdma-specific
-  bool   hdma_active;
-  bool   hdma_do_transfer;
-
-  uint8  hdma_current_channel;
-  uint8  hdma_current_pos;
-} channel[8];
-
-  inline void   dma_transfer_byte(bool direction, uint8 bbus, uint32 abus);
-  inline void   dma_add_cycles(uint32 cycles);
-  inline void   hdma_add_cycles(uint32 cycles);
-  inline void   dma_run();
-  inline void   hdma_run();
-  inline void   hdma_update(uint8 i);
-  inline uint8  hdma_enabled_channels();
-  inline uint8  hdma_active_channels();
-  inline void   hdmainit_activate();
-  inline void   hdma_activate();
-  inline void   dma_cputommio(uint8 i, uint8 index);
-  inline void   dma_mmiotocpu(uint8 i, uint8 index);
-  inline void   dma_write(uint8 i, uint8 index);
-  inline uint32 dma_addr(uint8 i);
-  inline uint32 hdma_addr(uint8 i);
-  inline uint32 hdma_iaddr(uint8 i);
-  inline uint16 hdma_mmio(uint8 i);
-  inline void   dma_reset();

src/cpu/bcpu/memory/memory.cpp

@@ -1,40 +0,0 @@
-uint8 bCPU::port_read(uint8 port) {
-  return apu_port[port & 3];
-}
-
-void bCPU::port_write(uint8 port, uint8 value) {
-  apu_port[port & 3] = value;
-}
-
-/* The next 3 functions control bus timing for the CPU.
- * cpu_io is an I/O cycle, and always 6 clock cycles long.
- * mem_read / mem_write indicate memory access bus cycle,
- * they are either 6, 8, or 12 bus cycles long, depending
- * both on location and the $420d.d0 FastROM enable bit.
- */
-
-void bCPU::cpu_io() {
-  status.cycle_count = 6;
-  pre_exec_cycle();
-  add_cycles(6);
-  cycle_edge();
-}
-
-uint8 bCPU::mem_read(uint32 addr) {
-  status.cycle_count = r_mem->speed(addr);
-  pre_exec_cycle();
-  add_cycles(status.cycle_count - 4);
-  regs.mdr = r_mem->read(addr);
-  add_cycles(4);
-  cycle_edge();
-  return regs.mdr;
-}
-
-void bCPU::mem_write(uint32 addr, uint8 value) {
-  status.cycle_count = r_mem->speed(addr);
-  pre_exec_cycle();
-  add_cycles(status.cycle_count);
-  regs.mdr = value;
-  r_mem->write(addr, value);
-  cycle_edge();
-}

src/cpu/bcpu/memory/memory.h

@@ -1,7 +0,0 @@
-uint8 apu_port[4];
-  inline uint8  port_read (uint8 port);
-  inline void   port_write(uint8 port, uint8 value);
-
-  inline void   cpu_io();
-  inline uint8  mem_read(uint32 addr);
-  inline void   mem_write(uint32 addr, uint8 value);

src/cpu/bcpu/timing/timing.cpp

@@ -1,358 +0,0 @@
-/* Notes about PAL timing:
- * As I do not have PAL hardware to run timing tests on, I've
- * had to guess on a lot of things. Below is how I've arrived
- * at various calculations:
- *
- * NTSC timing crystal: ~21477272hz
- * PAL  timing crystal: ~21281370hz
- * NTSC ~60fps, PAL ~50fps
- * NTSC ~262 lines/frame, PAL ~312 lines/frame
- * NTSC 21477272 / (262 * 60) = ~1366 cycles/line
- * PAL  21281370 / (312 * 50) = ~1364 cycles/line
- *
- * As the cycles/line are very close between the two systems,
- * I have left the known NTSC anomalies intact for PAL timing.
- * In reality, some of these may not exist, and some may be
- * slightly different.
- *
- * [known]
- * - DRAM refresh occurs at about the same time every
- * scanline on PAL units (per Overload).
- * [unknown]
- * - Are dots 323/327 still 2 cycles longer than the
- * other dots?
- * - Is scanline 240 on non-interlace odd frames still
- * 4 cycles short?
- */
-
-uint16 bCPU::vcounter() { return time.v; }
-uint16 bCPU::hcounter() { return get_hcounter(); }
-uint16 bCPU::hcycles()  { return time.hc; }
-
-bool   bCPU::interlace()        { return time.interlace; }
-bool   bCPU::interlace_field()  { return time.interlace_field; }
-bool   bCPU::overscan()         { return time.overscan; }
-uint16 bCPU::region_scanlines() { return time.region_scanlines; }
-
-void   bCPU::set_interlace(bool r) { time.interlace = r; update_interrupts(); }
-void   bCPU::set_overscan (bool r) { time.overscan  = r; update_interrupts(); }
-
-uint8  bCPU::dma_counter() { return (time.dma_counter + time.hc) & 6; }
-
-bool bCPU::nmi_trigger_pos_match(uint32 offset) {
-uint16 v  = overscan() ? 240 : 225;
-uint16 hc = 2 + offset;
-  return (time.v == v && time.hc == hc);
-}
-
-bool bCPU::irq_trigger_pos_match(uint32 offset) {
-uint16 v  = status.virq_pos;
-uint16 hc = (status.hirq_enabled) ? status.hirq_pos : 0;
-
-//positions that can never be latched
-//region_scanlines() = 262/NTSC, 312/PAL
-//PAL results are unverified on hardware
-  if(v == 240 && hc == 339 && interlace() == false && interlace_field() == 1)return false;
-  if(v == (region_scanlines() - 1) && hc == 339 && interlace() == false)return false;
-  if(v == region_scanlines() && interlace() == false)return false;
-  if(v == region_scanlines() && hc == 339)return false;
-  if(v  > region_scanlines())return false;
-  if(hc > 339)return false;
-
-  hc  = (hc != 0) ? ((hc << 2) + 14) : 10;
-  hc += offset;
-  if(hc >= time.line_cycles) {
-    hc -= time.line_cycles;
-    if(++v >= time.frame_lines) {
-      v = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == v) || status.virq_enabled == false) {
-    return (time.hc == hc);
-  }
-
-  return false;
-}
-
-void bCPU::update_nmi() {
-  if(time.v == (overscan() ? 240 : 225)) {
-    time.nmi_read_trigger_pos = 2;
-    time.nmi_line_trigger_pos = 6;
-  } else {
-    time.nmi_read_trigger_pos = -64;
-    time.nmi_line_trigger_pos = -64;
-  }
-}
-
-void bCPU::update_irq() {
-int vpos = status.virq_pos;
-int hpos = (status.hirq_enabled) ? status.hirq_pos : 0;
-
-//positions that can never be latched
-//region_scanlines() = 262/NTSC, 312/PAL
-//PAL results are unverified on hardware
-  if(vpos == 240 && hpos == 339 && interlace() == false && interlace_field() == 1)goto _nolatch;
-  if(vpos == (region_scanlines() - 1) && hpos == 339 && interlace() == false)goto _nolatch;
-  if(vpos == region_scanlines() && interlace() == false)goto _nolatch;
-  if(vpos == region_scanlines() && hpos == 339)goto _nolatch;
-  if(vpos  > region_scanlines())goto _nolatch;
-  if(hpos  > 339)goto _nolatch;
-
-  hpos = (hpos != 0) ? ((hpos << 2) + 14) : 10;
-  if(hpos >= time.line_cycles) {
-    hpos -= time.line_cycles;
-    if(++vpos >= time.frame_lines) {
-      vpos = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == vpos) || status.virq_enabled == false) {
-    time.irq_read_trigger_pos = hpos;
-  } else {
-    time.irq_read_trigger_pos = -64;
-  }
-
-  hpos += 4;
-  if(hpos >= time.line_cycles) {
-    hpos -= time.line_cycles;
-    if(++vpos >= time.frame_lines) {
-      vpos = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == vpos) || status.virq_enabled == false) {
-    time.irq_line_trigger_pos = hpos;
-  } else {
-    time.irq_line_trigger_pos = -64;
-  }
-
-  return;
-
-_nolatch:
-  time.irq_read_trigger_pos = -64;
-  time.irq_line_trigger_pos = -64;
-}
-
-void bCPU::update_interrupts() {
-  update_nmi();
-  update_irq();
-}
-
-void bCPU::poll_interrupts(int cycles) {
-int16 hc, hc_end;
-  if(time.hc == 0) {
-    hc     = -1;
-    hc_end = cycles;
-  } else {
-    hc     = time.hc;
-    hc_end = time.hc + cycles;
-  }
-
-  if(hc < time.nmi_read_trigger_pos && time.nmi_read_trigger_pos <= hc_end) {
-  //nmi_read can go low even with NMI interrupts disabled in $4200.d7
-    time.nmi_read = 0;
-  }
-
-  if(hc < time.nmi_line_trigger_pos && time.nmi_line_trigger_pos <= hc_end) {
-    if(status.nmi_enabled == true) {
-      if(time.nmi_line == 1) {
-        time.nmi_transition = 1;
-      }
-      time.nmi_line = 0;
-    }
-  }
-
-  if(hc < time.irq_read_trigger_pos && time.irq_read_trigger_pos <= hc_end) {
-    if(status.virq_enabled == true || status.hirq_enabled == true) {
-      time.irq_read = 0;
-    }
-  }
-
-  if(hc < time.irq_line_trigger_pos && time.irq_line_trigger_pos <= hc_end) {
-    if(status.virq_enabled == true || status.hirq_enabled == true) {
-      time.irq_line = 0;
-      time.irq_transition = 1;
-    }
-  }
-}
-
-//all scanlines are 1364 cycles long, except scanline 240
-//on non-interlace odd-frames, which is 1360 cycles long.
-//[NTSC]
-//interlace mode has 525 scanlines: 263 on the even frame,
-//and 262 on the odd.
-//non-interlace mode has 524 scanlines: 262 scanlines on
-//both even and odd frames.
-//[PAL] <PAL info is unverified on hardware>
-//interlace mode has 625 scanlines: 313 on the even frame,
-//and 312 on the odd.
-//non-interlace mode has 624 scanlines: 312 scanlines on
-//both even and odd frames.
-//
-//cycles per frame:
-//  263 * 1364     = 358732
-//  262 * 1364     = 357368
-//  262 * 1364 - 4 = 357364
-void bCPU::inc_vcounter() {
-  time.v++;
-  if(time.v >= time.frame_lines) {
-    time.v = 0;
-    time.interlace_field ^= 1;
-
-    if(interlace() == true && interlace_field() == 0) {
-      time.frame_lines = time.region_scanlines + 1;
-    } else {
-      time.frame_lines = time.region_scanlines;
-    }
-  }
-
-  time.dma_counter += time.line_cycles;
-  if(time.v == 240 && time.interlace == false && time.interlace_field == 1) {
-    time.line_cycles = 1360;
-  } else {
-    time.line_cycles = 1364;
-  }
-  time.dram_refreshed = false;
-
-  update_interrupts();
-}
-
-//all dots are 4 cycles long, except dots 323 and 327. dots 323 and 327
-//are 6 cycles long. this holds true for all scanlines except scanline
-//240 on non-interlace odd frames. the reason for this is because this
-//scanline is only 1360 cycles long, instead of 1364 like all other
-//scanlines.
-//this makes the effective range of hscan_pos 0-339 at all times.
-//dot 323 range = { 1292, 1294, 1296 }
-//dot 327 range = { 1310, 1312, 1314 }
-uint16 bCPU::get_hcounter() {
-  if(time.v == 240 && time.interlace == false && time.interlace_field == 1) {
-    return time.hc >> 2;
-  }
-  return (time.hc - ((time.hc > 1292) << 1) - ((time.hc > 1310) << 1)) >> 2;
-}
-
-uint32 bCPU::cycles_executed() {
-uint32 r = status.cycles_executed;
-  status.cycles_executed = 0;
-  return r;
-}
-
-void bCPU::cycle_edge() {
-  if(time.hdmainit_triggered == false) {
-    if(time.hc >= time.hdmainit_trigger_pos || time.v) {
-      time.hdmainit_triggered = true;
-      hdmainit_activate();
-    }
-  }
-
-  if(time.hdma_triggered == false) {
-    if(time.v <= (overscan() ? 239 : 224)) {
-      if(time.hc >= 1106) {
-        time.hdma_triggered = true;
-        hdma_activate();
-      }
-    }
-  }
-}
-
-void bCPU::add_cycles(int cycles) {
-  status.cycles_executed += cycles;
-
-  poll_interrupts(cycles);
-
-  if(time.hc + cycles >= time.line_cycles) {
-    cycles  = (time.hc + cycles) - time.line_cycles;
-    time.hc = 0;
-
-    inc_vcounter();
-    poll_interrupts(cycles);
-
-    if(time.v == 0) {
-      frame();
-      r_ppu->frame();
-      snes->frame();
-    }
-
-    scanline();
-    r_ppu->scanline();
-    snes->scanline();
-    time.line_rendered = false;
-  }
-
-  if(time.dram_refreshed == false) {
-    if(time.hc + cycles >= time.dram_refresh_pos) {
-      time.dram_refreshed = true;
-      status.cycles_executed += 40;
-      cycles  = (time.hc + cycles) - time.dram_refresh_pos;
-      time.hc = time.dram_refresh_pos + 40;
-
-      if(cpu_version == 2) {
-        if(time.v != 240 || time.interlace != false || time.interlace_field != 1) {
-          if(time.dram_refresh_pos == 534) {
-            time.dram_refresh_pos = 538;
-          } else {
-            time.dram_refresh_pos = 534;
-          }
-        }
-      }
-    }
-  }
-
-  if(time.line_rendered == false) {
-  //rendering should start at H=18 (+256=274), but since the
-  //current PPU emulation renders the entire scanline at once,
-  //PPU register changes mid-scanline do not show up.
-  //therefore, wait a few dots before rendering the scanline
-    if(time.hc + cycles >= (48 * 4)) {
-      time.line_rendered = true;
-      r_ppu->render_scanline();
-    }
-  }
-
-  time.hc += cycles;
-}
-
-void bCPU::time_reset() {
-  time.v  = 0;
-  time.hc = 0;
-
-//upon SNES reset, start at scanline 0 non-interlace
-  time.interlace       = 0;
-  time.interlace_field = 0;
-  time.overscan        = false;
-  time.line_cycles     = 1364;
-
-  time.dram_refreshed   = false;
-  time.dram_refresh_pos = (cpu_version == 2) ? 538 : 530;
-
-  time.dma_counter = 0;
-
-//set at V=0,H=0
-  time.hdmainit_trigger_pos = 0;
-  time.hdmainit_triggered   = true;
-
-  time.hdma_triggered = false;
-
-  time.nmi_pending = false;
-  time.irq_pending = false;
-  time.nmi_line = time.nmi_read = 1;
-  time.irq_line = time.irq_read = 1;
-
-  time.nmi_transition = 0;
-  time.irq_transition = 0;
-
-  update_interrupts();
-
-  switch(region) {
-  case NTSC:
-    time.region_scanlines = 262;
-    break;
-  case PAL:
-    time.region_scanlines = 312;
-    break;
-  }
-
-  time.frame_lines = time.region_scanlines;
-}

src/cpu/bcpu/timing/timing.h

@@ -1,74 +0,0 @@
-struct {
-  uint16 v, hc;
-
-  bool   interlace, interlace_field, overscan;
-  uint16 line_cycles, frame_lines;
-
-  bool   line_rendered;
-
-  bool   dram_refreshed;
-  uint16 dram_refresh_pos;
-
-  uint8  dma_counter;
-
-  uint16 hdmainit_trigger_pos;
-  bool   hdmainit_triggered;
-
-  bool   hdma_triggered;
-
-  uint16 region_scanlines;
-
-//nmi_pending, irq_pending are used by last_cycle()
-//nmi_line = /NMI, nmi_read = $4210.7
-//irq_line = /IRQ, irq_read = $4211.7
-  bool   nmi_pending, nmi_line, nmi_read;
-  bool   irq_pending, irq_line, irq_read;
-
-//NMI is edge-sensitive, meaning it triggers when /NMI
-//transitions from high to low. This value is set to 1
-//when that happens, and cleared after the nmi_test()
-//routine acknowledges it and invokes the NMI interrupt
-  bool   nmi_transition;
-
-//IRQ is level-sensitive, so it does not need to keep
-//track of transitions from high to low. IRQs will
-//continue to fire as long as /IRQ stays low.
-//However, if a write to $4200 forces IRQs high at the
-//exact same clock cycle that /IRQ goes low, the /IRQ
-//will still occur. Hence the need for this variable.
-  bool   irq_transition;
-
-//position is relative to time.hc, set at start of each scanline
-//-64 means no trigger point on this scanline
-//$4210/$4211 status bits get set before /NMI and /IRQ go low,
-//hence the need for two variables for each.
-  int32  nmi_read_trigger_pos, nmi_line_trigger_pos;
-  int32  irq_read_trigger_pos, irq_line_trigger_pos;
-} time;
-
-  inline uint16 vcounter();
-  inline uint16 hcounter();
-  inline uint16 hcycles();
-  inline bool   interlace();
-  inline bool   interlace_field();
-  inline bool   overscan();
-  inline uint16 region_scanlines();
-
-  inline bool   nmi_trigger_pos_match(uint32 offset);
-  inline bool   irq_trigger_pos_match(uint32 offset);
-
-  inline void   update_nmi();
-  inline void   update_irq();
-  inline void   update_interrupts();
-  inline void   poll_interrupts(int cycles);
-
-  inline void   set_interlace(bool r);
-  inline void   set_overscan (bool r);
-
-  inline uint8  dma_counter();
-
-  inline void   inc_vcounter();
-  inline uint16 get_hcounter();
-  inline void   cycle_edge();
-  inline void   add_cycles(int cycles);
-  inline void   time_reset();

src/cpu/cpu.cpp

@@ -4,3 +4,6 @@
 CPU::CPU() {
   cpu_version = 1;
 }
+
+CPU::~CPU() {
+}

src/cpu/cpu.h

@@ -1,6 +1,9 @@
 #include "cpuregs.h"
 
 class CPU : public MMIO {
+public:
+  virtual void enter() = 0;
+
 public:
 //CPU version number
 //* 1 and 2 are known
@@ -11,10 +14,10 @@ uint8 cpu_version;
 //timing
   virtual uint16 vcounter() = 0;
   virtual uint16 hcounter() = 0;
-  virtual uint16 hcycles() = 0;
-  virtual bool   overscan() = 0;
+  virtual uint16 hclock() = 0;
   virtual bool   interlace() = 0;
   virtual bool   interlace_field() = 0;
+  virtual bool   overscan() = 0;
   virtual uint16 region_scanlines() = 0;
   virtual void   set_interlace(bool r) = 0;
   virtual void   set_overscan (bool r) = 0;
@@ -30,14 +33,29 @@ CPURegs regs;
     FLAG_Z = 0x02, FLAG_C = 0x01
   };
   virtual uint8  pio_status() = 0;
-  virtual void   run() = 0;
-  virtual uint32 cycles_executed() = 0;
   virtual void   scanline() = 0;
   virtual void   frame() = 0;
   virtual void   power() = 0;
   virtual void   reset() = 0;
 
-//opcode disassembler
+/*****
+ * in opcode-based CPU emulators, the main emulation routine
+ * will only be able to call the disassemble_opcode() function
+ * on clean opcode edges. but with cycle-based CPU emulators,
+ * the CPU may be in the middle of executing an opcode when the
+ * emulator (e.g. debugger) wants to disassemble an opcode. this
+ * would mean that important registers may not reflect what they
+ * did at the start of the opcode (especially regs.pc), so in
+ * cycle-based emulators, this function should be overridden to
+ * reflect whether or not an opcode has only been partially
+ * executed. if not, the debugger should abort attempts to skip,
+ * disable, or disassemble the current opcode.
+ *****/
+  virtual bool in_opcode() { return false; }
+
+/*****
+ * opcode disassembler
+ *****/
 enum {
   OPTYPE_DP = 0,    //dp
   OPTYPE_DPX,       //dp,x
@@ -57,17 +75,18 @@ enum {
   OPTYPE_SR,        //sr,s
   OPTYPE_ISRY,      //(sr,s),y
   OPTYPE_ADDR_PC,   //pbr:addr
-  OPTYPE_IADDR_PC   //pbr:(addr)
+  OPTYPE_IADDR_PC,  //pbr:(addr)
+  OPTYPE_RELB,      //relb
+  OPTYPE_RELW,      //relw
 };
-//see dcpu.cpp for notes on this function
-  virtual bool in_opcode();
 
   void   disassemble_opcode(char *output);
-  uint32 resolve_offset(uint8 offset_type, uint32 addr);
+  uint8  dreadb(uint32 addr);
+  uint16 dreadw(uint32 addr);
+  uint32 dreadl(uint32 addr);
+  uint32 decode(uint8 offset_type, uint32 addr);
   uint8  opcode_length();
-  uint16 __relb(int8 offset);
-  uint16 __relw(int16 offset);
 
   CPU();
-  virtual ~CPU() {}
+  virtual ~CPU();
 };

src/cpu/cpuregs.h

@@ -1,88 +1,66 @@
 class CPURegFlags {
-private:
-  template <uint8 B> class bit {
-  public:
-  uint8 _b;
-    inline operator bool() { return (_b & B); }
-    inline bool operator =  (bool i) { (i) ? _b |= B : _b &= ~B; return (_b & B); }
-    inline bool operator &  (bool i) { if(i)_b &= ~B; return (_b & B); }
-    inline bool operator &= (bool i) { if(i)_b &= ~B; return (_b & B); }
-    inline bool operator |  (bool i) { if(i)_b |= B; return (_b & B); }
-    inline bool operator |= (bool i) { if(i)_b |= B; return (_b & B); }
-    inline bool operator ^  (bool i) { if(i)_b ^= B; return (_b & B); }
-    inline bool operator ^= (bool i) { if(i)_b ^= B; return (_b & B); }
-  };
 public:
 union {
-  uint8 _b;
-  bit<0x80> n;
-  bit<0x40> v;
-  bit<0x20> m, p;
-  bit<0x10> x, b;
-  bit<0x08> d;
-  bit<0x04> i;
-  bit<0x02> z;
-  bit<0x01> c;
+  uint8 data;
+  struct {
+    bool order_msb8(n:1, v:1, m:1, x:1, d:1, i:1, z:1, c:1);
+  };
 };
 
-  CPURegFlags() { _b = 0; }
-  inline operator uint8() { return _b; }
-  inline unsigned operator  = (uint8 i) { _b  = i; return _b; }
-  inline unsigned operator &= (uint8 i) { _b &= i; return _b; }
-  inline unsigned operator |= (uint8 i) { _b |= i; return _b; }
-  inline unsigned operator ^= (uint8 i) { _b ^= i; return _b; }
+  inline operator unsigned() const { return data; }
+  template<typename T> inline unsigned operator  = (const T i) { data  = i; return data; }
+  template<typename T> inline unsigned operator |= (const T i) { data |= i; return data; }
+  template<typename T> inline unsigned operator ^= (const T i) { data ^= i; return data; }
+  template<typename T> inline unsigned operator &= (const T i) { data &= i; return data; }
+
+  CPURegFlags() : data(0) {}
 };
 
 class CPUReg16 {
 public:
 union {
   uint16 w;
-#ifdef ARCH_LSB
-  struct { uint8 l, h; };
-#else
-  struct { uint8 h, l; };
-#endif
+  struct { uint8 order_lsb2(l, h); };
 };
 
-  CPUReg16() { w = 0; }
-  inline operator uint16() { return w; }
-  inline unsigned operator   = (uint16 i) { w   = i; return w; }
-  inline unsigned operator  += (uint16 i) { w  += i; return w; }
-  inline unsigned operator  -= (uint16 i) { w  -= i; return w; }
-  inline unsigned operator  *= (uint16 i) { w  *= i; return w; }
-  inline unsigned operator  /= (uint16 i) { w  /= i; return w; }
-  inline unsigned operator  &= (uint16 i) { w  &= i; return w; }
-  inline unsigned operator  |= (uint16 i) { w  |= i; return w; }
-  inline unsigned operator  ^= (uint16 i) { w  ^= i; return w; }
-  inline unsigned operator <<= (uint16 i) { w <<= i; return w; }
-  inline unsigned operator >>= (uint16 i) { w >>= i; return w; }
+  inline operator unsigned() const { return w; }
+  template<typename T> inline unsigned operator   = (const T i) { w   = i; return w; }
+  template<typename T> inline unsigned operator  |= (const T i) { w  |= i; return w; }
+  template<typename T> inline unsigned operator  ^= (const T i) { w  ^= i; return w; }
+  template<typename T> inline unsigned operator  &= (const T i) { w  &= i; return w; }
+  template<typename T> inline unsigned operator <<= (const T i) { w <<= i; return w; }
+  template<typename T> inline unsigned operator >>= (const T i) { w >>= i; return w; }
+  template<typename T> inline unsigned operator  += (const T i) { w  += i; return w; }
+  template<typename T> inline unsigned operator  -= (const T i) { w  -= i; return w; }
+  template<typename T> inline unsigned operator  *= (const T i) { w  *= i; return w; }
+  template<typename T> inline unsigned operator  /= (const T i) { w  /= i; return w; }
+  template<typename T> inline unsigned operator  %= (const T i) { w  %= i; return w; }
+
+  CPUReg16() : w(0) {}
 };
 
 class CPUReg24 {
 public:
 union {
   uint32 d;
-#ifdef ARCH_LSB
-  struct { uint16 w, null_w; };
-  struct { uint8  l, h, b, null_b; };
-#else
-  struct { uint16 null_w, w; };
-  struct { uint8  null_b, b, h, l; };
-#endif
+  struct { uint16 order_lsb2(w, wh); };
+  struct { uint8  order_lsb4(l, h, b, bh); };
 };
 
-  CPUReg24() { d = 0; }
-  inline operator uint32() { return (d & 0xffffff); }
-  inline unsigned operator   = (uint16 i) { d   = i; return d; }
-  inline unsigned operator  += (uint16 i) { d  += i; return d; }
-  inline unsigned operator  -= (uint16 i) { d  -= i; return d; }
-  inline unsigned operator  *= (uint16 i) { d  *= i; return d; }
-  inline unsigned operator  /= (uint16 i) { d  /= i; return d; }
-  inline unsigned operator  &= (uint16 i) { d  &= i; return d; }
-  inline unsigned operator  |= (uint16 i) { d  |= i; return d; }
-  inline unsigned operator  ^= (uint16 i) { d  ^= i; return d; }
-  inline unsigned operator <<= (uint16 i) { d <<= i; return d; }
-  inline unsigned operator >>= (uint16 i) { d >>= i; return d; }
+  inline operator unsigned() const { return d; }
+  template<typename T> inline unsigned operator   = (const T i) { d = uclip<24>(i);      return d; }
+  template<typename T> inline unsigned operator  |= (const T i) { d = uclip<24>(d  | i); return d; }
+  template<typename T> inline unsigned operator  ^= (const T i) { d = uclip<24>(d  ^ i); return d; }
+  template<typename T> inline unsigned operator  &= (const T i) { d = uclip<24>(d  & i); return d; }
+  template<typename T> inline unsigned operator <<= (const T i) { d = uclip<24>(d << i); return d; }
+  template<typename T> inline unsigned operator >>= (const T i) { d = uclip<24>(d >> i); return d; }
+  template<typename T> inline unsigned operator  += (const T i) { d = uclip<24>(d  + i); return d; }
+  template<typename T> inline unsigned operator  -= (const T i) { d = uclip<24>(d  - i); return d; }
+  template<typename T> inline unsigned operator  *= (const T i) { d = uclip<24>(d  * i); return d; }
+  template<typename T> inline unsigned operator  /= (const T i) { d = uclip<24>(d  / i); return d; }
+  template<typename T> inline unsigned operator  %= (const T i) { d = uclip<24>(d  % i); return d; }
+
+  CPUReg24() : d(0) {}
 };
 
 class CPURegs {
@@ -91,7 +69,7 @@ CPUReg24 pc;
 CPUReg16 a, x, y, s, d;
 CPURegFlags p;
 uint8 db;
-uint8 mdr; //memory data register (openbus)
+uint8 mdr;
 bool  e;
-  CPURegs() { db = 0; mdr = 0x00; e = false; }
+  CPURegs() : db(0), mdr(0x00), e(false) {}
 };

src/cpu/dcpu.cpp

@@ -1,30 +1,28 @@
-//this is a virtual function.
-//in opcode-based CPU emulators, the main emulation routine
-//will only be able to call the disassemble_opcode() function
-//on clean opcode edges. but with cycle-based CPU emulators,
-//the CPU may be in the middle of executing an opcode when the
-//emulator (e.g. debugger) wants to disassemble an opcode. this
-//would mean that important registers may not reflect what they
-//did at the start of the opcode (especially regs.pc), so in
-//cycle-based emulators, this function should be overridden to
-//reflect whether or not an opcode has only been partially
-//executed. if not, the debugger should abort attempts to skip,
-//disable, or disassemble the current opcode.
-bool CPU::in_opcode() { return false; }
-
-uint16 CPU::__relb(int8 offset) {
-uint32 addr;
-  addr = (regs.pc.d & 0xff0000) | ((regs.pc.d + 2) & 0xffff);
-  return addr + offset;
+uint8  CPU::dreadb(uint32 addr) {
+  if((addr & 0x40ffff) >= 0x2000 && (addr & 0x40ffff) <= 0x5fff) {
+  //$[00-3f|80-bf]:[2000-5fff]
+  //do not read MMIO registers within debugger
+    return 0x00;
+  }
+  return r_mem->read(addr);
 }
 
-uint16 CPU::__relw(int16 offset) {
-uint32 addr;
-  addr = (regs.pc.d & 0xff0000) | ((regs.pc.d + 3) & 0xffff);
-  return addr + offset;
+uint16 CPU::dreadw(uint32 addr) {
+uint16 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  return r;
 }
 
-uint32 CPU::resolve_offset(uint8 offset_type, uint32 addr) {
+uint32 CPU::dreadl(uint32 addr) {
+uint32 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  r |= dreadb((addr + 2) & 0xffffff) << 16;
+  return r;
+}
+
+uint32 CPU::decode(uint8 offset_type, uint32 addr) {
 uint32 r = 0;
   switch(offset_type) {
   case OPTYPE_DP:
@@ -38,23 +36,23 @@ uint32 r = 0;
     break;
   case OPTYPE_IDP:
     addr = (regs.d + (addr & 0xffff)) & 0xffff;
-    r = (regs.db << 16) + r_mem->read_word(addr);
+    r = (regs.db << 16) + dreadw(addr);
     break;
   case OPTYPE_IDPX:
     addr = (regs.d + regs.x + (addr & 0xffff)) & 0xffff;
-    r = (regs.db << 16) + r_mem->read_word(addr);
+    r = (regs.db << 16) + dreadw(addr);
     break;
   case OPTYPE_IDPY:
     addr = (regs.d + (addr & 0xffff)) & 0xffff;
-    r = (regs.db << 16) + r_mem->read_word(addr) + regs.y;
+    r = (regs.db << 16) + dreadw(addr) + regs.y;
     break;
   case OPTYPE_ILDP:
     addr = (regs.d + (addr & 0xffff)) & 0xffff;
-    r = r_mem->read_long(addr);
+    r = dreadl(addr);
     break;
   case OPTYPE_ILDPY:
     addr = (regs.d + (addr & 0xffff)) & 0xffff;
-    r = r_mem->read_long(addr) + regs.y;
+    r = dreadl(addr) + regs.y;
     break;
   case OPTYPE_ADDR:
     r = (regs.db << 16) + (addr & 0xffff);
@@ -75,31 +73,37 @@ uint32 r = 0;
     r = (regs.pc.b << 16) + ((addr + regs.x) & 0xffff);
     break;
   case OPTYPE_ILADDR:
-    r = addr & 0xffffff;
+    r = addr;
     break;
   case OPTYPE_LONG:
-    r = addr & 0xffffff;
+    r = addr;
     break;
   case OPTYPE_LONGX:
-    r = (addr + regs.x) & 0xffffff;
+    r = (addr + regs.x);
     break;
   case OPTYPE_SR:
     r = (regs.s + (addr & 0xff)) & 0xffff;
     break;
   case OPTYPE_ISRY:
     addr = (regs.s + (addr & 0xff)) & 0xffff;
-    r = (regs.db << 16) + r_mem->read_word(addr) + regs.y;
+    r = (regs.db << 16) + dreadw(addr) + regs.y;
+    break;
+  case OPTYPE_RELB:
+    r  = (regs.pc.b << 16) + ((regs.pc.w + 2) & 0xffff);
+    r += int8(addr);
+    break;
+  case OPTYPE_RELW:
+    r  = (regs.pc.b << 16) + ((regs.pc.w + 3) & 0xffff);
+    r += int16(addr);
     break;
   }
-  return r;
+  return(r & 0xffffff);
 }
 
 void CPU::disassemble_opcode(char *output) {
-char *s;
-char t[256];
-uint8 op, op0, op1, op2;
 static CPUReg24 pc;
-  s = output;
+char t[256];
+char *s = output;
 
   if(in_opcode() == true) {
     strcpy(s, "?????? <CPU within opcode>");
@@ -107,332 +111,338 @@ static CPUReg24 pc;
   }
 
   pc.d = regs.pc.d;
-  sprintf(s, "%0.6x ", pc.d);
+  sprintf(s, "%0.6x ", uint32(pc.d));
 
-  op  = r_mem->read(pc.d); pc.w++;
-  op0 = r_mem->read(pc.d); pc.w++;
-  op1 = r_mem->read(pc.d); pc.w++;
-  op2 = r_mem->read(pc.d);
+uint8 op  = dreadb(pc.d); pc.w++;
+uint8 op0 = dreadb(pc.d); pc.w++;
+uint8 op1 = dreadb(pc.d); pc.w++;
+uint8 op2 = dreadb(pc.d);
 
+#define op8  ((op0))
+#define op16 ((op0) | (op1 << 8))
+#define op24 ((op0) | (op1 << 8) | (op2 << 16))
+#define a8   (regs.e || regs.p.m)
+#define x8   (regs.e || regs.p.x)
   switch(op) {
-  case 0x00:sprintf(t, "brk #$%0.2x               ", op0);break;
-  case 0x01:sprintf(t, "ora ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0x02:sprintf(t, "cop #$%0.2x               ", op0);break;
-  case 0x03:sprintf(t, "ora $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0x04:sprintf(t, "tsb $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x05:sprintf(t, "ora $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x06:sprintf(t, "asl $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x07:sprintf(t, "ora [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0x08:sprintf(t, "php                    ");break;
-  case 0x09:
-    if(regs.p.m)sprintf(t, "ora #$%0.2x               ", op0);
-    else        sprintf(t, "ora #$%0.4x             ", op0|op1<<8);break;
-  case 0x0a:sprintf(t, "asl a                  ");break;
-  case 0x0b:sprintf(t, "phd                    ");break;
-  case 0x0c:sprintf(t, "tsb $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x0d:sprintf(t, "ora $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x0e:sprintf(t, "asl $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x0f:sprintf(t, "ora $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x10:sprintf(t, "bpl $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x11:sprintf(t, "ora ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0x12:sprintf(t, "ora ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0x13:sprintf(t, "ora ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0x14:sprintf(t, "trb $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x15:sprintf(t, "ora $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x16:sprintf(t, "asl $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x17:sprintf(t, "ora [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0x18:sprintf(t, "clc                    ");break;
-  case 0x19:sprintf(t, "ora $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0x1a:sprintf(t, "inc                    ");break;
-  case 0x1b:sprintf(t, "tcs                    ");break;
-  case 0x1c:sprintf(t, "trb $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x1d:sprintf(t, "ora $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x1e:sprintf(t, "asl $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x1f:sprintf(t, "ora $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0x20:sprintf(t, "jsr $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR_PC, (op0|op1<<8)));break;
-  case 0x21:sprintf(t, "and ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0x22:sprintf(t, "jsl $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x23:sprintf(t, "and $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0x24:sprintf(t, "bit $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x25:sprintf(t, "and $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x26:sprintf(t, "rol $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x27:sprintf(t, "and [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0x28:sprintf(t, "plp                    ");break;
-  case 0x29:
-    if(regs.p.m)sprintf(t, "and #$%0.2x               ", op0);
-    else        sprintf(t, "and #$%0.4x             ", op0|op1<<8);break;
-  case 0x2a:sprintf(t, "rol a                  ");break;
-  case 0x2b:sprintf(t, "pld                    ");break;
-  case 0x2c:sprintf(t, "bit $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x2d:sprintf(t, "and $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x2e:sprintf(t, "rol $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x2f:sprintf(t, "and $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x30:sprintf(t, "bmi $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x31:sprintf(t, "and ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0x32:sprintf(t, "and ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0x33:sprintf(t, "and ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0x34:sprintf(t, "bit $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x35:sprintf(t, "and $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x36:sprintf(t, "rol $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x37:sprintf(t, "and [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0x38:sprintf(t, "sec                    ");break;
-  case 0x39:sprintf(t, "and $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0x3a:sprintf(t, "dec                    ");break;
-  case 0x3b:sprintf(t, "tsc                    ");break;
-  case 0x3c:sprintf(t, "bit $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x3d:sprintf(t, "and $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x3e:sprintf(t, "rol $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x3f:sprintf(t, "and $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0x40:sprintf(t, "rti                    ");break;
-  case 0x41:sprintf(t, "eor ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0x42:sprintf(t, "wdm                    ");break;
-  case 0x43:sprintf(t, "eor $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0x44:sprintf(t, "mvp $%0.2x,$%0.2x            ", op1, op0);break;
-  case 0x45:sprintf(t, "eor $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x46:sprintf(t, "lsr $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x47:sprintf(t, "eor [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0x48:sprintf(t, "pha                    ");break;
-  case 0x49:
-    if(regs.p.m)sprintf(t, "eor #$%0.2x               ", op0);
-    else        sprintf(t, "eor #$%0.4x             ", op0|op1<<8);break;
-  case 0x4a:sprintf(t, "lsr a                  ");break;
-  case 0x4b:sprintf(t, "phk                    ");break;
-  case 0x4c:sprintf(t, "jmp $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR_PC, (op0|op1<<8)));break;
-  case 0x4d:sprintf(t, "eor $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x4e:sprintf(t, "lsr $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x4f:sprintf(t, "eor $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x50:sprintf(t, "bvc $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x51:sprintf(t, "eor ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0x52:sprintf(t, "eor ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0x53:sprintf(t, "eor ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0x54:sprintf(t, "mvn $%0.2x,$%0.2x            ", op1, op0);break;
-  case 0x55:sprintf(t, "eor $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x56:sprintf(t, "lsr $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x57:sprintf(t, "eor [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0x58:sprintf(t, "cli                    ");break;
-  case 0x59:sprintf(t, "eor $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0x5a:sprintf(t, "phy                    ");break;
-  case 0x5b:sprintf(t, "tcd                    ");break;
-  case 0x5c:sprintf(t, "jml $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x5d:sprintf(t, "eor $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x5e:sprintf(t, "lsr $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x5f:sprintf(t, "eor $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0x60:sprintf(t, "rts                    ");break;
-  case 0x61:sprintf(t, "adc ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0x62:sprintf(t, "per $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x63:sprintf(t, "adc $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0x64:sprintf(t, "stz $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x65:sprintf(t, "adc $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x66:sprintf(t, "ror $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x67:sprintf(t, "adc [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0x68:sprintf(t, "pla                    ");break;
-  case 0x69:
-    if(regs.p.m)sprintf(t, "adc #$%0.2x               ", op0);
-    else        sprintf(t, "adc #$%0.4x             ", op0|op1<<8);break;
-  case 0x6a:sprintf(t, "ror a                  ");break;
-  case 0x6b:sprintf(t, "rtl                    ");break;
-  case 0x6c:sprintf(t, "jmp ($%0.4x)   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_IADDR_PC, (op0|op1<<8)));break;
-  case 0x6d:sprintf(t, "adc $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x6e:sprintf(t, "ror $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x6f:sprintf(t, "adc $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x70:sprintf(t, "bvs $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x71:sprintf(t, "adc ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0x72:sprintf(t, "adc ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0x73:sprintf(t, "adc ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0x74:sprintf(t, "stz $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x75:sprintf(t, "adc $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x76:sprintf(t, "ror $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x77:sprintf(t, "adc [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0x78:sprintf(t, "sei                    ");break;
-  case 0x79:sprintf(t, "adc $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0x7a:sprintf(t, "ply                    ");break;
-  case 0x7b:sprintf(t, "tdc                    ");break;
-  case 0x7c:sprintf(t, "jmp ($%0.4x,x) [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_IADDRX, (op0|op1<<8)));break;
-  case 0x7d:sprintf(t, "adc $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x7e:sprintf(t, "ror $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x7f:sprintf(t, "adc $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0x80:sprintf(t, "bra $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x81:sprintf(t, "sta ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0x82:sprintf(t, "brl $%0.4x     [$%0.6x]", __relw(op0|op1<<8)&0xffff, __relw(op0|op1<<8)&0xffffff);break;
-  case 0x83:sprintf(t, "sta $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0x84:sprintf(t, "sty $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x85:sprintf(t, "sta $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x86:sprintf(t, "stx $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0x87:sprintf(t, "sta [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0x88:sprintf(t, "dey                    ");break;
-  case 0x89:
-    if(regs.p.m)sprintf(t, "bit #$%0.2x               ", op0);
-    else        sprintf(t, "bit #$%0.4x             ", op0|op1<<8);break;
-  case 0x8a:sprintf(t, "txa                    ");break;
-  case 0x8b:sprintf(t, "phb                    ");break;
-  case 0x8c:sprintf(t, "sty $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x8d:sprintf(t, "sta $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x8e:sprintf(t, "stx $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x8f:sprintf(t, "sta $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0x90:sprintf(t, "bcc $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0x91:sprintf(t, "sta ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0x92:sprintf(t, "sta ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0x93:sprintf(t, "sta ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0x94:sprintf(t, "sty $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x95:sprintf(t, "sta $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0x96:sprintf(t, "stx $%0.2x,y     [$%0.6x]", op0, resolve_offset(OPTYPE_DPY, op0));break;
-  case 0x97:sprintf(t, "sta [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0x98:sprintf(t, "tya                    ");break;
-  case 0x99:sprintf(t, "sta $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0x9a:sprintf(t, "txs                    ");break;
-  case 0x9b:sprintf(t, "txy                    ");break;
-  case 0x9c:sprintf(t, "stz $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0x9d:sprintf(t, "sta $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x9e:sprintf(t, "stz $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0x9f:sprintf(t, "sta $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0xa0:
-    if(regs.p.x)sprintf(t, "ldy #$%0.2x               ", op0);
-    else        sprintf(t, "ldy #$%0.4x             ", op0|op1<<8);break;
-  case 0xa1:sprintf(t, "lda ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0xa2:
-    if(regs.p.x)sprintf(t, "ldx #$%0.2x               ", op0);
-    else        sprintf(t, "ldx #$%0.4x             ", op0|op1<<8);break;
-  case 0xa3:sprintf(t, "lda $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0xa4:sprintf(t, "ldy $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xa5:sprintf(t, "lda $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xa6:sprintf(t, "ldx $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xa7:sprintf(t, "lda [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0xa8:sprintf(t, "tay                    ");break;
-  case 0xa9:
-    if(regs.p.m)sprintf(t, "lda #$%0.2x               ", op0);
-    else        sprintf(t, "lda #$%0.4x             ", op0|op1<<8);break;
-  case 0xaa:sprintf(t, "tax                    ");break;
-  case 0xab:sprintf(t, "plb                    ");break;
-  case 0xac:sprintf(t, "ldy $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xad:sprintf(t, "lda $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xae:sprintf(t, "ldx $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xaf:sprintf(t, "lda $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0xb0:sprintf(t, "bcs $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0xb1:sprintf(t, "lda ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0xb2:sprintf(t, "lda ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0xb3:sprintf(t, "lda ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0xb4:sprintf(t, "ldy $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xb5:sprintf(t, "lda $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xb6:sprintf(t, "ldx $%0.2x,y     [$%0.6x]", op0, resolve_offset(OPTYPE_DPY, op0));break;
-  case 0xb7:sprintf(t, "lda [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0xb8:sprintf(t, "clv                    ");break;
-  case 0xb9:sprintf(t, "lda $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0xba:sprintf(t, "tsx                    ");break;
-  case 0xbb:sprintf(t, "tyx                    ");break;
-  case 0xbc:sprintf(t, "ldy $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xbd:sprintf(t, "lda $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xbe:sprintf(t, "ldx $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0xbf:sprintf(t, "lda $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0xc0:
-    if(regs.p.x)sprintf(t, "cpy #$%0.2x               ", op0);
-    else        sprintf(t, "cpy #$%0.4x             ", op0|op1<<8);break;
-  case 0xc1:sprintf(t, "cmp ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0xc2:sprintf(t, "rep #$%0.2x               ", op0);break;
-  case 0xc3:sprintf(t, "cmp $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0xc4:sprintf(t, "cpy $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xc5:sprintf(t, "cmp $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xc6:sprintf(t, "dec $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xc7:sprintf(t, "cmp [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0xc8:sprintf(t, "iny                    ");break;
-  case 0xc9:
-    if(regs.p.m)sprintf(t, "cmp #$%0.2x               ", op0);
-    else        sprintf(t, "cmp #$%0.4x             ", op0|op1<<8);break;
-  case 0xca:sprintf(t, "dex                    ");break;
-  case 0xcb:sprintf(t, "wai                    ");break;
-  case 0xcc:sprintf(t, "cpy $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xcd:sprintf(t, "cmp $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xce:sprintf(t, "dec $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xcf:sprintf(t, "cmp $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0xd0:sprintf(t, "bne $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0xd1:sprintf(t, "cmp ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0xd2:sprintf(t, "cmp ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0xd3:sprintf(t, "cmp ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0xd4:sprintf(t, "pei ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0xd5:sprintf(t, "cmp $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xd6:sprintf(t, "dec $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xd7:sprintf(t, "cmp [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0xd8:sprintf(t, "cld                    ");break;
-  case 0xd9:sprintf(t, "cmp $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0xda:sprintf(t, "phx                    ");break;
-  case 0xdb:sprintf(t, "stp                    ");break;
-  case 0xdc:sprintf(t, "jmp [$%0.4x]   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ILADDR, (op0|op1<<8)));break;
-  case 0xdd:sprintf(t, "cmp $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xde:sprintf(t, "dec $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xdf:sprintf(t, "cmp $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
-  case 0xe0:
-    if(regs.p.x)sprintf(t, "cpx #$%0.2x               ", op0);
-    else        sprintf(t, "cpx #$%0.4x             ", op0|op1<<8);break;
-  case 0xe1:sprintf(t, "sbc ($%0.2x,x)   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPX, op0));break;
-  case 0xe2:sprintf(t, "sep #$%0.2x               ", op0);break;
-  case 0xe3:sprintf(t, "sbc $%0.2x,s     [$%0.6x]", op0, resolve_offset(OPTYPE_SR, op0));break;
-  case 0xe4:sprintf(t, "cpx $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xe5:sprintf(t, "sbc $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xe6:sprintf(t, "inc $%0.2x       [$%0.6x]", op0, resolve_offset(OPTYPE_DP, op0));break;
-  case 0xe7:sprintf(t, "sbc [$%0.2x]     [$%0.6x]", op0, resolve_offset(OPTYPE_ILDP, op0));break;
-  case 0xe8:sprintf(t, "inx                    ");break;
-  case 0xe9:
-    if(regs.p.m)sprintf(t, "sbc #$%0.2x               ", op0);
-    else        sprintf(t, "sbc #$%0.4x             ", op0|op1<<8);break;
-  case 0xea:sprintf(t, "nop                    ");break;
-  case 0xeb:sprintf(t, "xba                    ");break;
-  case 0xec:sprintf(t, "cpx $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xed:sprintf(t, "sbc $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xee:sprintf(t, "inc $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xef:sprintf(t, "sbc $%0.6x   [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONG, (op0|op1<<8|op2<<16)));break;
-  case 0xf0:sprintf(t, "beq $%0.4x     [$%0.6x]", __relb(op0)&0xffff, __relb(op0)&0xffffff);break;
-  case 0xf1:sprintf(t, "sbc ($%0.2x),y   [$%0.6x]", op0, resolve_offset(OPTYPE_IDPY, op0));break;
-  case 0xf2:sprintf(t, "sbc ($%0.2x)     [$%0.6x]", op0, resolve_offset(OPTYPE_IDP, op0));break;
-  case 0xf3:sprintf(t, "sbc ($%0.2x,s),y [$%0.6x]", op0, resolve_offset(OPTYPE_ISRY, op0));break;
-  case 0xf4:sprintf(t, "pea $%0.4x     [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDR, (op0|op1<<8)));break;
-  case 0xf5:sprintf(t, "sbc $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xf6:sprintf(t, "inc $%0.2x,x     [$%0.6x]", op0, resolve_offset(OPTYPE_DPX, op0));break;
-  case 0xf7:sprintf(t, "sbc [$%0.2x],y   [$%0.6x]", op0, resolve_offset(OPTYPE_ILDPY, op0));break;
-  case 0xf8:sprintf(t, "sed                    ");break;
-  case 0xf9:sprintf(t, "sbc $%0.4x,y   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRY, (op0|op1<<8)));break;
-  case 0xfa:sprintf(t, "plx                    ");break;
-  case 0xfb:sprintf(t, "xce                    ");break;
-  case 0xfc:sprintf(t, "jsr ($%0.4x,x) [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_IADDRX, (op0|op1<<8)));break;
-  case 0xfd:sprintf(t, "sbc $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xfe:sprintf(t, "inc $%0.4x,x   [$%0.6x]", op0|op1<<8, resolve_offset(OPTYPE_ADDRX, (op0|op1<<8)));break;
-  case 0xff:sprintf(t, "sbc $%0.6x,x [$%0.6x]", op0|op1<<8|op2<<16, resolve_offset(OPTYPE_LONGX, (op0|op1<<8|op2<<16)));break;
+  case 0x00: sprintf(t, "brk #$%0.2x               ", op8); break;
+  case 0x01: sprintf(t, "ora ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0x02: sprintf(t, "cop #$%0.2x               ", op8); break;
+  case 0x03: sprintf(t, "ora $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0x04: sprintf(t, "tsb $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x05: sprintf(t, "ora $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x06: sprintf(t, "asl $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x07: sprintf(t, "ora [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0x08: sprintf(t, "php                    "); break;
+  case 0x09: if(a8)sprintf(t, "ora #$%0.2x               ", op8);
+             else  sprintf(t, "ora #$%0.4x             ", op16); break;
+  case 0x0a: sprintf(t, "asl a                  "); break;
+  case 0x0b: sprintf(t, "phd                    "); break;
+  case 0x0c: sprintf(t, "tsb $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x0d: sprintf(t, "ora $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x0e: sprintf(t, "asl $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x0f: sprintf(t, "ora $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x10: sprintf(t, "bpl $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x11: sprintf(t, "ora ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0x12: sprintf(t, "ora ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0x13: sprintf(t, "ora ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0x14: sprintf(t, "trb $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x15: sprintf(t, "ora $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x16: sprintf(t, "asl $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x17: sprintf(t, "ora [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0x18: sprintf(t, "clc                    "); break;
+  case 0x19: sprintf(t, "ora $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0x1a: sprintf(t, "inc                    "); break;
+  case 0x1b: sprintf(t, "tcs                    "); break;
+  case 0x1c: sprintf(t, "trb $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x1d: sprintf(t, "ora $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x1e: sprintf(t, "asl $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x1f: sprintf(t, "ora $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0x20: sprintf(t, "jsr $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+  case 0x21: sprintf(t, "and ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0x22: sprintf(t, "jsl $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x23: sprintf(t, "and $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0x24: sprintf(t, "bit $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x25: sprintf(t, "and $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x26: sprintf(t, "rol $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x27: sprintf(t, "and [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0x28: sprintf(t, "plp                    "); break;
+  case 0x29: if(a8)sprintf(t, "and #$%0.2x               ", op8);
+             else  sprintf(t, "and #$%0.4x             ", op16); break;
+  case 0x2a: sprintf(t, "rol a                  "); break;
+  case 0x2b: sprintf(t, "pld                    "); break;
+  case 0x2c: sprintf(t, "bit $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x2d: sprintf(t, "and $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x2e: sprintf(t, "rol $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x2f: sprintf(t, "and $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x30: sprintf(t, "bmi $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x31: sprintf(t, "and ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0x32: sprintf(t, "and ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0x33: sprintf(t, "and ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0x34: sprintf(t, "bit $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x35: sprintf(t, "and $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x36: sprintf(t, "rol $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x37: sprintf(t, "and [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0x38: sprintf(t, "sec                    "); break;
+  case 0x39: sprintf(t, "and $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0x3a: sprintf(t, "dec                    "); break;
+  case 0x3b: sprintf(t, "tsc                    "); break;
+  case 0x3c: sprintf(t, "bit $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x3d: sprintf(t, "and $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x3e: sprintf(t, "rol $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x3f: sprintf(t, "and $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0x40: sprintf(t, "rti                    "); break;
+  case 0x41: sprintf(t, "eor ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0x42: sprintf(t, "wdm                    "); break;
+  case 0x43: sprintf(t, "eor $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0x44: sprintf(t, "mvp $%0.2x,$%0.2x            ", op1, op8); break;
+  case 0x45: sprintf(t, "eor $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x46: sprintf(t, "lsr $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x47: sprintf(t, "eor [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0x48: sprintf(t, "pha                    "); break;
+  case 0x49: if(a8)sprintf(t, "eor #$%0.2x               ", op8);
+             else  sprintf(t, "eor #$%0.4x             ", op16); break;
+  case 0x4a: sprintf(t, "lsr a                  "); break;
+  case 0x4b: sprintf(t, "phk                    "); break;
+  case 0x4c: sprintf(t, "jmp $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+  case 0x4d: sprintf(t, "eor $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x4e: sprintf(t, "lsr $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x4f: sprintf(t, "eor $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x50: sprintf(t, "bvc $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x51: sprintf(t, "eor ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0x52: sprintf(t, "eor ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0x53: sprintf(t, "eor ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0x54: sprintf(t, "mvn $%0.2x,$%0.2x            ", op1, op8); break;
+  case 0x55: sprintf(t, "eor $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x56: sprintf(t, "lsr $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x57: sprintf(t, "eor [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0x58: sprintf(t, "cli                    "); break;
+  case 0x59: sprintf(t, "eor $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0x5a: sprintf(t, "phy                    "); break;
+  case 0x5b: sprintf(t, "tcd                    "); break;
+  case 0x5c: sprintf(t, "jml $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x5d: sprintf(t, "eor $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x5e: sprintf(t, "lsr $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x5f: sprintf(t, "eor $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0x60: sprintf(t, "rts                    "); break;
+  case 0x61: sprintf(t, "adc ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0x62: sprintf(t, "per $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x63: sprintf(t, "adc $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0x64: sprintf(t, "stz $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x65: sprintf(t, "adc $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x66: sprintf(t, "ror $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x67: sprintf(t, "adc [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0x68: sprintf(t, "pla                    "); break;
+  case 0x69: if(a8)sprintf(t, "adc #$%0.2x               ", op8);
+             else  sprintf(t, "adc #$%0.4x             ", op16); break;
+  case 0x6a: sprintf(t, "ror a                  "); break;
+  case 0x6b: sprintf(t, "rtl                    "); break;
+  case 0x6c: sprintf(t, "jmp ($%0.4x)   [$%0.6x]", op16, decode(OPTYPE_IADDR_PC, op16)); break;
+  case 0x6d: sprintf(t, "adc $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x6e: sprintf(t, "ror $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x6f: sprintf(t, "adc $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x70: sprintf(t, "bvs $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x71: sprintf(t, "adc ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0x72: sprintf(t, "adc ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0x73: sprintf(t, "adc ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0x74: sprintf(t, "stz $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x75: sprintf(t, "adc $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x76: sprintf(t, "ror $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x77: sprintf(t, "adc [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0x78: sprintf(t, "sei                    "); break;
+  case 0x79: sprintf(t, "adc $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0x7a: sprintf(t, "ply                    "); break;
+  case 0x7b: sprintf(t, "tdc                    "); break;
+  case 0x7c: sprintf(t, "jmp ($%0.4x,x) [$%0.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+  case 0x7d: sprintf(t, "adc $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x7e: sprintf(t, "ror $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x7f: sprintf(t, "adc $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0x80: sprintf(t, "bra $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x81: sprintf(t, "sta ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0x82: sprintf(t, "brl $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELW, op16)), decode(OPTYPE_RELW, op16)); break;
+  case 0x83: sprintf(t, "sta $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0x84: sprintf(t, "sty $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x85: sprintf(t, "sta $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x86: sprintf(t, "stx $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0x87: sprintf(t, "sta [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0x88: sprintf(t, "dey                    "); break;
+  case 0x89: if(a8)sprintf(t, "bit #$%0.2x               ", op8);
+             else  sprintf(t, "bit #$%0.4x             ", op16); break;
+  case 0x8a: sprintf(t, "txa                    "); break;
+  case 0x8b: sprintf(t, "phb                    "); break;
+  case 0x8c: sprintf(t, "sty $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x8d: sprintf(t, "sta $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x8e: sprintf(t, "stx $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x8f: sprintf(t, "sta $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0x90: sprintf(t, "bcc $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0x91: sprintf(t, "sta ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0x92: sprintf(t, "sta ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0x93: sprintf(t, "sta ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0x94: sprintf(t, "sty $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x95: sprintf(t, "sta $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0x96: sprintf(t, "stx $%0.2x,y     [$%0.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+  case 0x97: sprintf(t, "sta [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0x98: sprintf(t, "tya                    "); break;
+  case 0x99: sprintf(t, "sta $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0x9a: sprintf(t, "txs                    "); break;
+  case 0x9b: sprintf(t, "txy                    "); break;
+  case 0x9c: sprintf(t, "stz $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0x9d: sprintf(t, "sta $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x9e: sprintf(t, "stz $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0x9f: sprintf(t, "sta $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0xa0: if(x8)sprintf(t, "ldy #$%0.2x               ", op8);
+             else  sprintf(t, "ldy #$%0.4x             ", op16); break;
+  case 0xa1: sprintf(t, "lda ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0xa2: if(x8)sprintf(t, "ldx #$%0.2x               ", op8);
+             else  sprintf(t, "ldx #$%0.4x             ", op16); break;
+  case 0xa3: sprintf(t, "lda $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0xa4: sprintf(t, "ldy $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xa5: sprintf(t, "lda $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xa6: sprintf(t, "ldx $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xa7: sprintf(t, "lda [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0xa8: sprintf(t, "tay                    "); break;
+  case 0xa9: if(a8)sprintf(t, "lda #$%0.2x               ", op8);
+             else  sprintf(t, "lda #$%0.4x             ", op16); break;
+  case 0xaa: sprintf(t, "tax                    "); break;
+  case 0xab: sprintf(t, "plb                    "); break;
+  case 0xac: sprintf(t, "ldy $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xad: sprintf(t, "lda $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xae: sprintf(t, "ldx $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xaf: sprintf(t, "lda $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0xb0: sprintf(t, "bcs $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0xb1: sprintf(t, "lda ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0xb2: sprintf(t, "lda ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0xb3: sprintf(t, "lda ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0xb4: sprintf(t, "ldy $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xb5: sprintf(t, "lda $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xb6: sprintf(t, "ldx $%0.2x,y     [$%0.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+  case 0xb7: sprintf(t, "lda [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0xb8: sprintf(t, "clv                    "); break;
+  case 0xb9: sprintf(t, "lda $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0xba: sprintf(t, "tsx                    "); break;
+  case 0xbb: sprintf(t, "tyx                    "); break;
+  case 0xbc: sprintf(t, "ldy $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xbd: sprintf(t, "lda $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xbe: sprintf(t, "ldx $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0xbf: sprintf(t, "lda $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0xc0: if(x8)sprintf(t, "cpy #$%0.2x               ", op8);
+             else  sprintf(t, "cpy #$%0.4x             ", op16); break;
+  case 0xc1: sprintf(t, "cmp ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0xc2: sprintf(t, "rep #$%0.2x               ", op8); break;
+  case 0xc3: sprintf(t, "cmp $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0xc4: sprintf(t, "cpy $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xc5: sprintf(t, "cmp $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xc6: sprintf(t, "dec $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xc7: sprintf(t, "cmp [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0xc8: sprintf(t, "iny                    "); break;
+  case 0xc9: if(a8)sprintf(t, "cmp #$%0.2x               ", op8);
+             else  sprintf(t, "cmp #$%0.4x             ", op16); break;
+  case 0xca: sprintf(t, "dex                    "); break;
+  case 0xcb: sprintf(t, "wai                    "); break;
+  case 0xcc: sprintf(t, "cpy $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xcd: sprintf(t, "cmp $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xce: sprintf(t, "dec $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xcf: sprintf(t, "cmp $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0xd0: sprintf(t, "bne $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0xd1: sprintf(t, "cmp ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0xd2: sprintf(t, "cmp ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0xd3: sprintf(t, "cmp ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0xd4: sprintf(t, "pei ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0xd5: sprintf(t, "cmp $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xd6: sprintf(t, "dec $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xd7: sprintf(t, "cmp [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0xd8: sprintf(t, "cld                    "); break;
+  case 0xd9: sprintf(t, "cmp $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0xda: sprintf(t, "phx                    "); break;
+  case 0xdb: sprintf(t, "stp                    "); break;
+  case 0xdc: sprintf(t, "jmp [$%0.4x]   [$%0.6x]", op16, decode(OPTYPE_ILADDR, op16)); break;
+  case 0xdd: sprintf(t, "cmp $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xde: sprintf(t, "dec $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xdf: sprintf(t, "cmp $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  case 0xe0: if(x8)sprintf(t, "cpx #$%0.2x               ", op8);
+             else  sprintf(t, "cpx #$%0.4x             ", op16); break;
+  case 0xe1: sprintf(t, "sbc ($%0.2x,x)   [$%0.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+  case 0xe2: sprintf(t, "sep #$%0.2x               ", op8); break;
+  case 0xe3: sprintf(t, "sbc $%0.2x,s     [$%0.6x]", op8, decode(OPTYPE_SR, op8)); break;
+  case 0xe4: sprintf(t, "cpx $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xe5: sprintf(t, "sbc $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xe6: sprintf(t, "inc $%0.2x       [$%0.6x]", op8, decode(OPTYPE_DP, op8)); break;
+  case 0xe7: sprintf(t, "sbc [$%0.2x]     [$%0.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+  case 0xe8: sprintf(t, "inx                    "); break;
+  case 0xe9: if(a8)sprintf(t, "sbc #$%0.2x               ", op8);
+             else  sprintf(t, "sbc #$%0.4x             ", op16); break;
+  case 0xea: sprintf(t, "nop                    "); break;
+  case 0xeb: sprintf(t, "xba                    "); break;
+  case 0xec: sprintf(t, "cpx $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xed: sprintf(t, "sbc $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xee: sprintf(t, "inc $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xef: sprintf(t, "sbc $%0.6x   [$%0.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+  case 0xf0: sprintf(t, "beq $%0.4x     [$%0.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+  case 0xf1: sprintf(t, "sbc ($%0.2x),y   [$%0.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+  case 0xf2: sprintf(t, "sbc ($%0.2x)     [$%0.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+  case 0xf3: sprintf(t, "sbc ($%0.2x,s),y [$%0.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+  case 0xf4: sprintf(t, "pea $%0.4x     [$%0.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+  case 0xf5: sprintf(t, "sbc $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xf6: sprintf(t, "inc $%0.2x,x     [$%0.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+  case 0xf7: sprintf(t, "sbc [$%0.2x],y   [$%0.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+  case 0xf8: sprintf(t, "sed                    "); break;
+  case 0xf9: sprintf(t, "sbc $%0.4x,y   [$%0.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+  case 0xfa: sprintf(t, "plx                    "); break;
+  case 0xfb: sprintf(t, "xce                    "); break;
+  case 0xfc: sprintf(t, "jsr ($%0.4x,x) [$%0.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+  case 0xfd: sprintf(t, "sbc $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xfe: sprintf(t, "inc $%0.4x,x   [$%0.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+  case 0xff: sprintf(t, "sbc $%0.6x,x [$%0.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
   }
+#undef op8
+#undef op16
+#undef op24
+#undef a8
+#undef x8
+
   strcat(s, t);
   strcat(s, " ");
 
   sprintf(t, "A:%0.4x X:%0.4x Y:%0.4x S:%0.4x D:%0.4x DB:%0.2x ",
     regs.a.w, regs.x.w, regs.y.w, regs.s.w, regs.d.w, regs.db);
   strcat(s, t);
+
   if(regs.e) {
     sprintf(t, "%c%c%c%c%c%c%c%c",
-      (regs.p.n)?'N':'n', (regs.p.v)?'V':'v',
-      (regs.p.m)?'1':'0', (regs.p.x)?'B':'b',
-      (regs.p.d)?'D':'d', (regs.p.i)?'I':'i',
-      (regs.p.z)?'Z':'z', (regs.p.c)?'C':'c');
+      (regs.p.n) ? 'N' : 'n', (regs.p.v) ? 'V' : 'v',
+      (regs.p.m) ? '1' : '0', (regs.p.x) ? 'B' : 'b',
+      (regs.p.d) ? 'D' : 'd', (regs.p.i) ? 'I' : 'i',
+      (regs.p.z) ? 'Z' : 'z', (regs.p.c) ? 'C' : 'c');
   } else {
     sprintf(t, "%c%c%c%c%c%c%c%c",
-      (regs.p.n)?'N':'n', (regs.p.v)?'V':'v',
-      (regs.p.m)?'M':'m', (regs.p.x)?'X':'x',
-      (regs.p.d)?'D':'d', (regs.p.i)?'I':'i',
-      (regs.p.z)?'Z':'z', (regs.p.c)?'C':'c');
+      (regs.p.n) ? 'N' : 'n', (regs.p.v) ? 'V' : 'v',
+      (regs.p.m) ? 'M' : 'm', (regs.p.x) ? 'X' : 'x',
+      (regs.p.d) ? 'D' : 'd', (regs.p.i) ? 'I' : 'i',
+      (regs.p.z) ? 'Z' : 'z', (regs.p.c) ? 'C' : 'c');
   }
+
+  strcat(s, t);
+  strcat(s, " ");
+
+  sprintf(t, "V:%3d H:%4d", vcounter(), hclock());
   strcat(s, t);
 }
 
-/*
-  opcode_length() retrieves the length of the next opcode
-  to be executed. It is used by the debugger to step over,
-  disable, and proceed cpu opcodes.
-
-  5 and 6 are special cases, 5 is used for #consts based on
-  the A register size, 6 for the X/Y register size. the
-  rest are literal sizes. There's no need to test for
-  emulation mode, as regs.p.m/regs.p.x should *always* be
-  set in emulation mode.
-*/
+/*****
+ * opcode_length() retrieves the length of the next opcode
+ * to be executed. It is used by the debugger to step over,
+ * disable and proceed cpu opcodes.
+ *
+ * 5 and 6 are special cases, 5 is used for #consts based on
+ * the A register size, 6 for the X/Y register size. the
+ * rest are literal sizes. There's no need to test for
+ * emulation mode, as regs.p.m/regs.p.x should *always* be
+ * set in emulation mode.
+ *****/
 uint8 CPU::opcode_length() {
 uint8 op, len;
 static uint8 op_len_tbl[256] = {
 //0,1,2,3,  4,5,6,7,  8,9,a,b,  c,d,e,f
+
   2,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x0n
   2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x1n
   3,2,4,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x2n
@@ -457,9 +467,9 @@ static uint8 op_len_tbl[256] = {
     return 0;
   }
 
-  op = r_mem->read(regs.pc.d);
+  op  = dreadb(regs.pc.d);
   len = op_len_tbl[op];
-  if(len == 5)return (regs.p.m)?2:3;
-  if(len == 6)return (regs.p.x)?2:3;
+  if(len == 5)return (regs.e || regs.p.m) ? 2 : 3;
+  if(len == 6)return (regs.e || regs.p.x) ? 2 : 3;
   return len;
 }

src/cpu/scpu/core/cc.bat

@@ -0,0 +1,3 @@
+cl /nologo /O2 scpugen.cpp
+@pause
+@del *.obj

src/cpu/scpu/core/clean.bat

@@ -0,0 +1 @@
+@del *.exe

src/cpu/scpu/core/core.cpp

@@ -0,0 +1,64 @@
+#include "opfn.cpp"
+
+#include "op_read.cpp"
+#include "op_write.cpp"
+#include "op_rmw.cpp"
+#include "op_pc.cpp"
+#include "op_misc.cpp"
+
+void sCPU::enter() { loop:
+  if(event.irq) {
+    event.irq = false;
+    if(status.nmi_pending == true) {
+      status.nmi_pending = false;
+      event.irq_vector = (regs.e == false) ? 0xffea : 0xfffa;
+    } else if(status.irq_pending == true) {
+      status.irq_pending = false;
+      event.irq_vector = (regs.e == false) ? 0xffee : 0xfffe;
+    }
+    op_irq();
+  }
+
+  tracer.trace_cpuop(); //traces CPU opcode (only if tracer is enabled)
+
+  status.in_opcode = true;
+  (this->*optbl[op_readpc()])();
+  status.in_opcode = false;
+
+  goto loop;
+}
+
+void sCPU::op_irq() {
+  op_read(regs.pc.d);
+  op_io();
+  if(!regs.e)op_writestack(regs.pc.b);
+  op_writestack(regs.pc.h);
+  op_writestack(regs.pc.l);
+  op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
+  rd.l = op_read(event.irq_vector + 0);
+  regs.pc.b = 0x00;
+  regs.p.i  = 1;
+  regs.p.d  = 0;
+  rd.h = op_read(event.irq_vector + 1);
+  regs.pc.w = rd.w;
+}
+
+//
+
+alwaysinline void sCPU::op_io_cond2() {
+  if(regs.d.l != 0x00) {
+    op_io();
+  }
+}
+
+alwaysinline void sCPU::op_io_cond4(uint16 x, uint16 y) {
+  if(!regs.p.x || (x & 0xff00) != (y & 0xff00)) {
+    op_io();
+  }
+}
+
+alwaysinline void sCPU::op_io_cond6(uint16 addr) {
+  if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
+    op_io();
+  }
+}