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AArch64: prevent literal displacement truncation (#2984)

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Widen AArch64 memory displacements to 64 bits (int64_t) and update cstool,
cstest, regression coverage, and release documentation accordingly.

Signed-off-by: Amaan Mujawar <[email protected]>
This commit is contained in:
Amaan Mujawar
2026-07-18 17:02:29 +00:00
committed by GitHub
parent 032f79993d
commit 44ca257811
6 changed files with 31 additions and 5 deletions
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cstool/cstool_aarch64.c
+3 -2
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@@ -63,8 +63,9 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0 ||
op->mem.base == AARCH64_REG_INVALID)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
op->mem.disp);
printf("\t\toperands[%u].mem.disp: 0x%" PRIx64
"\n",
i, (uint64_t)op->mem.disp);
if (ins->detail->aarch64.post_index)
printf("\t\t\tpost-indexed: true\n");
docs/cs_v6_release_guide.md
+1
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@@ -443,6 +443,7 @@ Such an instruction is ill-defined in LLVM and should be fixed upstream.
| ---------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
| ARM64 -> AArch64 | ARM64 was everywhere renamed to AArch64 to match the LLVM naming. | See below. |
| Post-index | Post-index memory access has the disponent now set int the `MEMORY` operand! No longer as separated `reg`/`imm` operand. | See post-index explanation for ARM. |
| `mem.disp` | `cs_aarch64_op.mem.disp` changed from `int32_t` to `int64_t`. | Prevent truncation of large AArch64 memory displacements. |
| `SME` operands | `SME` operands contain more detail now and member names are closer to the ISA terminology. | New SVE2, SME extensions required more detail. |
| System operands | System Operands are separated into different types now. | System operands follow a special encoding. Some byte sequences match two different operands. Hence, a more detailed concept was necessary. |
| `writeback` | `writeback` member was moved to detail. | See ARM explanation. |
include/capstone/aarch64.h
+1 -1
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@@ -2786,7 +2786,7 @@ typedef enum aarch64_reg {
typedef struct aarch64_op_mem {
aarch64_reg base; ///< base register
aarch64_reg index; ///< index register
int32_t disp; ///< displacement/offset value
int64_t disp; ///< displacement/offset value
} aarch64_op_mem;
typedef enum {
suite/cstest/include/test_detail_aarch64.h
+1 -1
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@@ -52,7 +52,7 @@ typedef struct {
int64_t imm;
char *mem_base;
char *mem_index;
int32_t mem_disp;
int64_t mem_disp;
int8_t imm_range_first;
int8_t imm_range_offset;
suite/cstest/src/test_detail_aarch64.c
+1 -1
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@@ -204,7 +204,7 @@ bool test_expected_aarch64(csh *handle, cs_aarch64 *actual,
false);
compare_reg_ret(*handle, op->mem.index, eop->mem_index,
false);
compare_int32_ret(op->mem.disp, eop->mem_disp, false);
compare_int64_ret(op->mem.disp, eop->mem_disp, false);
break;
case AARCH64_OP_PRED:
compare_reg_ret(*handle, op->pred.reg, eop->pred_reg,
tests/issues/issues.yaml
+24
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@@ -6859,3 +6859,27 @@ test_cases:
shift_type: AARCH64_SFT_LSL
shift_value: 16
regs_write: [ w4 ]
-
input:
name: "issue 2878 AArch64 LDR literal detail operand truncation"
bytes: [ 0xa8, 0x79, 0x29, 0x58 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
address: 0x100c894d4
expected:
insns:
-
asm_text: "ldr x8, 0x100cdc408"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x8
access: CS_AC_WRITE
-
type: AARCH64_OP_MEM
mem_disp: 0x100cdc408
access: CS_AC_READ
regs_write: [ x8 ]