1997-05-05 12:46:25 +00:00
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// Texas Instruments TMS320C80 (MVP) Simulator.
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// Copyright (C) 1997 Free Software Foundation, Inc.
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// Contributed by Cygnus Support.
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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1997-05-07 13:58:52 +00:00
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// The following is called when ever an illegal instruction is encountered.
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1997-04-22 17:46:07 +00:00
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::internal::illegal
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1997-05-19 03:42:33 +00:00
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sim_io_eprintf (SD, "0x%lx: illegal instruction\n", (unsigned long) cia.ip);
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sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
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1997-05-07 13:58:52 +00:00
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// The following is called when ever an FP op is attempted with FPU disabled.
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::internal::fp_unavailable
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1997-05-19 03:42:33 +00:00
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sim_io_eprintf (SD, "0x%lx: floating-point unavailable\n", (unsigned long) cia.ip);
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sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGFPE);
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1997-05-13 13:57:49 +00:00
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// Handle a branch instruction
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instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
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instruction_address nia;
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if (annul)
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{
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if (rLink_p)
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*rLink = cia.dp;
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nia.ip = target;
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nia.dp = target + 4;
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}
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else
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{
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if (rLink_p)
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*rLink = cia.dp + sizeof (instruction_word);
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nia.ip = cia.dp;
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nia.dp = target;
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}
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return nia;
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1997-04-22 17:46:07 +00:00
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// Signed Integer Add - add source1, source2, dest
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1997-05-16 03:27:40 +00:00
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void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2
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unsigned32 result;
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ALU_BEGIN (source1);
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ALU_ADD (source2);
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ALU_END (result);
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*rDest = result;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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1997-04-23 13:56:14 +00:00
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/* FIXME - a signed add may cause an exception */
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31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
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1997-05-16 03:27:40 +00:00
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do_add (_SD, rDest, vSource1, vSource2);
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1997-04-22 17:46:07 +00:00
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31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
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1997-05-16 03:27:40 +00:00
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do_add (_SD, rDest, vSource1, vSource2);
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1997-04-22 17:46:07 +00:00
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31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
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1997-04-24 12:06:27 +00:00
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_add (_SD, rDest, LongSignedImmediate, vSource2);
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1997-04-22 17:46:07 +00:00
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// Unsigned Integer Add - addu source1, source2, dest
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1997-05-16 03:27:40 +00:00
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void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
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unsigned32 result = source1 + source2;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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1997-05-06 19:27:57 +00:00
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*rDest = result;
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
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1997-05-16 03:27:40 +00:00
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do_addu (_SD, rDest, vSource1, vSource2);
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1997-04-22 17:46:07 +00:00
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31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
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1997-05-16 03:27:40 +00:00
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do_addu (_SD, rDest, vSource1, vSource2);
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1997-04-22 17:46:07 +00:00
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31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
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1997-04-23 13:56:14 +00:00
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_addu (_SD, rDest, LongSignedImmediate, vSource2);
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1997-04-22 17:46:07 +00:00
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1997-05-16 03:27:40 +00:00
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void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2
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unsigned32 result = source1 & source2;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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1997-05-06 19:27:57 +00:00
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*rDest = result;
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1997-04-22 17:46:07 +00:00
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// and, and.tt
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1997-05-10 16:40:21 +00:00
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31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, vSource1, vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, vSource1, vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, LongSignedImmediate, vSource2);
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1997-04-22 17:46:07 +00:00
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// and.ff
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1997-05-10 16:40:21 +00:00
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31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~vSource1, ~vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~vSource1, ~vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
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1997-04-22 17:46:07 +00:00
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// and.ft
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1997-05-10 16:40:21 +00:00
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31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~vSource1, vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~vSource1, vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
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1997-04-22 17:46:07 +00:00
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// and.tf
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1997-05-10 16:40:21 +00:00
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31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, vSource1, ~vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, vSource1, ~vSource2);
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
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1997-04-22 17:46:07 +00:00
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// bbo.[a]
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1997-05-07 13:58:52 +00:00
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instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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1997-05-06 19:27:57 +00:00
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int jump_p;
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1997-05-13 13:57:49 +00:00
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address_word target = cia.ip + 4 * offset;
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1997-05-08 23:04:22 +00:00
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bitnum = (~ bitnum) & 0x1f;
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if (MASKED32 (source, bitnum, bitnum))
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1997-04-23 13:56:14 +00:00
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{
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1997-05-13 13:57:49 +00:00
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nia = do_branch (_SD, annul, target, 0, NULL);
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1997-05-06 19:27:57 +00:00
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jump_p = 1;
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1997-04-23 13:56:14 +00:00
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}
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1997-05-06 19:27:57 +00:00
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else
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jump_p = 0;
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1997-05-07 13:58:52 +00:00
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TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
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1997-04-23 13:56:14 +00:00
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return nia;
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31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
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1997-05-16 03:27:40 +00:00
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset);
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1997-04-23 13:56:14 +00:00
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31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
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1997-05-16 03:27:40 +00:00
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff);
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1997-04-23 13:56:14 +00:00
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31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
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1997-04-22 17:46:07 +00:00
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// bbz[.a]
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1997-05-07 13:58:52 +00:00
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instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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1997-05-06 19:27:57 +00:00
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int jump_p;
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1997-05-13 13:57:49 +00:00
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address_word target = cia.ip + 4 * offset;
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1997-05-08 23:04:22 +00:00
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bitnum = (~ bitnum) & 0x1f;
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if (!MASKED32 (source, bitnum, bitnum))
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1997-04-22 17:46:07 +00:00
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{
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1997-05-13 13:57:49 +00:00
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nia = do_branch (_SD, annul, target, 0, NULL);
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1997-05-06 19:27:57 +00:00
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jump_p = 1;
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1997-04-22 17:46:07 +00:00
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}
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1997-05-06 19:27:57 +00:00
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else
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jump_p = 0;
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1997-05-07 13:58:52 +00:00
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TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
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1997-04-22 17:46:07 +00:00
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return nia;
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1997-04-23 13:56:14 +00:00
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31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
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1997-05-16 03:27:40 +00:00
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset);
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1997-04-22 17:46:07 +00:00
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31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
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1997-05-16 03:27:40 +00:00
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff);
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1997-04-22 17:46:07 +00:00
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31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
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1997-04-23 13:56:14 +00:00
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
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1997-04-22 17:46:07 +00:00
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// bcnd[.a]
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1997-05-07 13:58:52 +00:00
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instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
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1997-04-23 13:56:14 +00:00
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int condition;
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int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
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int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
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signed32 val = 0;
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1997-05-13 13:57:49 +00:00
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address_word target = cia.ip + 4 * offset;
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1997-04-23 13:56:14 +00:00
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switch (size)
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{
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case 0: val = SEXT32 (source, 7); break;
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case 1: val = SEXT32 (source, 15); break;
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case 2: val = source; break;
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1997-05-19 03:42:33 +00:00
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default: sim_engine_abort (SD, CPU, cia, "bcnd - reserved size");
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1997-04-23 13:56:14 +00:00
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}
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switch (code)
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{
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case 0: condition = 0; break;
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case 1: condition = val > 0; break;
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case 2: condition = val == 0; break;
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case 3: condition = val >= 0; break;
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case 4: condition = val < 0; break;
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case 5: condition = val != 0; break;
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case 6: condition = val <= 0; break;
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default: condition = 1; break;
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}
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if (condition)
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{
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1997-05-13 13:57:49 +00:00
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nia = do_branch (_SD, annul, target, 0, NULL);
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1997-04-23 13:56:14 +00:00
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}
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1997-05-07 13:58:52 +00:00
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TRACE_COND_BR(MY_INDEX, condition, source, target);
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1997-04-23 13:56:14 +00:00
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return nia;
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31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
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1997-05-16 03:27:40 +00:00
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nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
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1997-04-23 13:56:14 +00:00
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31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
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1997-05-16 03:27:40 +00:00
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nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
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1997-04-23 13:56:14 +00:00
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31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
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long_immediate (LongSignedImmediate);
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1997-05-16 03:27:40 +00:00
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nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
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1997-04-22 17:46:07 +00:00
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// br[.a] - see bbz[.a]
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// brcr
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1997-05-07 13:58:52 +00:00
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sim_cia::function::do_brcr:instruction_address nia, int cr
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if (cr >= 0x4000 || !(CPU)->is_user_mode)
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{
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unsigned32 control = CR (cr);
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unsigned32 ie = control & 0x00000001;
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unsigned32 pc = control & 0xfffffffc;
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unsigned32 is_user_mode = control & 0x00000002;
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(CPU)->is_user_mode = is_user_mode;
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nia.dp = pc;
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if (ie)
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(CPU)->cr[IE_CR] |= IE_CR_IE;
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else
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(CPU)->cr[IE_CR] &= ~IE_CR_IE;
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}
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TRACE_UCOND_BR (MY_INDEX, nia.dp);
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return nia;
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31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
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nia = do_brcr (_SD, nia, UCRN);
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31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
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nia = do_brcr (_SD, nia, UCRN);
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1997-04-24 12:06:27 +00:00
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31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
|
1997-05-07 13:58:52 +00:00
|
|
|
long_immediate (UnsignedControlRegisterNumber)
|
|
|
|
nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// bsr[.a]
|
1997-05-07 13:58:52 +00:00
|
|
|
instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
|
1997-05-13 13:57:49 +00:00
|
|
|
address_word target = cia.ip + 4 * offset;
|
|
|
|
nia = do_branch (_SD, annul, target, 1, rLink);
|
|
|
|
TRACE_UCOND_BR (MY_INDEX, target);
|
1997-04-23 13:56:14 +00:00
|
|
|
return nia;
|
|
|
|
31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
|
1997-05-07 13:58:52 +00:00
|
|
|
nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
|
1997-05-07 13:58:52 +00:00
|
|
|
nia = do_bsr (_SD, nia, rLink, A, rIndOff);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-05-07 13:58:52 +00:00
|
|
|
nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// cmnd
|
1997-05-07 13:58:52 +00:00
|
|
|
void::function::do_cmnd:signed32 source
|
1997-05-05 12:46:25 +00:00
|
|
|
int Reset = EXTRACTED32 (source, 31, 31);
|
|
|
|
int Halt = EXTRACTED32 (source, 30, 30);
|
|
|
|
int Unhalt = EXTRACTED32 (source, 29, 29);
|
|
|
|
/* int ICR = EXTRACTED32 (source, 28, 28); */
|
|
|
|
/* int DCR = EXTRACTED32 (source, 27, 27); */
|
|
|
|
int Task = EXTRACTED32 (source, 14, 14);
|
|
|
|
int Msg = EXTRACTED32 (source, 13, 13);
|
|
|
|
int VC = EXTRACTED32 (source, 10, 10);
|
|
|
|
int TC = EXTRACTED32 (source, 9, 9);
|
|
|
|
int MP = EXTRACTED32 (source, 8, 8);
|
|
|
|
int PP = EXTRACTED32 (source, 3, 0);
|
|
|
|
/* what is implemented? */
|
|
|
|
if (PP != 0)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (VC != 0)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (TC != 0)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (MP)
|
|
|
|
{
|
|
|
|
if (Reset || Halt)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (Unhalt)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
/* if (ICR || DCR); */
|
|
|
|
if (Task)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (Msg)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
|
|
|
|
(unsigned long) cia.ip);
|
1997-05-05 12:46:25 +00:00
|
|
|
}
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_SINK1 (MY_INDEX, source);
|
1997-04-24 12:06:27 +00:00
|
|
|
31./,21.0b0000010,14.UI::::cmnd i
|
1997-05-07 13:58:52 +00:00
|
|
|
do_cmnd (_SD, UI);
|
1997-05-05 12:46:25 +00:00
|
|
|
31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_cmnd (_SD, vSource);
|
1997-04-24 12:06:27 +00:00
|
|
|
31./,21.0b110000010,12.1,11./::::cmnd l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (LongUnsignedImmediate);
|
1997-05-07 13:58:52 +00:00
|
|
|
do_cmnd (_SD, LongUnsignedImmediate);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
// cmp
|
1997-04-23 13:56:14 +00:00
|
|
|
unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
|
|
|
|
unsigned32 field = 0;
|
1997-05-09 19:48:52 +00:00
|
|
|
if (s1 == s2) field |= 0x001;
|
|
|
|
if (s1 != s2) field |= 0x002;
|
|
|
|
if (s1 > s2) field |= 0x004;
|
|
|
|
if (s1 <= s2) field |= 0x008;
|
|
|
|
if (s1 < s2) field |= 0x010;
|
|
|
|
if (s1 >= s2) field |= 0x020;
|
|
|
|
if (u1 > u2) field |= 0x040;
|
|
|
|
if (u1 <= u2) field |= 0x080;
|
|
|
|
if (u1 < u2) field |= 0x100;
|
|
|
|
if (u1 >= u2) field |= 0x200;
|
1997-04-23 13:56:14 +00:00
|
|
|
return field;
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
|
1997-04-23 13:56:14 +00:00
|
|
|
unsigned32 field = 0;
|
1997-05-16 03:27:40 +00:00
|
|
|
field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
|
|
|
|
field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
|
|
|
|
(signed16)source2, (unsigned16)source2) << 10;
|
|
|
|
field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
|
|
|
|
(signed8)source2, (unsigned8)source2);
|
|
|
|
TRACE_ALU3 (MY_INDEX, field, source1, source2);
|
1997-04-23 13:56:14 +00:00
|
|
|
*rDest = field;
|
|
|
|
31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_cmp (_SD, rDest, vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_cmp (_SD, rDest, vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// dcache
|
1997-04-23 13:56:14 +00:00
|
|
|
31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
|
1997-05-06 19:27:57 +00:00
|
|
|
TRACE_NOP (MY_INDEX);
|
1997-04-23 13:56:14 +00:00
|
|
|
/* NOP */
|
|
|
|
31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
|
1997-05-06 19:27:57 +00:00
|
|
|
TRACE_NOP (MY_INDEX);
|
1997-04-23 13:56:14 +00:00
|
|
|
/* NOP */
|
|
|
|
31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-04-30 08:41:47 +00:00
|
|
|
LongSignedImmediate++;
|
1997-05-06 19:27:57 +00:00
|
|
|
TRACE_NOP (MY_INDEX);
|
1997-04-23 13:56:14 +00:00
|
|
|
/* NOP */
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// dld[{.b|.h|.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
|
|
|
do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
|
1997-04-29 08:41:15 +00:00
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// dld.u[{.b|.h|.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
|
|
|
do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
|
1997-04-29 08:41:15 +00:00
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// dst[{.b|.h|.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
|
|
|
do_st (_SD, Source, base, rBase, m, sz, S, offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-29 08:41:15 +00:00
|
|
|
31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
|
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// estop
|
1997-04-24 12:06:27 +00:00
|
|
|
31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
// etrap
|
1997-04-24 12:06:27 +00:00
|
|
|
31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
|
|
|
|
31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
|
|
|
|
31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// exts - see shift.ds
|
|
|
|
|
|
|
|
|
|
|
|
// extu - see shift.dz
|
|
|
|
|
|
|
|
|
1997-05-05 12:46:25 +00:00
|
|
|
sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
|
|
|
|
switch (precision)
|
|
|
|
{
|
|
|
|
case 0: /* single */
|
1997-05-15 02:21:11 +00:00
|
|
|
return sim_fpu_32to (val);
|
1997-05-05 12:46:25 +00:00
|
|
|
case 1: /* double */
|
|
|
|
if (reg < 0)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "DP immediate invalid");
|
1997-05-05 12:46:25 +00:00
|
|
|
if (reg & 1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "DP FP register must be even");
|
1997-05-05 12:46:25 +00:00
|
|
|
if (reg <= 1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "DP FP register must be >= 2");
|
1997-05-16 03:27:40 +00:00
|
|
|
return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
|
|
|
|
| INSERTED64 (GPR (reg), 31, 0));
|
1997-05-05 12:46:25 +00:00
|
|
|
case 2: /* 32 bit signed integer */
|
1997-05-15 02:21:11 +00:00
|
|
|
return sim_fpu_i32to (val);
|
1997-05-05 12:46:25 +00:00
|
|
|
case 3: /* 32 bit unsigned integer */
|
1997-05-15 02:21:11 +00:00
|
|
|
return sim_fpu_u32to (val);
|
1997-05-05 12:46:25 +00:00
|
|
|
default:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
|
1997-05-05 12:46:25 +00:00
|
|
|
}
|
1997-05-15 02:21:11 +00:00
|
|
|
return sim_fpu_i32to (0);
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::set_fp_reg:int Dest, sim_fpu val, int PD
|
|
|
|
switch (PD)
|
|
|
|
{
|
|
|
|
case 0: /* single */
|
|
|
|
{
|
|
|
|
GPR (Dest) = sim_fpu_to32 (val);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 1: /* double */
|
|
|
|
{
|
1997-05-15 02:21:11 +00:00
|
|
|
unsigned64 v = sim_fpu_to64 (val);
|
1997-05-05 12:46:25 +00:00
|
|
|
if (Dest & 1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be even");
|
1997-05-05 12:46:25 +00:00
|
|
|
if (Dest <= 1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be >= 2");
|
1997-05-15 02:21:11 +00:00
|
|
|
GPR (Dest + 0) = VL4_8 (v);
|
|
|
|
GPR (Dest + 1) = VH4_8 (v);
|
1997-05-05 12:46:25 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: /* signed */
|
1997-05-15 16:39:38 +00:00
|
|
|
{
|
|
|
|
GPR (Dest) = sim_fpu_to32i (val);
|
|
|
|
break;
|
|
|
|
}
|
1997-05-05 12:46:25 +00:00
|
|
|
case 3: /* unsigned */
|
1997-05-15 16:39:38 +00:00
|
|
|
{
|
|
|
|
GPR (Dest) = sim_fpu_to32u (val);
|
|
|
|
break;
|
|
|
|
}
|
1997-05-05 12:46:25 +00:00
|
|
|
default:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
|
1997-05-05 12:46:25 +00:00
|
|
|
}
|
|
|
|
|
1997-04-22 17:46:07 +00:00
|
|
|
// fadd.{s|d}{s|d}{s|d}
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
|
|
|
sim_fpu ans = sim_fpu_add (s1, s2);
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_FPU3 (MY_INDEX, ans, s1, s2);
|
1997-05-05 12:46:25 +00:00
|
|
|
set_fp_reg (_SD, Dest, ans, PD);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_fadd (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source1, vSource1, P1),
|
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_fadd (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// fcmp.{s|d}{s|d}{s|d}
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
|
1997-05-15 02:21:11 +00:00
|
|
|
unsigned32 result = 0;
|
1997-05-05 12:46:25 +00:00
|
|
|
if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
|
1997-05-15 02:21:11 +00:00
|
|
|
result |= BIT32 (30);
|
1997-05-05 12:46:25 +00:00
|
|
|
else
|
|
|
|
{
|
1997-05-15 02:21:11 +00:00
|
|
|
result |= BIT32 (31);
|
|
|
|
if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20);
|
|
|
|
if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21);
|
|
|
|
if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22);
|
|
|
|
if (sim_fpu_is_le (s1, s2)) result |= BIT32(23);
|
|
|
|
if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24);
|
|
|
|
if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25);
|
|
|
|
if (sim_fpu_is_lt (s1, sim_fpu_i32to (0))
|
|
|
|
|| sim_fpu_is_gt (s1, s2)) result |= BIT32(26);
|
|
|
|
if (sim_fpu_is_lt (sim_fpu_i32to (0), s1)
|
|
|
|
&& sim_fpu_is_lt (s1, s2)) result |= BIT32(27);
|
|
|
|
if (sim_fpu_is_le (sim_fpu_i32to (0), s1)
|
|
|
|
&& sim_fpu_is_le (s1, s2)) result |= BIT32(28);
|
|
|
|
if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
|
|
|
|
|| sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
|
1997-05-05 12:46:25 +00:00
|
|
|
}
|
1997-05-16 03:27:40 +00:00
|
|
|
*rDest = result;
|
1997-05-15 02:21:11 +00:00
|
|
|
TRACE_FPU2I (MY_INDEX, result, s1, s2);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_fcmp (_SD, rDest,
|
|
|
|
get_fp_reg (_SD, Source1, vSource1, P1),
|
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_fcmp (_SD, rDest,
|
1997-05-05 12:46:25 +00:00
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-05 12:46:25 +00:00
|
|
|
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// fdiv.{s|d}{s|d}{s|d}
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
|
|
|
sim_fpu ans = sim_fpu_div (s1, s2);
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_FPU3 (MY_INDEX, ans, s1, s2);
|
1997-05-05 12:46:25 +00:00
|
|
|
set_fp_reg (_SD, Dest, ans, PD);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_fdiv (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source1, vSource1, P1),
|
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_fdiv (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
1997-05-15 16:39:38 +00:00
|
|
|
switch (PD)
|
|
|
|
{
|
|
|
|
case 2: /* signed */
|
|
|
|
{
|
|
|
|
GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
|
|
|
|
TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: /* unsigned */
|
|
|
|
{
|
|
|
|
GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
|
|
|
|
TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
{
|
|
|
|
sim_fpu ans = sim_fpu_mul (s1, s2);
|
|
|
|
set_fp_reg (_SD, Dest, ans, PD);
|
|
|
|
TRACE_FPU3 (MY_INDEX, ans, s1, s2);
|
|
|
|
}
|
|
|
|
}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_fmpy (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source1, vSource1, P1),
|
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_fmpy (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
|
|
|
set_fp_reg (_SD, Dest, s1, PD);
|
1997-05-15 02:21:11 +00:00
|
|
|
TRACE_FPU1 (MY_INDEX, s1);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_frnd (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source, vSource, P1));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_frnd (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_frnd (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source, vSource, P1));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_frnd (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_frnd (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source, vSource, P1));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_frnd (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_frnd (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source, vSource, P1));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_frnd (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// fsqrt.{s|d}{s|d}{s|d}
|
1997-04-23 13:56:14 +00:00
|
|
|
#void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
|
1997-04-22 17:46:07 +00:00
|
|
|
# sim_io_error ("fsqrt");
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
|
1997-05-16 03:27:40 +00:00
|
|
|
# do_fsqrt (_SD, rDest, vSource1, vSource2);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
|
1997-05-16 03:27:40 +00:00
|
|
|
# do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// fsub.{s|d}{s|d}{s|d}
|
1997-05-05 12:46:25 +00:00
|
|
|
void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
|
|
|
sim_fpu ans = sim_fpu_sub (s1, s2);
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_FPU3 (MY_INDEX, ans, s1, s2);
|
1997-05-05 12:46:25 +00:00
|
|
|
set_fp_reg (_SD, Dest, ans, PD);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
|
1997-05-05 12:46:25 +00:00
|
|
|
do_fsub (_SD, Dest, PD,
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source1, vSource1, P1),
|
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
|
1997-05-05 12:46:25 +00:00
|
|
|
long_immediate (SinglePrecisionFloatingPoint);
|
|
|
|
do_fsub (_SD, Dest, PD,
|
|
|
|
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
1997-05-16 03:27:40 +00:00
|
|
|
get_fp_reg (_SD, Source2, vSource2, P2));
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// illop
|
1997-04-24 12:06:27 +00:00
|
|
|
31./,21.0b0000000,14./::::illop
|
|
|
|
31./,21.0b111111111,12./::::illop l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// ins - see sl.im
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// jsr[.a]
|
1997-05-07 13:58:52 +00:00
|
|
|
instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
|
1997-05-13 13:57:49 +00:00
|
|
|
address_word target = offset + base;
|
|
|
|
TRACE_UCOND_BR (MY_INDEX, target);
|
|
|
|
nia = do_branch (_SD, annul, target, 1, rLink);
|
1997-04-29 08:41:15 +00:00
|
|
|
if (nia.dp & 0x3)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: destination address 0x%lx misaligned",
|
|
|
|
(unsigned long) cia.ip,
|
|
|
|
(unsigned long) nia.dp);
|
1997-04-23 13:56:14 +00:00
|
|
|
return nia;
|
|
|
|
31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
|
1997-05-16 03:27:40 +00:00
|
|
|
nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
|
1997-05-16 03:27:40 +00:00
|
|
|
nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// ld[{.b.h.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
1997-04-24 12:06:27 +00:00
|
|
|
unsigned32 addr;
|
|
|
|
switch (sz)
|
|
|
|
{
|
|
|
|
case 0:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 0) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
|
|
|
GPR(Dest) = MEM (signed, addr, 1);
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 1) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
|
|
|
GPR(Dest) = MEM (signed, addr, 2);
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 2) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
|
|
|
GPR(Dest) = MEM (signed, addr, 4);
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
1997-05-12 04:57:49 +00:00
|
|
|
{
|
|
|
|
signed64 val;
|
|
|
|
if (Dest & 0x1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
|
|
|
|
cia.ip, Dest);
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 3) : offset);
|
1997-05-12 04:57:49 +00:00
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
|
|
|
val = MEM (signed, addr, 8);
|
|
|
|
GPR(Dest + 1) = VH4_8 (val);
|
|
|
|
GPR(Dest + 0) = VL4_8 (val);
|
|
|
|
}
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
addr = -1;
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "ld - invalid sz %d", sz);
|
1997-04-24 12:06:27 +00:00
|
|
|
}
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
|
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// ld.u[{.b.h.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
1997-04-24 12:06:27 +00:00
|
|
|
unsigned32 addr;
|
|
|
|
switch (sz)
|
|
|
|
{
|
|
|
|
case 0:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 0) : offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
*rDest = MEM (unsigned, addr, 1);
|
|
|
|
break;
|
|
|
|
case 1:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 1) : offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
*rDest = MEM (unsigned, addr, 2);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
addr = -1;
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "ld.u - invalid sz %d", sz);
|
1997-04-24 12:06:27 +00:00
|
|
|
}
|
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_LD (MY_INDEX, m, S, *rDest, base, offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
|
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// lmo
|
1997-05-11 14:32:32 +00:00
|
|
|
31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
|
1997-05-07 13:58:52 +00:00
|
|
|
int b;
|
|
|
|
for (b = 0; b < 32; b++)
|
1997-05-16 03:27:40 +00:00
|
|
|
if (vSource & BIT32 (31 - b))
|
1997-05-07 13:58:52 +00:00
|
|
|
break;
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_ALU2 (MY_INDEX, b, vSource);
|
1997-05-07 13:58:52 +00:00
|
|
|
*rDest = b;
|
|
|
|
|
1997-04-22 17:46:07 +00:00
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// nop - see rdcr 0, r0
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
|
1997-05-06 19:27:57 +00:00
|
|
|
unsigned32 result = Source1 | Source2;
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
|
1997-05-06 19:27:57 +00:00
|
|
|
*rDest = result;
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// or, or.tt
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
|
|
|
|
long_immediate (LongUnsignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// or.ff
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~vSource1, ~vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~vSource1, ~vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
|
|
|
|
long_immediate (LongUnsignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// or.ft
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~vSource1, vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
|
|
|
|
long_immediate (LongUnsignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// or.tf
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, vSource1, ~vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, vSource1, ~vSource2);
|
1997-04-23 13:56:14 +00:00
|
|
|
31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
|
|
|
|
long_immediate (LongUnsignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// rdcr
|
1997-05-07 13:58:52 +00:00
|
|
|
void::function::do_rdcr:unsigned32 Dest, int cr
|
|
|
|
TRACE_SINK2 (MY_INDEX, Dest, cr);
|
|
|
|
GPR (Dest) = CR (cr);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
|
1997-05-07 13:58:52 +00:00
|
|
|
do_rdcr (_SD, Dest, UCRN);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
|
1997-05-07 13:58:52 +00:00
|
|
|
do_rdcr (_SD, Dest, UCRN);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
|
1997-04-29 08:41:15 +00:00
|
|
|
long_immediate (UnsignedControlRegisterNumber);
|
1997-05-07 13:58:52 +00:00
|
|
|
do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// rmo
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
|
1997-05-07 13:58:52 +00:00
|
|
|
int b;
|
|
|
|
for (b = 0; b < 32; b++)
|
1997-05-16 03:27:40 +00:00
|
|
|
if (vSource & BIT32 (b))
|
1997-05-07 13:58:52 +00:00
|
|
|
break;
|
|
|
|
if (b < 32)
|
|
|
|
b = 31 - b;
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_ALU2 (MY_INDEX, b, vSource);
|
1997-05-07 13:58:52 +00:00
|
|
|
*rDest = b;
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// rotl - see sl.dz
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
// rotr - see sl.dz
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// shl - see sl.iz
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// sl.{d|e|i}{m|s|z}
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
|
1997-04-30 08:41:47 +00:00
|
|
|
/* see 10-30 for a reasonable description */
|
1997-05-16 03:27:40 +00:00
|
|
|
unsigned32 input = source;
|
1997-04-30 08:41:47 +00:00
|
|
|
unsigned32 rotated;
|
|
|
|
unsigned32 endmask;
|
|
|
|
unsigned32 shiftmask;
|
|
|
|
unsigned32 cm;
|
|
|
|
int nRotate;
|
|
|
|
/* rotate the source */
|
|
|
|
if (n)
|
|
|
|
{
|
1997-05-16 03:27:40 +00:00
|
|
|
rotated = ROTR32 (source, Rotate);
|
1997-04-30 08:41:47 +00:00
|
|
|
nRotate = (- Rotate) & 31;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
1997-05-16 03:27:40 +00:00
|
|
|
rotated = ROTL32 (source, Rotate);
|
1997-04-30 08:41:47 +00:00
|
|
|
nRotate = Rotate;
|
|
|
|
}
|
|
|
|
/* form the end mask */
|
|
|
|
if (EndMask == 0)
|
1997-05-11 14:32:32 +00:00
|
|
|
endmask = ~ (unsigned32)0;
|
1997-04-30 08:41:47 +00:00
|
|
|
else
|
|
|
|
endmask = (1 << EndMask) - 1;
|
|
|
|
if (i)
|
|
|
|
endmask = ~endmask;
|
|
|
|
/* form the shiftmask */
|
|
|
|
switch (Merge)
|
|
|
|
{
|
|
|
|
case 0: case 1: case 2:
|
1997-05-11 14:32:32 +00:00
|
|
|
shiftmask = ~ (unsigned32)0; /* disabled */
|
1997-04-30 08:41:47 +00:00
|
|
|
break;
|
1997-05-15 16:39:38 +00:00
|
|
|
case 3: case 5: /* enabled - 0 -> 32 */
|
|
|
|
if (nRotate == 0)
|
|
|
|
shiftmask = ~ (unsigned32)0;
|
|
|
|
else
|
|
|
|
shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
|
1997-04-30 08:41:47 +00:00
|
|
|
break;
|
|
|
|
case 6: case 7:
|
1997-05-11 14:32:32 +00:00
|
|
|
shiftmask = ~((1 << nRotate) - 1); /* inverted */
|
1997-04-30 08:41:47 +00:00
|
|
|
break;
|
|
|
|
default:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: Invalid merge (%d) for shift",
|
|
|
|
cia.ip, source);
|
1997-04-30 08:41:47 +00:00
|
|
|
shiftmask = 0;
|
|
|
|
}
|
|
|
|
/* and the composite mask */
|
|
|
|
cm = shiftmask & endmask;
|
|
|
|
/* and merge */
|
|
|
|
switch (Merge)
|
|
|
|
{
|
1997-05-11 14:32:32 +00:00
|
|
|
case 0: case 3: case 6: /* zero */
|
1997-04-30 08:41:47 +00:00
|
|
|
GPR (Dest) = rotated & cm;
|
|
|
|
break;
|
1997-05-11 14:32:32 +00:00
|
|
|
case 1: case 4: case 7: /* merge */
|
1997-04-30 08:41:47 +00:00
|
|
|
GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
|
|
|
|
break;
|
1997-05-11 14:32:32 +00:00
|
|
|
case 2: case 5: /* sign */
|
1997-04-30 08:41:47 +00:00
|
|
|
{
|
|
|
|
int b;
|
|
|
|
GPR (Dest) = rotated & cm;
|
|
|
|
for (b = 1; b <= 31; b++)
|
|
|
|
if (!MASKED32 (cm, b, b))
|
|
|
|
GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
|
|
|
|
b, b);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: Invalid merge (%d)",
|
|
|
|
cia.ip, source);
|
1997-04-30 08:41:47 +00:00
|
|
|
|
|
|
|
}
|
1997-05-11 14:32:32 +00:00
|
|
|
TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
|
1997-04-30 08:41:47 +00:00
|
|
|
31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
|
1997-04-30 08:41:47 +00:00
|
|
|
31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
// sli.{d|e|i}{m|s|z} - see shift
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
// sr.{d|e|i}{m|s|z} - see shift
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
// sra - see sr.es - see shift
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-05-07 13:58:52 +00:00
|
|
|
// sri.{d|e|i}{m|s|z} - see shift
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// srl - see sr.ez
|
|
|
|
|
|
|
|
|
|
|
|
// st[{.b|.h|.d}]
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
1997-04-24 12:06:27 +00:00
|
|
|
unsigned32 addr;
|
|
|
|
switch (sz)
|
|
|
|
{
|
|
|
|
case 0:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 0) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
STORE (addr, 1, GPR(Source));
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 1) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
STORE (addr, 2, GPR(Source));
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 2) : offset);
|
1997-04-29 08:41:15 +00:00
|
|
|
STORE (addr, 4, GPR(Source));
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
case 3:
|
1997-05-12 04:57:49 +00:00
|
|
|
{
|
|
|
|
signed64 val;
|
|
|
|
if (Source & 0x1)
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: st.d with odd source register %d",
|
|
|
|
cia.ip, Source);
|
1997-05-16 03:27:40 +00:00
|
|
|
addr = base + (S ? (offset << 3) : offset);
|
1997-05-12 04:57:49 +00:00
|
|
|
val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
|
|
|
|
STORE (addr, 8, val);
|
|
|
|
}
|
1997-04-24 12:06:27 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
addr = -1;
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia, "st - invalid sz %d", sz);
|
1997-04-24 12:06:27 +00:00
|
|
|
}
|
|
|
|
if (m)
|
|
|
|
*rBase = addr;
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_ST (MY_INDEX, Source, m, S, base, offset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
|
|
|
|
long_immediate (LongSignedImmediateOffset);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// sub
|
1997-05-07 13:58:52 +00:00
|
|
|
void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
|
1997-04-24 12:06:27 +00:00
|
|
|
ALU_BEGIN (Source1);
|
|
|
|
ALU_SUB (Source2);
|
1997-05-06 19:27:57 +00:00
|
|
|
ALU_END (*rDest);
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_sub (_SD, rDest, vSource1, vSource2);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_sub (_SD, rDest, vSource1, vSource2);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_sub (_SD, rDest, LongSignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// subu
|
1997-05-11 14:32:32 +00:00
|
|
|
void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
|
1997-05-06 19:27:57 +00:00
|
|
|
unsigned32 result = Source1 - Source2;
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
|
1997-05-06 19:27:57 +00:00
|
|
|
*rDest = result;
|
1997-04-29 08:41:15 +00:00
|
|
|
// NOTE - the book has 15.1 which conflicts with subu.
|
1997-05-11 14:32:32 +00:00
|
|
|
31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_subu (_SD, rDest, vSource1, vSource2);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_subu (_SD, rDest, vSource1, vSource2);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
|
|
|
|
long_immediate (LongSignedImmediate);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_subu (_SD, rDest, LongSignedImmediate, vSource2);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// swcr
|
1997-05-16 03:27:40 +00:00
|
|
|
void::function::do_swcr:int Dest, signed32 source, signed32 cr
|
1997-05-07 13:58:52 +00:00
|
|
|
tic80_control_regs reg = tic80_index2cr (cr);
|
|
|
|
/* cache the old CR value */
|
|
|
|
unsigned32 old_cr = CR (cr);
|
|
|
|
/* Handle the write if allowed */
|
|
|
|
if (cr >= 0x4000 || !(CPU)->is_user_mode)
|
|
|
|
switch (reg)
|
|
|
|
{
|
|
|
|
case INTPEN_CR:
|
1997-05-16 03:27:40 +00:00
|
|
|
CR (cr) &= ~source;
|
1997-05-07 13:58:52 +00:00
|
|
|
break;
|
|
|
|
default:
|
1997-05-16 03:27:40 +00:00
|
|
|
CR (cr) = source;
|
1997-05-07 13:58:52 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Finish off the read */
|
|
|
|
GPR (Dest) = old_cr;
|
1997-05-16 03:27:40 +00:00
|
|
|
TRACE_SINK3 (MY_INDEX, source, cr, Dest);
|
1997-05-07 13:58:52 +00:00
|
|
|
31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
|
1997-05-16 03:27:40 +00:00
|
|
|
do_swcr (_SD, Dest, vSource, UCRN);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
|
1997-05-16 03:27:40 +00:00
|
|
|
do_swcr (_SD, Dest, vSource, UCRN);
|
1997-04-24 12:06:27 +00:00
|
|
|
31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
|
1997-05-07 13:58:52 +00:00
|
|
|
long_immediate (LongUnsignedControlRegister);
|
1997-05-16 03:27:40 +00:00
|
|
|
do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// trap
|
1997-05-07 13:58:52 +00:00
|
|
|
void::function::do_trap:unsigned32 trap_number
|
1997-05-13 22:04:32 +00:00
|
|
|
int i;
|
1997-05-07 13:58:52 +00:00
|
|
|
TRACE_SINK1 (MY_INDEX, trap_number);
|
1997-04-29 08:41:15 +00:00
|
|
|
switch (trap_number)
|
1997-04-22 17:46:07 +00:00
|
|
|
{
|
1997-04-29 08:41:15 +00:00
|
|
|
case 72:
|
|
|
|
switch (GPR(15))
|
1997-04-22 17:46:07 +00:00
|
|
|
{
|
|
|
|
case 1: /* EXIT */
|
|
|
|
{
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR(2));
|
1997-04-22 17:46:07 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 4: /* WRITE */
|
|
|
|
{
|
|
|
|
int i;
|
1997-05-05 12:46:25 +00:00
|
|
|
if (GPR(2) == 1)
|
|
|
|
for (i = 0; i < GPR(6); i++)
|
|
|
|
{
|
|
|
|
char c;
|
|
|
|
c = MEM (unsigned, GPR(4) + i, 1);
|
|
|
|
sim_io_write_stdout (SD, &c, 1);
|
|
|
|
}
|
|
|
|
else if (GPR(2) == 2)
|
|
|
|
for (i = 0; i < GPR(6); i++)
|
|
|
|
{
|
|
|
|
char c;
|
|
|
|
c = MEM (unsigned, GPR(4) + i, 1);
|
|
|
|
sim_io_write_stderr (SD, &c, 1);
|
|
|
|
}
|
|
|
|
else
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: write to invalid fid %d",
|
|
|
|
(unsigned long) cia.ip, GPR(2));
|
1997-04-29 08:41:15 +00:00
|
|
|
GPR(2) = GPR(6);
|
1997-04-22 17:46:07 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
1997-05-13 22:04:32 +00:00
|
|
|
/* For system calls which are defined, just return EINVAL instead of trapping */
|
|
|
|
if (GPR(15) <= 204)
|
|
|
|
{
|
|
|
|
GPR(2) = -22; /* -EINVAL */
|
|
|
|
break;
|
|
|
|
}
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: unknown syscall %d",
|
|
|
|
(unsigned long) cia.ip, GPR(15));
|
1997-04-22 17:46:07 +00:00
|
|
|
}
|
1997-04-29 08:41:15 +00:00
|
|
|
break;
|
1997-04-30 08:41:47 +00:00
|
|
|
case 73:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
|
1997-05-13 22:04:32 +00:00
|
|
|
|
|
|
|
/* Add a few traps for now to print the register state */
|
|
|
|
case 74:
|
|
|
|
case 75:
|
|
|
|
case 76:
|
|
|
|
case 77:
|
|
|
|
case 78:
|
|
|
|
case 79:
|
|
|
|
if (!TRACE_ALU_P (CPU))
|
|
|
|
trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
|
|
|
|
itable[MY_INDEX].line_nr, "trap",
|
1997-05-15 00:14:33 +00:00
|
|
|
"Trap %ld", (long) trap_number);
|
1997-05-13 22:04:32 +00:00
|
|
|
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
|
|
|
|
(((i+1) % 8) == 0) ? "\n" : "");
|
|
|
|
sim_io_write_stderr (SD, "\n", 1);
|
|
|
|
break;
|
|
|
|
|
1997-04-29 08:41:15 +00:00
|
|
|
default:
|
1997-05-19 03:42:33 +00:00
|
|
|
sim_engine_abort (SD, CPU, cia,
|
|
|
|
"0x%lx: unsupported trap %d",
|
|
|
|
(unsigned long) cia.ip, trap_number);
|
1997-04-22 17:46:07 +00:00
|
|
|
}
|
|
|
|
31./,27.0,26./,21.0b0000001,14.UTN::::trap i
|
1997-05-07 13:58:52 +00:00
|
|
|
do_trap (_SD, UTN);
|
1997-04-22 17:46:07 +00:00
|
|
|
31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
|
1997-05-07 13:58:52 +00:00
|
|
|
do_trap (_SD, UTN);
|
1997-04-22 17:46:07 +00:00
|
|
|
31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
|
|
|
|
long_immediate (UTN);
|
1997-05-07 13:58:52 +00:00
|
|
|
do_trap (_SD, UTN);
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vadd.{s|d}{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
|
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// vld{0|1}.{s|d} - see above - same instruction
|
1997-05-07 13:58:52 +00:00
|
|
|
#31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vmac.ss{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
|
|
|
|
31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
|
|
|
|
#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
|
|
|
|
31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vmpy.{s|d}{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
|
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vmsc.ss{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
|
|
|
|
31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
|
|
|
|
#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
|
|
|
|
31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vmsub.{s|d}{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
|
|
|
|
31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vrnd.{s|d}{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
|
|
|
|
31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
|
|
|
// vrnd.{i|u}{s|d}
|
1997-05-07 13:58:52 +00:00
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
|
|
|
|
31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
|
1997-04-22 17:46:07 +00:00
|
|
|
|
|
|
|
|
1997-04-24 12:06:27 +00:00
|
|
|
// vst.{s|d} - see above - same instruction
|
1997-05-07 13:58:52 +00:00
|
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#31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
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1997-04-22 17:46:07 +00:00
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// vsub.{i|u}{s|d}
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1997-05-07 13:58:52 +00:00
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31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
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31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
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1997-04-22 17:46:07 +00:00
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1997-04-24 12:06:27 +00:00
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// wrcr - see swcr, creg, source, r0
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1997-04-22 17:46:07 +00:00
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// xnor
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1997-05-16 03:27:40 +00:00
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void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
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unsigned32 result = ~ (source1 ^ source2);
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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1997-05-06 19:27:57 +00:00
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*rDest = result;
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1997-04-24 12:06:27 +00:00
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31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
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1997-05-16 03:27:40 +00:00
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do_xnor (_SD, rDest, vSource1, vSource2);
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1997-04-24 12:06:27 +00:00
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31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
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1997-05-16 03:27:40 +00:00
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do_xnor (_SD, rDest, vSource1, vSource2);
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1997-04-24 12:06:27 +00:00
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31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
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1997-04-23 13:56:14 +00:00
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long_immediate (LongUnsignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
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1997-04-22 17:46:07 +00:00
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// xor
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1997-05-16 03:27:40 +00:00
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void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
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unsigned32 result = source1 ^ source2;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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1997-05-06 19:27:57 +00:00
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*rDest = result;
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1997-04-23 13:56:14 +00:00
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31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
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1997-05-16 03:27:40 +00:00
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do_xor (_SD, rDest, vSource1, vSource2);
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1997-05-09 20:16:01 +00:00
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31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
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1997-05-16 03:27:40 +00:00
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do_xor (_SD, rDest, vSource1, vSource2);
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1997-05-09 20:16:01 +00:00
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31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
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1997-04-23 13:56:14 +00:00
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long_immediate (LongUnsignedImmediate);
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1997-05-16 03:27:40 +00:00
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do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);
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