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opcodes: blackfin: fix decoding of ABS

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The single cycle dual mac ABS insn was incorrectly decoding the mac1
part of the insn.

Once we fix the decode, update the gas tests to have the correct output.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-02-13 18:55:22 +00:00
parent 4db6639409
commit 13c02f06ff
5 changed files with 11 additions and 3 deletions
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4
gas/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* gas/bfin/arithmetic.d, gas/bfin/parallel.d: Change A0 to A1.
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* gas/bfin/arithmetic.d, gas/bfin/parallel.d, gas/bfin/parallel3.d,

2
gas/testsuite/gas/bfin/arithmetic.d
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@ -10,7 +10,7 @@ Disassembly of section .text:
4: 10 c4 [0-3][[:xdigit:]] 40 A0 = ABS A1;
8: 30 c4 [0-3][[:xdigit:]] 00 A1 = ABS A0;
c: 30 c4 [0-3][[:xdigit:]] 40 A1 = ABS A1;
10: 10 c4 [0-3][[:xdigit:]] c0 A1 = ABS A0, A0 = ABS A0;
10: 10 c4 [0-3][[:xdigit:]] c0 A1 = ABS A1, A0 = ABS A0;
14: 07 c4 10 80 R0 = ABS R2;
00000018 <add>:

2
gas/testsuite/gas/bfin/parallel.d
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@ -37,7 +37,7 @@ Disassembly of section .text:
74: fc b9 0a 9c
78: 30 cc 00 40 A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\];
7c: 77 91 93 9c
80: 10 cc 00 c0 A1 = ABS A0, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\];
80: 10 cc 00 c0 A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\];
84: ac a3 40 9d
88: 07 cc 10 80 R0 = ABS R2 \|\| B\[SP\] = R0 \|\| R1.H = W\[I1\+\+\];
8c: 30 9b 49 9c

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output

2
opcodes/bfin-dis.c
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@ -3476,7 +3476,7 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
OUTS (outf, " = (A0 += A1)");
}
else if (aop == 3 && HL == 0 && aopcde == 16)
OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
else if (aop == 0 && aopcde == 23 && HL == 1)
{