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Rewrite the mipsI/II/III pending-slot code.
This commit is contained in:
Andrew Cagney
parent
192ae475f9
commit
2acd126a47
@ -1,3 +1,15 @@
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Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (ColdReset): Call PENDING_INVALIDATE.
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* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
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* interp.c (pending_tick): New function. Deliver pending writes.
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* sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
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PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
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it can handle mixed sized quantites and single bits.
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Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (oengine.h): Do not include when building with IGEN.
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@ -1198,12 +1198,7 @@ ColdReset (SIM_DESC sd)
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/* Ensure that any instructions with pending register updates are
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cleared: */
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{
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int loop;
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for (loop = 0; (loop < PSLOTS); loop++)
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PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
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PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
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}
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PENDING_INVALIDATE();
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/* Initialise the FPU registers to the unknown state */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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@ -3308,73 +3303,8 @@ sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
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CANCELDELAYSLOT();
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}
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if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
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/* Deal with pending register updates: */
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#ifdef DEBUG
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printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
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#endif /* DEBUG */
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if (PENDING_OUT != PENDING_IN) {
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int loop;
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int index = PENDING_OUT;
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int total = PENDING_TOTAL;
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if (PENDING_TOTAL == 0) {
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fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
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exit(1);
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}
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for (loop = 0; (loop < total); loop++) {
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#ifdef DEBUG
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printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
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#endif /* DEBUG */
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if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
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#ifdef DEBUG
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printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
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#endif /* DEBUG */
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if (--(PENDING_SLOT_COUNT[index]) == 0) {
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#ifdef DEBUG
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printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
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printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
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#endif /* DEBUG */
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if (PENDING_SLOT_REG[index] == COCIDX)
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{
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
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}
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}
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else
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{
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REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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/* The only time we have PENDING updates to FPU
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registers, is when performing binary transfers. This
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means we should update the register type field. */
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if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
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FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
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}
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}
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#ifdef DEBUG
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printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
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#endif /* DEBUG */
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PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
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PENDING_OUT++;
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if (PENDING_OUT == PSLOTS)
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PENDING_OUT = 0;
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PENDING_TOTAL--;
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}
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}
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#ifdef DEBUG
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printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
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#endif /* DEBUG */
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index++;
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if (index == PSLOTS)
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index = 0;
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}
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}
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#ifdef DEBUG
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printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
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#endif /* DEBUG */
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}
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if (MIPSISA < 4)
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PENDING_TICK();
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#if !defined(FASTSIM)
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if (sim_events_tickn (sd, pipeline_count))
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@ -3448,5 +3378,72 @@ pr_uword64(addr)
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}
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void
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pending_tick (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia)
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{
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if (PENDING_TRACE)
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sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
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if (PENDING_OUT != PENDING_IN)
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{
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int loop;
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int index = PENDING_OUT;
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int total = PENDING_TOTAL;
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if (PENDING_TOTAL == 0)
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sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
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for (loop = 0; (loop < total); loop++)
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{
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if (PENDING_SLOT_DEST[index] != NULL)
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{
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PENDING_SLOT_DELAY[index] -= 1;
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if (PENDING_SLOT_DELAY[index] == 0)
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{
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if (PENDING_SLOT_BIT[index] >= 0)
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switch (PENDING_SLOT_SIZE[index])
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{
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case 32:
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if (PENDING_SLOT_VALUE[index])
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*(unsigned32*)PENDING_SLOT_DEST[index] |=
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BIT32 (PENDING_SLOT_BIT[index]);
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else
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*(unsigned32*)PENDING_SLOT_DEST[index] &=
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BIT32 (PENDING_SLOT_BIT[index]);
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break;
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case 64:
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if (PENDING_SLOT_VALUE[index])
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*(unsigned64*)PENDING_SLOT_DEST[index] |=
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BIT64 (PENDING_SLOT_BIT[index]);
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else
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*(unsigned64*)PENDING_SLOT_DEST[index] &=
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BIT64 (PENDING_SLOT_BIT[index]);
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break;
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break;
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}
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else
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switch (PENDING_SLOT_SIZE[index])
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{
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case 32:
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*(unsigned32*)PENDING_SLOT_DEST[index] =
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PENDING_SLOT_VALUE[index];
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break;
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case 64:
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*(unsigned64*)PENDING_SLOT_DEST[index] =
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PENDING_SLOT_VALUE[index];
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break;
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}
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}
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if (PENDING_OUT == index)
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{
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PENDING_SLOT_DEST[index] = NULL;
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PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
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PENDING_TOTAL--;
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}
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}
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}
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index = (index + 1) % PSLOTS;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*> EOF interp.c <*/
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@ -285,6 +285,81 @@ GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
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/* The following is probably not used for MIPS IV onwards: */
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/* Slots for delayed register updates. For the moment we just have a
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fixed number of slots (rather than a more generic, dynamic
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system). This keeps the simulator fast. However, we only allow
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for the register update to be delayed for a single instruction
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cycle. */
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#define PSLOTS (8) /* Maximum number of instruction cycles */
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typedef struct _pending_write_queue {
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int in;
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int out;
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int total;
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int slot_delay[PSLOTS];
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int slot_size[PSLOTS];
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int slot_bit[PSLOTS];
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void *slot_dest[PSLOTS];
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unsigned64 slot_value[PSLOTS];
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} pending_write_queue;
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#ifndef PENDING_TRACE
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#define PENDING_TRACE 0
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#endif
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#define PENDING_IN ((CPU)->pending.in)
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#define PENDING_OUT ((CPU)->pending.out)
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#define PENDING_TOTAL ((CPU)->pending.total)
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#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
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#define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
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#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
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#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
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#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
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/* Invalidate the pending write queue, all pending writes are
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discarded. */
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#define PENDING_INVALIDATE() \
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memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
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/* Schedule a write to DEST for N cycles time. For 64 bit
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destinations, schedule two writes. For floating point registers,
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the caller should schedule a write to both the dest register and
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the FPR_STATE register. When BIT is non-negative, only BIT of DEST
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is updated. */
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#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
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do { \
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if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
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sim_engine_abort (SD, CPU, cia, \
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"PENDING_SCHED - buffer overflow\n"); \
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if (PENDING_TRACE) \
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sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
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PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
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PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
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PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
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PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
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PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
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} while (0)
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#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
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#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
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#define PENDING_TICK() pending_tick (SD, CPU, cia)
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#define PENDING_FLUSH() abort () /* think about this one */
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#define PENDING_FP() abort () /* think about this one */
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/* For backward compatibility */
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#define PENDING_FILL(R,VAL) \
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{ \
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if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
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PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1); \
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else \
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PENDING_SCHED(GPR[(R)], VAL, 2, -1); \
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}
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struct _sim_cpu {
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@ -337,6 +412,8 @@ struct _sim_cpu {
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#define ENGINE_ISSUE_PREFIX_HOOK() \
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{ \
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/* Perform any pending writes */ \
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PENDING_TICK(); \
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/* Set previous flag, depending on current: */ \
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if (STATE & simPCOC0) \
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STATE |= simPCOC1; \
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@ -376,6 +453,7 @@ struct _sim_cpu {
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#define GPR (®ISTERS[0])
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#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
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#define NR_FGR (32)
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#define FGRIDX (38)
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#define FGR (®ISTERS[FGRIDX])
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#define LO (REGISTERS[33])
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@ -412,42 +490,7 @@ struct _sim_cpu {
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FP_formats fpr_state[32];
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#define FPR_STATE ((CPU)->fpr_state)
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/* Slots for delayed register updates. For the moment we just have a
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fixed number of slots (rather than a more generic, dynamic
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system). This keeps the simulator fast. However, we only allow
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for the register update to be delayed for a single instruction
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cycle. */
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#define PSLOTS (5) /* Maximum number of instruction cycles */
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int pending_in;
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int pending_out;
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int pending_total;
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int pending_slot_count[PSLOTS];
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int pending_slot_reg[PSLOTS];
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unsigned_word pending_slot_value[PSLOTS];
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#define PENDING_IN ((CPU)->pending_in)
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#define PENDING_OUT ((CPU)->pending_out)
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#define PENDING_TOTAL ((CPU)->pending_total)
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#define PENDING_SLOT_COUNT ((CPU)->pending_slot_count)
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#define PENDING_SLOT_REG ((CPU)->pending_slot_reg)
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#define PENDING_SLOT_VALUE ((CPU)->pending_slot_value)
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/* The following are not used for MIPS IV onwards: */
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#define PENDING_FILL(r,v) {\
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/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
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if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
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sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
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PENDING_SLOT_COUNT[PENDING_IN] = 2;\
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PENDING_SLOT_REG[PENDING_IN] = (r);\
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PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
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/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
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PENDING_TOTAL++;\
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PENDING_IN++;\
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if (PENDING_IN == PSLOTS)\
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PENDING_IN = 0;\
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/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
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}
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pending_write_queue pending;
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/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
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read-write instructions. It is set when a linked load occurs. It
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@ -737,4 +780,6 @@ unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, addres
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void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
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FILE *tracefh;
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void pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
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#endif
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