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144 Commits

Author SHA1 Message Date
Ben Elliston
45fdcabea2 2003-01-10 Ben Elliston <bje@redhat.com> 
* README.Cygnus: Rename from this ..
	* README: .. to this.
 2003-01-10 05:27:17 +00:00
Ben Elliston
7f53bce4e3 * remove duplicated entry from 2002-05-17 on 2002-05-20. 
* s/SWI_TARGET_SWITCHES/SIM_TARGET_SWITCHES/.
 2003-01-10 04:51:58 +00:00
Andrew Cagney
058f270dea Add support for -m option. Fix PR gdb/433. 2002-09-27 23:57:50 +00:00
Nick Clifton
2ec3c90a77 oops - fix typo in previous delta 2002-08-16 09:38:09 +00:00
Nick Clifton
c7a7b500fd Catch and ignore SWIs of -1, they can be caused by an interrupted system 
call being resumed by GDB.
 2002-08-15 14:28:55 +00:00
Nick Clifton
630ace253a Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions. 2002-07-05 14:12:01 +00:00
Nick Clifton
7b77dec665 Set correct value for ADP_Stopped_RunTimeError 2002-06-21 06:58:36 +00:00
Andrew Cagney
c8cca39f98 Import current --enable-gdb-build-warnings. 2002-06-16 16:33:35 +00:00
Andrew Cagney
26216b9822 Add the file include/gdb/sim-arm.h defining an enum that specifies the 
register numbering used by the GDB<->SIM interface.
 2002-06-12 21:19:43 +00:00
Andrew Cagney
3c25f8c7b0 Move include/callback.h and include/remote-sim.h to include/gdb/. 
Update accordingly.
 2002-06-09 15:45:54 +00:00
Nick Clifton
5aa682b2e0 Set the FSR and FAR registers if a Data Abort is detected. 2002-05-29 19:01:36 +00:00
Nick Clifton
10b57fcbd7 Only perform access checks if 'check' is set. 
Report unknown machine numbers.
Formatting tidy ups.
 2002-05-27 14:12:00 +00:00
Nick Clifton
7378e198a5 Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced. 2002-05-27 13:30:36 +00:00
Nick Clifton
2984e11475 When decoding a BLX(1) instruction do not add in the second bit of the base 
address - this has already been accounted for.
 2002-05-23 12:38:31 +00:00
Nick Clifton
8b2440b731 Simulate XScale BCUMOD register 2002-05-21 20:28:26 +00:00
Nick Clifton
de4112fa38 Add support for target specific command line switches to old-style simualtors. 
Make use of this support in the ARM simulator to add a --swi-support= switch
to select whcih SWI protocols to emulate.
 2002-05-20 14:32:50 +00:00
Nick Clifton
ace4f296f5 Uses sim callback interface for system calls in RedBoot SWI support. 2002-05-09 10:29:08 +00:00
Nick Clifton
d8512e6afd Support the RedBoot SWI in ARM mode and some of its system calls. 2002-05-09 10:14:12 +00:00
Anthony Green
ae60d3ddec Increase default memory size to 8MB. 2002-03-18 21:43:15 +00:00
Keith Seitz
b3ba81f8ee * armos.c (SWIWrite0): Use generic host_callback mechanism 
for supported OS functions "open", "close", "write", etc.
	(SWIopen): Likewise.
	(SWIread): Likewise.
	(SWIwrite): Likewise.
	(SWIflen): Likewise.
	(ARMul_OSHandleSWI): Likewise.
 2002-02-21 20:22:49 +00:00
Nick Clifton
c17aa31873 Modify previous patch so that it is only triggered for COFF format executables. 2002-02-05 11:22:26 +00:00
Nick Clifton
25180f8aef If a v5 architecture is detected, assume it might be an XScale binary, since 
there is no way to distinguish between    the two in the COFF file format.
 2002-02-04 16:27:22 +00:00
Nick Clifton
57165fb4bb Fix parameters passed to CPRead[13] and CPRead[14]. 2002-01-10 11:14:57 +00:00
Nick Clifton
86c735a526 General format tidy ups 2002-01-09 15:08:21 +00:00
Nick Clifton
272fcdcd59 Fix bug detected by GDB testsuite - when fetching registers more than 4 
bytes wide return 0 for the other bytes.
 2002-01-09 14:59:22 +00:00
Ben Harris
6746a76a70 2001-11-16 Ben Harris <bjh21@netbsd.org> 
* Makefile.in (armemu32.o): Replace $< with autoconf recommended
	$(srcdir)/....
	(armemu26.o): Ditto.
 2001-11-16 18:56:01 +00:00
Nick Clifton
ff44f8e352 Add support for XScale's coprocessor access check register. 
Fix formatting.
 2001-10-18 12:20:49 +00:00
Nick Clifton
fb7a8ef0df Fix handling of XScale LDRD and STRD instructions with post indexed addressing modes. 2001-05-11 21:51:07 +00:00
Nick Clifton
dac07255f9 Check Mode not Bank in order to determine rocesor mode. 2001-05-08 08:28:28 +00:00
Matthew Green
c3ae2f98d0 * XScale coprocessor support. 
2001-04-18  matthew green  <mrg@redhat.com>

	* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
	(read_cp15_reg): Make non-static.
	(XScale_cp15_LDC): Update for write_cp15_reg() change.
	(XScale_cp15_MCR): Likewise.
	(XScale_cp15_write_reg): Likewise.
	(XScale_check_memacc): New function. Check for breakpoints being
	activated by memory accesses.  Does not support the Branch Target
	Buffer.
	(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
	(XScale_debug_moe): New function. Set the debug Method Of Entry,
	if configured.
	(write_cp14_reg): Reset count counter if requested.
	* armdefs.h (struct ARMul_State): New members `LastTime' and
	`CP14R0_CCD' used for the timer/counters.
	(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
	ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
	ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
	ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
	ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
	ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
	ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
	ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
	defines for XScale registers.
	(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
	(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
	(ARMul_Emulate32): Handle the clock counter and hardware instruction
	breakpoints.  Call XScale_set_fsr_far() for software breakpoints and
	software interrupts.
	(LoadMult): Call XScale_set_fsr_far() for data aborts.
	(LoadSMult): Likewise.
	(StoreMult): Likewise.
	(StoreSMult): Likewise.
	* armemu.h (write_cp15_reg): Update prototype.
	* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
	(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
	register 0.
	* armvirt.c (GetWord): Call XScale_check_memacc().
	(PutWord): Likewise.
 2001-04-18 16:39:37 +00:00
Nick Clifton
3cf84db9ef Do not enable alignment checking when loading unaligned thumb instructions. 2001-03-20 17:48:02 +00:00
Nick Clifton
4f3c3dbb37 Fix BLX(1) for Thumb 2001-03-06 22:33:47 +00:00
Nick Clifton
917bca4f21 Add support for disabling alignment checks when performing GDB interface 
calls or SWI emulaiton routines.  (Alignment checking code has not yet been
contributed).
 2001-02-28 01:04:24 +00:00
Nick Clifton
2ef048fc9f Remove Prefetch abort for breakpoints. Instead set the state to RESUME. 2001-02-16 22:04:22 +00:00
Nick Clifton
44e23e575b Add code to preserve processor mode when a prefetch 
abort is signalled after processing a breakpoint.
 2001-02-15 02:38:15 +00:00
Nick Clifton
5f7d0a33db Reset processor into ARM mode for any machine type except the early ARMs. 2001-02-14 22:21:20 +00:00
Nick Clifton
94ab9d7b9e remove spurious whitespace 2001-02-14 03:55:57 +00:00
Nick Clifton
1e5d4e465c Prevent Aborts from happening whilst emulating a SWI 2001-02-14 03:50:46 +00:00
Nick Clifton
179ae6ea64 Fix definition of NEGBRANCH 2001-02-12 23:29:49 +00:00
Nick Clifton
fae0bf59e6 Add parentheses ready for future conbtribution 2001-02-01 20:56:35 +00:00
Nick Clifton
dda308f5fd Update base address register after restoring register bank. 2001-02-01 20:39:51 +00:00
Nick Clifton
88694af3f9 Detect installation of SWI vector by running program as well as loading program. 2001-02-01 00:14:40 +00:00
Nick Clifton
ac1c9d3aad Fix test for StoreDouble Instruction. 2000-12-19 00:58:04 +00:00
Nick Clifton
9a6b6a66b7 Add 0x91 as an FPE SWI. 2000-12-11 03:08:17 +00:00
Nick Clifton
df38a86eec oops - remove redundant prototype introduced in previous delta 2000-12-08 01:39:48 +00:00
Nick Clifton
760a7bbec5 Add emulation of double word load and store instructions. 2000-12-08 01:38:47 +00:00
Nick Clifton
7f53bc3526 Suppress support of DEMON swi's in XScale mode. 2000-12-03 23:28:46 +00:00
Nick Clifton
f1129fb8ff Add support for ARM's v5TE architecture and Intel's XScale extenstions 2000-11-30 01:55:12 +00:00
Nick Clifton
3943c96b07 Replace StrongARM property with v4 and v5 properties. 2000-09-15 23:55:50 +00:00
Nick Clifton
4bc1de7b2d Compute write back value for post increment loads before 
performing the load in case the offset register is overwritten.
 2000-08-15 00:10:52 +00:00