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https://github.com/freebsd/freebsd-src.git
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e1000: Separate DH89xxCC memory errors
DH89xxCC shares the 82580 MAC type but reserves several of its memory
error control and status registers. Accessing the full 82580 register
set breaks normal RX/TX operation on affected adapters.
Give DH89xxCC separate configuration, accounting, and recovery paths.
Use its transmit packet-buffer ECC counter and DMA/LAN parity status
with device-specific masks, avoiding the reserved receive-buffer ECC
and PCIe error registers. Retain the port-reset sequence for fatal
memory-error recovery without waiting for the absent STATUS.RST_DONE.
Tested by: chuck2k (https://github.com/opnsense/src/issues/329)
Fixes: 915c628c4f ("igb: Report 82580 memory ECC errors")
MFC after: 1 day
Sponsored by: BBOX.io
Differential Revision: https://reviews.freebsd.org/D61138
This commit is contained in:
Kevin Bowling committed
1 parent
ba855bc358
commit
0857b57787
2 files changed
+153
-17
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@@ -535,7 +535,7 @@
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#define E1000_ECC_82575_UNCORR_CNT_SHIFT 8
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#define E1000_ECC_82575_ENABLE 0x00010000
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/* I350, I354, and I210/I211 memory error status bits. */
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/* 82580, DH89xxCC, I350, I354, and I210/I211 memory error status bits. */
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#define E1000_PEIND_LANPORT_PARITY_FATAL 0x00000001
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#define E1000_PEIND_MNG_PARITY_FATAL 0x00000002
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#define E1000_PEIND_PCIE_PARITY_FATAL 0x00000004
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@@ -555,6 +555,14 @@
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#define E1000_PBECCSTS_82580_ECC_ENABLE 0x00010000
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#define E1000_PBECCSTS_82580_CORR_CNT_MASK 0x000000FF
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/* DH89xxCC implements only the transmit packet-buffer ECC counter. */
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#define E1000_TPBECCSTS_DH89XXCC_ECC_ENABLE 0x00010000
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#define E1000_TPBECCSTS_DH89XXCC_CORR_CNT_MASK 0x000000FF
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#define E1000_DTPARS_DH89XXCC_ERROR_MASK 0x0000007F
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#define E1000_DRPARS_DH89XXCC_ERROR_MASK 0x0000000F
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#define E1000_DDPARS_DH89XXCC_ERROR_MASK 0x0000000F
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#define E1000_LANPERRSTS_DH89XXCC_ERROR_MASK 0x00007FFF
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/* 82576 uses PEIND directly rather than the later four-region layout. */
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#define E1000_PEIND_82576_NONFATAL_MASK 0x00000007
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#define E1000_PEIND_82576_FATAL_MASK 0x7FFFFF00
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+144
-16
@@ -469,8 +469,10 @@ static void em_finish_fatal_error_reset(struct e1000_softc *);
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static void em_configure_peind_memory_errors(struct e1000_softc *);
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static void em_configure_82575_memory_errors(struct e1000_softc *);
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static void em_configure_82580_memory_errors(struct e1000_softc *);
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static void em_configure_dh89xxcc_memory_errors(struct e1000_softc *);
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static void em_update_82580_ecc_stats(struct e1000_softc *, u32, u32,
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u32);
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static void em_update_dh89xxcc_ecc_stats(struct e1000_softc *);
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static void em_if_multi_set(if_ctx_t);
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static void em_if_update_admin_status(if_ctx_t);
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static void em_if_debug(if_ctx_t);
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@@ -2096,6 +2098,7 @@ em_if_init(if_ctx_t ctx)
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em_configure_peind_memory_errors(sc);
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em_configure_82575_memory_errors(sc);
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em_configure_82580_memory_errors(sc);
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em_configure_dh89xxcc_memory_errors(sc);
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if (sc->vf_ifp) {
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sc->vf_reset_pending = false;
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} else {
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@@ -2382,19 +2385,37 @@ em_configure_82576_memory_errors(struct e1000_softc *sc)
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E1000_WRITE_FLUSH(hw);
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}
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static bool
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em_has_dh89xxcc_memory_errors(const struct e1000_hw *hw)
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{
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if (hw->mac.type != e1000_82580)
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return (false);
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switch (hw->device_id) {
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case E1000_DEV_ID_DH89XXCC_SGMII:
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case E1000_DEV_ID_DH89XXCC_SERDES:
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case E1000_DEV_ID_DH89XXCC_BACKPLANE:
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case E1000_DEV_ID_DH89XXCC_SFP:
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return (true);
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default:
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return (false);
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}
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}
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static bool
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em_has_82580_memory_errors(const struct e1000_hw *hw)
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{
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return (hw->mac.type == e1000_82580);
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return (hw->mac.type == e1000_82580 &&
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!em_has_dh89xxcc_memory_errors(hw));
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}
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static void
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em_clear_82580_memory_error_status(struct e1000_hw *hw, u32 reg)
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em_clear_memory_error_status(struct e1000_hw *hw, u32 reg, u32 mask)
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{
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u32 status;
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status = E1000_READ_REG(hw, reg);
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status = E1000_READ_REG(hw, reg) & mask;
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if (status != 0)
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E1000_WRITE_REG(hw, reg, status);
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}
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@@ -2411,10 +2432,10 @@ em_configure_82580_memory_errors(struct e1000_softc *sc)
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/* Clear status left before the driver completed its memory tables. */
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(void)E1000_READ_REG(hw, E1000_PEIND);
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em_clear_82580_memory_error_status(hw, E1000_DTPARS_82580);
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em_clear_82580_memory_error_status(hw, E1000_DRPARS_82580);
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em_clear_82580_memory_error_status(hw, E1000_DDPARS_82580);
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em_clear_82580_memory_error_status(hw, E1000_PCIEERRSTS);
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em_clear_memory_error_status(hw, E1000_DTPARS_82580, ~0U);
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em_clear_memory_error_status(hw, E1000_DRPARS_82580, ~0U);
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em_clear_memory_error_status(hw, E1000_DDPARS_82580, ~0U);
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em_clear_memory_error_status(hw, E1000_PCIEERRSTS, ~0U);
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(void)E1000_READ_REG(hw, E1000_LANPERRSTS);
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em_update_82580_ecc_stats(sc,
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E1000_READ_REG(hw, E1000_RPBECCSTS),
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@@ -2452,6 +2473,43 @@ em_configure_82580_memory_errors(struct e1000_softc *sc)
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E1000_WRITE_FLUSH(hw);
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}
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static void
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em_clear_dh89xxcc_parity_status(struct e1000_hw *hw)
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{
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em_clear_memory_error_status(hw, E1000_DTPARS_82580,
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E1000_DTPARS_DH89XXCC_ERROR_MASK);
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em_clear_memory_error_status(hw, E1000_DRPARS_82580,
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E1000_DRPARS_DH89XXCC_ERROR_MASK);
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em_clear_memory_error_status(hw, E1000_DDPARS_82580,
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E1000_DDPARS_DH89XXCC_ERROR_MASK);
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}
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static void
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em_configure_dh89xxcc_memory_errors(struct e1000_softc *sc)
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{
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struct e1000_hw *hw;
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hw = &sc->hw;
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if (!em_has_dh89xxcc_memory_errors(hw))
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return;
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/*
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* Intel 89xx datasheet, section 28.22: the DMA parity status layout
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* matches 82580, but its parity controls, receive-buffer ECC and PCIe
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* error registers are reserved. LANPERRCTL only controls management
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* flex filters whose memories are not initialized by this driver.
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*/
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em_clear_dh89xxcc_parity_status(hw);
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(void)E1000_READ_REG(hw, E1000_PEIND);
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em_update_dh89xxcc_ecc_stats(sc);
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E1000_WRITE_REG(hw, E1000_TPBECCSTS,
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E1000_TPBECCSTS_DH89XXCC_ECC_ENABLE);
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/* All other PEINDM bits are reserved; do not preserve read values. */
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E1000_WRITE_REG(hw, E1000_PEINDM, E1000_PEIND_FATAL_MASK);
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E1000_WRITE_FLUSH(hw);
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}
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static bool
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em_has_i210_memory_errors(const struct e1000_hw *hw)
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{
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@@ -2493,6 +2551,7 @@ em_has_peind_memory_errors(const struct e1000_hw *hw)
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{
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return (em_has_82580_memory_errors(hw) ||
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em_has_dh89xxcc_memory_errors(hw) ||
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em_has_i350_i354_memory_errors(hw) ||
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em_has_i210_memory_errors(hw));
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}
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@@ -2563,6 +2622,15 @@ em_update_82580_ecc_stats(struct e1000_softc *sc, u32 rpbeccsts,
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E1000_WRITE_REG(&sc->hw, E1000_PCIEECCSTS, status);
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}
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static void
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em_update_dh89xxcc_ecc_stats(struct e1000_softc *sc)
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{
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sc->corrected_error_packet_buffer_count +=
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E1000_READ_REG(&sc->hw, E1000_TPBECCSTS) &
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E1000_TPBECCSTS_DH89XXCC_CORR_CNT_MASK;
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}
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static void
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em_update_82575_ecc_stats(struct e1000_softc *sc, u32 pbeccsts,
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u32 rdhests, u32 tdhests)
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@@ -2788,6 +2856,27 @@ em_handle_fatal_error_intr(struct e1000_softc *sc, u32 icr)
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E1000_READ_REG(hw, E1000_TDHESTS_82575);
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} else if (em_has_82576_memory_errors(hw)) {
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sc->fatal_error_peind = E1000_READ_REG(hw, E1000_PEIND);
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} else if (em_has_dh89xxcc_memory_errors(hw)) {
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/* PCIe and management errors have no subordinate status CSR. */
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peind = E1000_READ_REG(hw, E1000_PEIND) &
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E1000_PEIND_FATAL_MASK;
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dma_tx = E1000_READ_REG(hw, E1000_DTPARS_82580) &
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E1000_DTPARS_DH89XXCC_ERROR_MASK;
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dma_rx = E1000_READ_REG(hw, E1000_DRPARS_82580) &
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E1000_DRPARS_DH89XXCC_ERROR_MASK;
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dma_host = E1000_READ_REG(hw, E1000_DDPARS_82580) &
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E1000_DDPARS_DH89XXCC_ERROR_MASK;
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lanerr = E1000_READ_REG(hw, E1000_LANPERRSTS) &
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E1000_LANPERRSTS_DH89XXCC_ERROR_MASK;
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if (dma_tx != 0 || dma_rx != 0 || dma_host != 0)
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peind |= E1000_PEIND_DMA_PARITY_FATAL;
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if (lanerr != 0)
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peind |= E1000_PEIND_LANPORT_PARITY_FATAL;
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sc->fatal_error_peind = peind;
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sc->fatal_error_dma_tx = dma_tx;
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sc->fatal_error_dma_rx = dma_rx;
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sc->fatal_error_dma_host = dma_host;
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sc->fatal_error_lan = lanerr;
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} else {
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peind = E1000_READ_REG(hw, E1000_PEIND) &
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E1000_PEIND_FATAL_MASK;
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@@ -2906,7 +2995,9 @@ em_handle_fatal_error_admin(struct e1000_softc *sc)
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E1000_READ_REG(&sc->hw, E1000_RPBECCSTS),
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E1000_READ_REG(&sc->hw, E1000_TPBECCSTS),
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pcieecc);
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} else if (em_has_i350_i354_memory_errors(&sc->hw))
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} else if (em_has_dh89xxcc_memory_errors(&sc->hw))
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em_update_dh89xxcc_ecc_stats(sc);
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else if (em_has_i350_i354_memory_errors(&sc->hw))
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em_update_i350_i354_ecc_stats(sc);
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if (peind & E1000_PEIND_LANPORT_PARITY_FATAL)
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sc->fatal_error_lan_count++;
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@@ -2930,6 +3021,15 @@ em_handle_fatal_error_admin(struct e1000_softc *sc)
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sc->fatal_error_dma_rx,
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sc->fatal_error_dma_host,
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sc->fatal_error_lan);
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} else if (em_has_dh89xxcc_memory_errors(&sc->hw)) {
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device_printf(sc->dev,
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"fatal internal memory error: PEIND %#x, "
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"DTPARS %#x, DRPARS %#x, DDPARS %#x, "
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"LANPERRSTS %#x\n", peind,
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sc->fatal_error_dma_tx,
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sc->fatal_error_dma_rx,
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sc->fatal_error_dma_host,
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sc->fatal_error_lan);
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} else {
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device_printf(sc->dev,
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"fatal internal memory error: PEIND %#x, "
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@@ -3186,6 +3286,8 @@ igb_finish_device_reset(struct e1000_softc *sc, u32 icr)
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* 82580 stops PCIe traffic for a fatal error in any host-owned region, so use
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* the same order for every 82580 recovery. This differs from the normal
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* reset path, which disables the bus master first.
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* DH89xxCC uses the same port-reset sequence without the 82580 PCIe status
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* registers. Like 82580, it has no STATUS.RST_DONE bit.
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*
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* Indications that relatch after admin accounting are discarded during
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* reset; sticky bits cannot distinguish them from the saved event.
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@@ -3203,11 +3305,13 @@ em_prepare_fatal_error_reset(struct e1000_softc *sc)
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EM_FATAL_ERROR_RESET_REQUESTED)
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return;
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pcieerr = sc->fatal_error_pcie |
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(E1000_READ_REG(&sc->hw, E1000_PCIEERRSTS) &
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em_pcie_fatal_error_mask(&sc->hw));
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pcieerr = sc->fatal_error_pcie;
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if (!em_has_dh89xxcc_memory_errors(&sc->hw))
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pcieerr |= E1000_READ_REG(&sc->hw, E1000_PCIEERRSTS) &
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em_pcie_fatal_error_mask(&sc->hw);
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pcieecc = sc->fatal_error_pcie_ecc;
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if (!em_has_82580_memory_errors(&sc->hw) &&
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!em_has_dh89xxcc_memory_errors(&sc->hw) &&
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(sc->fatal_error_peind & E1000_PEIND_PCIE_PARITY_FATAL) == 0 &&
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pcieerr == 0)
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return;
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@@ -3220,7 +3324,7 @@ em_prepare_fatal_error_reset(struct e1000_softc *sc)
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for (i = 0; i < AUTO_READ_DONE_TIMEOUT; i++) {
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if ((E1000_READ_REG(hw, E1000_EECD) &
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E1000_EECD_AUTO_RD) != 0 &&
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(em_has_82580_memory_errors(hw) ||
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(hw->mac.type == e1000_82580 ||
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(E1000_READ_REG(hw, E1000_STATUS) &
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E1000_STATUS_RST_DONE) != 0))
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break;
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@@ -3234,10 +3338,12 @@ em_prepare_fatal_error_reset(struct e1000_softc *sc)
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device_printf(sc->dev,
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"PCIe master disable failed during parity recovery: %d\n",
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error);
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pcieerr |= E1000_READ_REG(hw, E1000_PCIEERRSTS) &
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em_pcie_fatal_error_mask(hw);
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if (pcieerr != 0)
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E1000_WRITE_REG(hw, E1000_PCIEERRSTS, pcieerr);
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if (!em_has_dh89xxcc_memory_errors(hw)) {
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pcieerr |= E1000_READ_REG(hw, E1000_PCIEERRSTS) &
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em_pcie_fatal_error_mask(hw);
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if (pcieerr != 0)
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E1000_WRITE_REG(hw, E1000_PCIEERRSTS, pcieerr);
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}
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if (em_has_82580_memory_errors(hw)) {
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pcieecc |= E1000_READ_REG(hw, E1000_PCIEECCSTS) &
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E1000_PCIEECCSTS_82580_ERROR_MASK;
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@@ -3305,6 +3411,21 @@ em_finish_fatal_error_reset(struct e1000_softc *sc)
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sc->fatal_error_dma_tx = 0;
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sc->fatal_error_dma_rx = 0;
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sc->fatal_error_dma_host = 0;
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} else if (em_has_dh89xxcc_memory_errors(hw)) {
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em_clear_dh89xxcc_parity_status(hw);
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/* LANPERRSTS is read-only and is cleared by the port reset. */
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lanerr = E1000_READ_REG(hw, E1000_LANPERRSTS) &
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E1000_LANPERRSTS_DH89XXCC_ERROR_MASK;
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if (lanerr != 0)
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device_printf(sc->dev,
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"LAN parity status remained set after reset: %#x\n",
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lanerr);
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(void)E1000_READ_REG(hw, E1000_PEIND);
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sc->fatal_error_peind = 0;
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sc->fatal_error_lan = 0;
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sc->fatal_error_dma_tx = 0;
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sc->fatal_error_dma_rx = 0;
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sc->fatal_error_dma_host = 0;
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} else if (em_has_peind_memory_errors(hw)) {
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pcieerr = sc->fatal_error_pcie |
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(E1000_READ_REG(hw, E1000_PCIEERRSTS) &
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@@ -7465,6 +7586,8 @@ em_update_stats_counters(struct e1000_softc *sc)
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E1000_READ_REG(&sc->hw, E1000_RPBECCSTS),
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E1000_READ_REG(&sc->hw, E1000_TPBECCSTS),
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E1000_READ_REG(&sc->hw, E1000_PCIEECCSTS));
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else if (em_has_dh89xxcc_memory_errors(&sc->hw))
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em_update_dh89xxcc_ecc_stats(sc);
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else if (em_has_i350_i354_memory_errors(&sc->hw))
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em_update_i350_i354_ecc_stats(sc);
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else if (em_has_i210_memory_errors(&sc->hw))
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@@ -8032,6 +8155,11 @@ em_add_hw_stats(struct e1000_softc *sc)
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"uncorrected_pcie", CTLFLAG_RD,
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&sc->uncorrected_error_pcie_count,
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"Uncorrected PCIe command-memory ECC indications");
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} else if (em_has_dh89xxcc_memory_errors(&sc->hw)) {
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SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO,
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"corrected_packet_buffer", CTLFLAG_RD,
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&sc->corrected_error_packet_buffer_count,
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"Corrected transmit packet-buffer ECC errors");
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} else if (em_has_i210_memory_errors(&sc->hw)) {
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SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO,
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"corrected_dma", CTLFLAG_RD,
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