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clk: rockchip: rk3568: Select the sdmmc source clocks by rate

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The sdmmc clocks are muxes without a divider, whose parents provide the
750kHz clock for card identification and the 50MHz and 100MHz clocks for
the bus.  Use RK_CLK_MUX_ROUND_PARENT so that the host driver can change the
card clock, which used to fail with EBUSY and left the SD cards at half
speed.

Differential Revision:	https://reviews.freebsd.org/D60891
This commit is contained in:
Emmanuel Vadot committed 2026-11-05 15:50:33 +01:00
1 parent 9c85482ca5
commit 090ffc7f01
1 file changed
+6 -3
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sys/dev/clk/rockchip/rk3568_cru.c
+6 -3
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@@ -497,9 +497,11 @@ static struct rk_clk rk3568_clks[] = {
MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2),
MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2),
CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4),
MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, 0, 30, 8, 3),
MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p,
RK_CLK_MUX_ROUND_PARENT, 30, 8, 3),
/* 11 Reserved */
MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3),
MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p,
RK_CLK_MUX_ROUND_PARENT, 30, 12, 3),
/* 15 Reserved */
/* CRU_CLKSEL_CON31 */
@@ -523,7 +525,8 @@ static struct rk_clk rk3568_clks[] = {
MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2),
MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2),
CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4),
MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3),
MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p,
RK_CLK_MUX_ROUND_PARENT, 32, 8, 3),
/* 11:15 Reserved */
/* CRU_CLKSEL_CON33 */