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tests: add a regression test for the orphaned IBS NMI
Toggle IBS op and fetch through /dev/cpuctl0 with hwpmc loaded and check that every NMI hwpmc declined was claimed. Without the fix both cases fail on an EPYC 9654. Reviewed by: kib MFC after: 2 weeks Sponsored by: AMD Signed-off-by: Osvaldo Janeri Filho <[email protected]> Differential Revision: https://reviews.freebsd.org/D60766
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Osvaldo Janeri Filho authored and Mitchell Horne committed
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@@ -819,6 +819,8 @@
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..
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compat32
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..
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cpuctl
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..
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devrandom
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..
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dtrace
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@@ -12,6 +12,7 @@ TESTS_SUBDIRS+= capsicum
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TESTS_SUBDIRS+= ${_cddl}
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# XXX: Currently broken in CI
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#TESTS_SUBDIRS+= compat32
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TESTS_SUBDIRS+= ${_cpuctl}
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TESTS_SUBDIRS+= devrandom
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TESTS_SUBDIRS+= fifo
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TESTS_SUBDIRS+= file
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@@ -47,6 +48,10 @@ _audit= audit
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_cddl= cddl
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.endif
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.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
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_cpuctl= cpuctl
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.endif
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.if ${MK_NETGRAPH} != "no"
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_netgraph= netgraph
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.endif
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@@ -0,0 +1,9 @@
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TESTSDIR= ${TESTSBASE}/sys/cpuctl
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ATF_TESTS_C+= cpuctl_ibs_stray_nmi_test
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TEST_METADATA.cpuctl_ibs_stray_nmi_test+= is_exclusive="true"
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TEST_METADATA.cpuctl_ibs_stray_nmi_test+= required_kmods="cpuctl hwpmc"
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TEST_METADATA.cpuctl_ibs_stray_nmi_test+= required_user="root"
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.include <bsd.test.mk>
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@@ -0,0 +1,310 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2026 Advanced Micro Devices, Inc.
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*/
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/*
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* Every IBS NMI hwpmc declines must be claimed after the cpuctl(4) write.
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* machdep.panic_on_nmi is cleared so that an unfixed kernel fails instead
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* of panicking.
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*/
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#include <sys/param.h>
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#include <sys/cpuctl.h>
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#include <sys/cpuset.h>
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#include <sys/ioctl.h>
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#include <sys/sysctl.h>
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#include <machine/specialreg.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <atf-c.h>
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#define FETCH_EN (1ULL << 48)
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#define OP_EN (1ULL << 17)
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#define TOGGLES 20000
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#define FETCH_MAXCNT 0x100ULL /* complete within the spin window */
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#define OP_MAXCNT 0x1000ULL
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#define MAX_SPIN 200000 /* TSC ticks */
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#define STATE_FILE "ibs_stray_state"
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struct stray_state {
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int panic_on_nmi;
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uint64_t fetch;
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uint64_t op;
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};
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static int
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msr_rw(int fd, u_long cmd, uint32_t msr, uint64_t *val)
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{
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cpuctl_msr_args_t args;
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args.msr = msr;
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args.data = *val;
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if (ioctl(fd, cmd, &args) != 0)
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return (errno);
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if (cmd == CPUCTL_RDMSR)
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*val = args.data;
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return (0);
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}
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static uint64_t
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intr_ignored(void)
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{
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uint64_t v;
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size_t len;
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len = sizeof(v);
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ATF_REQUIRE_MSG(sysctlbyname("kern.hwpmc.stats.intr_ignored", &v, &len,
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NULL, 0) == 0, "kern.hwpmc.stats.intr_ignored: %s",
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strerror(errno));
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return (v);
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}
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/* A kernel without the fix has no counter and claims nothing. */
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static uint64_t
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nmis_claimed(void)
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{
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u_long v;
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size_t len;
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len = sizeof(v);
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if (sysctlbyname("machdep.ibs_ctl_write_nmis", &v, &len, NULL,
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0) != 0) {
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ATF_REQUIRE_MSG(errno == ENOENT,
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"machdep.ibs_ctl_write_nmis: %s", strerror(errno));
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return (0);
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}
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return (v);
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}
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static void
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set_panic_on_nmi(int v)
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{
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ATF_REQUIRE_MSG(sysctlbyname("machdep.panic_on_nmi", NULL, NULL, &v,
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sizeof(v)) == 0, "machdep.panic_on_nmi: %s", strerror(errno));
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}
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static int
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setup(void)
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{
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cpuctl_cpuid_args_t ext, vendor;
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struct stray_state st;
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uint64_t v;
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size_t len;
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FILE *f;
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int error, fd;
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fd = open("/dev/cpuctl0", O_RDWR);
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if (fd < 0)
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atf_tc_skip("/dev/cpuctl0: %s", strerror(errno));
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vendor.level = 0;
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ext.level = 0x80000001;
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error = 0;
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if (ioctl(fd, CPUCTL_CPUID, &vendor) != 0 ||
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ioctl(fd, CPUCTL_CPUID, &ext) != 0)
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error = errno;
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if (error != 0) {
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close(fd);
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atf_tc_fail("CPUCTL_CPUID: %s", strerror(error));
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}
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if (!(vendor.data[1] == 0x68747541 && vendor.data[3] == 0x69746e65 &&
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vendor.data[2] == 0x444d4163) && /* AuthenticAMD */
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!(vendor.data[1] == 0x6f677948 && vendor.data[3] == 0x6e65476e &&
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vendor.data[2] == 0x656e6975)) { /* HygonGenuine */
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close(fd);
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atf_tc_skip("not an AMD or Hygon CPU");
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}
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if ((ext.data[2] & AMDID2_IBS) == 0) {
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close(fd);
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atf_tc_skip("CPU does not implement IBS");
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}
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len = sizeof(v);
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if (sysctlbyname("kern.hwpmc.stats.intr_ignored", &v, &len,
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NULL, 0) != 0) {
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close(fd);
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atf_tc_skip("hwpmc is not loaded (IBS NMIs stay masked)");
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}
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len = sizeof(st.panic_on_nmi);
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if (sysctlbyname("machdep.panic_on_nmi", &st.panic_on_nmi, &len,
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NULL, 0) != 0)
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error = errno;
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st.fetch = st.op = 0;
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if (error == 0)
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error = msr_rw(fd, CPUCTL_RDMSR, MSR_AMD_IBS_FETCH_CTL,
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&st.fetch);
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if (error == 0)
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error = msr_rw(fd, CPUCTL_RDMSR, MSR_AMD_IBS_OP_CTL, &st.op);
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if (error != 0) {
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close(fd);
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atf_tc_fail("reading the initial state: %s", strerror(error));
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}
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if ((st.fetch & FETCH_EN) != 0 || (st.op & OP_EN) != 0) {
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close(fd);
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atf_tc_skip("IBS sampling is already enabled on CPU 0 "
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"(fetch 0x%jx, op 0x%jx); run in a reserved environment "
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"with no other IBS users", (uintmax_t)st.fetch,
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(uintmax_t)st.op);
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}
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f = fopen(STATE_FILE, "w");
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if (f == NULL || fwrite(&st, sizeof(st), 1, f) != 1 ||
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fclose(f) != 0) {
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close(fd);
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atf_tc_fail("cannot save the state to %s", STATE_FILE);
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}
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return (fd);
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}
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static void
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toggle(const char *unit, uint32_t msr, uint64_t enable)
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{
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cpuset_t set;
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uint64_t claimed, deadline, ignored, val;
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int fd, i;
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CPU_ZERO(&set);
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CPU_SET(0, &set);
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ATF_REQUIRE(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1,
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sizeof(set), &set) == 0);
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fd = setup();
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set_panic_on_nmi(0);
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srandom((unsigned)__builtin_ia32_rdtsc());
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ignored = intr_ignored();
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claimed = nmis_claimed();
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for (i = 0; i < TOGGLES; i++) {
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val = enable;
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ATF_REQUIRE_EQ(msr_rw(fd, CPUCTL_WRMSR, msr, &val), 0);
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/* Let the disabling write land anywhere in the period. */
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deadline = __builtin_ia32_rdtsc() +
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(uint64_t)(random() % (MAX_SPIN + 1));
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while (__builtin_ia32_rdtsc() < deadline)
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;
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val = 0;
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ATF_REQUIRE_EQ(msr_rw(fd, CPUCTL_WRMSR, msr, &val), 0);
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}
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close(fd);
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ignored = intr_ignored() - ignored;
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claimed = nmis_claimed() - claimed;
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ATF_CHECK_MSG(ignored == claimed,
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"%ju IBS %s NMIs declined by hwpmc, %ju claimed after the cpuctl "
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"write, after %d toggles", (uintmax_t)ignored, unit,
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(uintmax_t)claimed, TOGGLES);
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}
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static void
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restore_msr(int fd, const char *unit, uint32_t msr, uint64_t saved, int *bad)
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{
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uint64_t val;
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int i;
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for (i = 0; i < 3; i++) {
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val = saved;
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if (msr_rw(fd, CPUCTL_WRMSR, msr, &val) == 0 &&
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msr_rw(fd, CPUCTL_RDMSR, msr, &val) == 0 && val == saved)
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return;
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}
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warnx("cannot restore the IBS %s control of CPU 0", unit);
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(*bad)++;
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}
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static void
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cleanup(void)
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{
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struct stray_state st;
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int bad, fd, i, v;
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size_t len;
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FILE *f;
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f = fopen(STATE_FILE, "r");
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if (f == NULL)
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return; /* skipped before anything was changed */
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if (fread(&st, sizeof(st), 1, f) != 1) {
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fclose(f);
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errx(EXIT_FAILURE, "cannot read the saved state");
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}
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fclose(f);
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bad = 0;
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fd = open("/dev/cpuctl0", O_RDWR);
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if (fd < 0) {
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warn("/dev/cpuctl0");
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bad++;
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} else {
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restore_msr(fd, "fetch", MSR_AMD_IBS_FETCH_CTL, st.fetch, &bad);
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restore_msr(fd, "op", MSR_AMD_IBS_OP_CTL, st.op, &bad);
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close(fd);
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}
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for (i = 0; i < 3; i++) {
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len = sizeof(v);
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if (sysctlbyname("machdep.panic_on_nmi", NULL, NULL,
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&st.panic_on_nmi, sizeof(st.panic_on_nmi)) == 0 &&
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sysctlbyname("machdep.panic_on_nmi", &v, &len, NULL,
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0) == 0 && v == st.panic_on_nmi)
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break;
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}
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if (i == 3) {
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warnx("cannot restore machdep.panic_on_nmi to %d",
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st.panic_on_nmi);
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bad++;
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}
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if (bad != 0)
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errx(EXIT_FAILURE, "state not restored");
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}
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ATF_TC_WITH_CLEANUP(raw_op_toggle_claimed);
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ATF_TC_HEAD(raw_op_toggle_claimed, tc)
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{
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atf_tc_set_md_var(tc, "descr",
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"Toggling IBS op through cpuctl leaves no unclaimed NMI");
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}
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ATF_TC_BODY(raw_op_toggle_claimed, tc)
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{
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toggle("op", MSR_AMD_IBS_OP_CTL, OP_EN | OP_MAXCNT);
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}
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ATF_TC_CLEANUP(raw_op_toggle_claimed, tc)
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{
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cleanup();
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}
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ATF_TC_WITH_CLEANUP(raw_fetch_toggle_claimed);
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ATF_TC_HEAD(raw_fetch_toggle_claimed, tc)
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{
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atf_tc_set_md_var(tc, "descr",
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"Toggling IBS fetch through cpuctl leaves no unclaimed NMI");
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}
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ATF_TC_BODY(raw_fetch_toggle_claimed, tc)
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{
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toggle("fetch", MSR_AMD_IBS_FETCH_CTL, FETCH_EN | FETCH_MAXCNT);
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}
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ATF_TC_CLEANUP(raw_fetch_toggle_claimed, tc)
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{
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cleanup();
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}
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ATF_TP_ADD_TCS(tp)
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{
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ATF_TP_ADD_TC(tp, raw_op_toggle_claimed);
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ATF_TP_ADD_TC(tp, raw_fetch_toggle_claimed);
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return (atf_no_error());
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}
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