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https://github.com/joel16/uofw.git
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ge: use brand new L2 cache function
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81965ecfe5
commit
128c203128
@ -81,3 +81,23 @@ static inline void pspClearMemory(void *ptr, int size) {
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pspClearMemory8(ptr, size);
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}
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/* If we believe in the sysmem NIDs, 04g+ seem to have a "L2" cache
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* we can send commands to through this address */
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#define L2_CACHE_CMD (vu32*)0xA7F00000
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static inline void pspL2CacheWriteback0(void *ptr, u8 align) {
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*L2_CACHE_CMD = 0xA0000000 | ((u32)ptr & 0x07FFFFC0) | align;
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*L2_CACHE_CMD;
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}
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static inline void pspL2CacheWriteback1(void *ptr, u8 align) {
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*L2_CACHE_CMD = 0xA0000000 | 0x08000000 | ((u32)ptr & 0x07FFFFC0) | align;
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*L2_CACHE_CMD;
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}
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static inline void pspL2CacheWriteback10(void *ptr, u8 align) {
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*L2_CACHE_CMD = 0xA0000000 | 0x08000000 | ((u32)ptr & 0x07FFFFC0) | align;
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*L2_CACHE_CMD = 0xA0000000 | ((u32)ptr & 0x07FFFFC0) | align;
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*L2_CACHE_CMD;
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}
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@ -4,7 +4,7 @@
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TARGET = ge
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OBJS = stall.o ge.o
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DEBUG = 1
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DEBUG = 0
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LIBS = -lInterruptManagerForKernel -lThreadManForKernel -lsceSysreg_driver -lKDebugForKernel -lUtilsForKernel -lsceSysEventForKernel -lSysMemForKernel -lSysclibForKernel -lInitForKernel
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46
src/ge/ge.c
46
src/ge/ge.c
@ -26,7 +26,6 @@ SCE_MODULE_REBOOT_PHASE("_sceGeModuleRebootPhase");
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#pragma GCC diagnostic pop
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SCE_SDK_VERSION(SDK_VERSION);
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#define HW_GE_CTRL HW(0xA7F00000)
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#define HW_GE_RESET HW(0xBD400000)
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#define HW_GE_UNK004 HW(0xBD400004)
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#define HW_GE_EDRAM_HW_SIZE HW(0xBD400008)
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@ -941,11 +940,9 @@ int sceGeSetCmd(u32 cmdOff, u32 cmd)
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}
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// 0C44
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pspCache(0x1A, dl);
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// XXX 04g+ caching
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL = ((int)dl & 0x07FFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback0(dl, 1);
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}
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// 0C88
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sceSysregSetMasterPriv(64, 1);
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@ -1228,10 +1225,7 @@ int _sceGeSetInternalReg(int type, int base, int radr1, int radr2)
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pspCache(0x1A, uncachedNewCmdList);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)uncachedNewCmdList | 0x08000000) &
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0x0FFFFFC0) | 0xA0000000;
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HW_GE_CTRL;
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pspL2CacheWriteback1(uncachedNewCmdList, 0);
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}
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// 1E18
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cmdList[1] = GE_MAKE_OP(SCE_GE_CMD_BASE, (relAddr >> 24) << 16);
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@ -1250,10 +1244,7 @@ int _sceGeSetInternalReg(int type, int base, int radr1, int radr2)
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uncachedNewCmdList[0] = oldCmd;
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)uncachedNewCmdList | 0x08000000) &
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0x0FFFFFC0) | 0xA0000000;
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HW_GE_CTRL;
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pspL2CacheWriteback1(uncachedNewCmdList, 0);
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}
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}
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// 1ED0
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@ -1266,10 +1257,7 @@ int _sceGeSetInternalReg(int type, int base, int radr1, int radr2)
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pspCache(0x1A, uncachedNewCmdList);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)uncachedNewCmdList | 0x08000000) &
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0x0FFFFFC0) | 0xA0000000;
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HW_GE_CTRL;
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pspL2CacheWriteback1(uncachedNewCmdList, 0);
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}
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// 1F50
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cmdList[1] = GE_MAKE_OP(SCE_GE_CMD_BASE, (relAddr >> 24) << 16);
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@ -1291,10 +1279,7 @@ int _sceGeSetInternalReg(int type, int base, int radr1, int radr2)
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pspCache(0x1A, uncachedNewCmdList);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)uncachedNewCmdList | 0x08000000) &
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0x0FFFFFC0) | 0xA0000000;
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HW_GE_CTRL;
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pspL2CacheWriteback1(uncachedNewCmdList, 0);
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}
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}
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cmdList[0] = base;
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@ -1723,10 +1708,7 @@ int _sceGeQueueSuspend()
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pspCache(0x1A, &stall[1]);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)stall | 0x08000000) & 0x0FFFFFC0) | 0xA0000001;
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HW_GE_CTRL = ((int)stall & 0x07FFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback10(stall, 1);
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}
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// 2ECC
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HW_GE_STALLADDR += 8;
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@ -3243,9 +3225,7 @@ void _sceGeWriteBp(int *list)
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pspCache(0x1A, &ptr2[1]);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)ptr2 | 0x08000000) & 0x0FFFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback1(ptr2, 1);
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}
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}
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// 5494
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@ -3267,9 +3247,7 @@ void _sceGeWriteBp(int *list)
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pspCache(0x1A, &ptr[1]);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)ptr | 0x08000000) & 0x0FFFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback1(ptr, 1);
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}
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}
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// 5504
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@ -3298,9 +3276,7 @@ void _sceGeClearBp()
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pspCache(0x1A, &out[1]);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)out | 0x08000000) & 0x0FFFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback1(out, 1);
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}
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// 5684
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}
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@ -3315,9 +3291,7 @@ void _sceGeClearBp()
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pspCache(0x1A, &out[1]);
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if ((pspCop0StateGet(24) & 1) != 0) {
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pspSync();
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HW_GE_CTRL =
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(((int)out | 0x08000000) & 0x0FFFFFC0) | 0xA0000001;
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HW_GE_CTRL;
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pspL2CacheWriteback1(out, 1);
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}
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// 5728
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}
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