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Merge pull request #110 from uofw/syscon-controller-firmware-ta-096
Syscon controller firmware ta 096
This commit is contained in:
artart78
GitHub
commit
5b3a798316
@ -264,6 +264,9 @@ enum SceCtrlPadButtonMaskMode {
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SCE_CTRL_MASK_APPLY_BUTTONS = 2,
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};
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/* The center position of the analog stick on both axes. */
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#define SCE_CTRL_ANALOG_PAD_CENTER_VALUE 0x80
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/**
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* Initializes the controller device. Bind the controller driver to the controller device.
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*
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@ -17,10 +17,11 @@
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*/
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#define PSP_SYSCON_CMD_NOP 0x00
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#define PSP_SYSCON_CMD_GET_BARYON 0x01
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#define PSP_SYSCON_CMD_GET_BARYON_VERSION 0x01
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#define PSP_SYSCON_CMD_GET_DIGITAL_KEY 0x02
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#define PSP_SYSCON_CMD_GET_ANALOG 0x03
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#define PSP_SYSCON_CMD_GET_TACHYON_TEMP 0x05
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#define PSP_SYSCON_CMD_GET_DIGITAL_KEY_ANALOG 0x06
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#define PSP_SYSCON_CMD_GET_KERNEL_DIGITAL_KEY 0x07
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#define PSP_SYSCON_CMD_GET_KERNEL_DIGITAL_KEY_ANALOG 0x08
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@ -50,6 +51,8 @@
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#define PSP_SYSCON_CMD_RESET_DEVICE 0x32
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#define PSP_SYSCON_CMD_CTRL_ANALOG_XY_POLLING 0x33
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#define PSP_SYSCON_CMD_CTRL_HR_POWER 0x34
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#define PSP_SYSCON_CMD_POWER_STANDBY 0x35
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#define PSP_SYSCON_CMD_POWER_SUSPEND 0x36
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#define PSP_SYSCON_CMD_GET_BATT_VOLT_AD 0x37
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@ -782,6 +785,11 @@ s32 sceSysconWriteScratchPad(u32 dst, void *src, u32 size);
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*/
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s32 sceSysconReadScratchPad(u32 src, void *dst, u32 size);
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#define SCE_SYSCON_SET_PARAM_POWER_BATTERY_SUSPEND_CAPACITY 0
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#define SCE_SYSCON_SET_PARAM_POWER_BATTERY_TTC 4
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#define SCE_SYSCON_SET_PARAM_PAYLOAD_SIZE 8
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/**
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* Set a parameter (used by power).
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*
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@ -863,6 +871,15 @@ s32 sceSysconGetBaryonVersion(s32 *baryonVersion);
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*/
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s32 sceSysconGetGValue(void);
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/* Returned power supply status flags by ::sceSysconGetPowerSupplyStatus() */
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/* Indicates that a battery is equipped. */
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#define SCE_SYSCON_POWER_SUPPLY_STATUS_BATTERY_EQUIPPED 0x00000002
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/* Indicates that remaining battery life is short (PSP-2000 and later). */
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#define SCE_SYSCON_POWER_SUPPLY_STATUS_IS_LOW_BATTERY_02G_AND_LATER 0x00000020
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/* Indicates that the battery is currently charging (using an AC adapter). */
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#define SCE_SYSCON_POWER_SUPPLY_STATUS_BATTERY_CHARGING 0x00000080
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/**
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* Get the power supply status.
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*
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@ -67,7 +67,7 @@ SCE_SDK_VERSION(SDK_VERSION);
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#define CTRL_MAX_INTERNAL_CONTROLLER_BUFFER (CTRL_NUM_INTERNAL_CONTROLLER_BUFFERS - 1)
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/* The center position of the analog stick on both axes. */
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#define CTRL_ANALOG_PAD_CENTER_VALUE (0x80)
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#define CTRL_ANALOG_PAD_CENTER_VALUE (0x80) // TODO: Replace with SCE_CTRL_ANALOG_PAD_CENTER_VALUE
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/* The minimum position of the analog stick on both axes. */
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#define CTRL_ANALOG_PAD_MIN_VALUE (0)
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@ -1597,7 +1597,7 @@ s32 sceSysconNop(void)
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s32 sceSysconGetBaryonVersion(s32 *baryonVersion)
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{
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return _sceSysconCommonRead(baryonVersion, PSP_SYSCON_CMD_GET_BARYON);
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return _sceSysconCommonRead(baryonVersion, PSP_SYSCON_CMD_GET_BARYON_VERSION);
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}
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s32 sceSysconGetGValue(void)
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47
src/syscon_firmware/firmware.h
Normal file
47
src/syscon_firmware/firmware.h
Normal file
@ -0,0 +1,47 @@
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/* Copyright (C) The uOFW team
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See the file COPYING for copying permission.
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*/
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#include "common_header.h"
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#ifndef FIRMWARE_H
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#define FIRMWARE_H
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/*
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* This constant specifies the base length of the data to be transmitted back to the SYSCON module.
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* This base length represents the first three members in the ::SceSysconPacket.tx[16] data buffer, which
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* are always sent back to the SYSCON module.
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*/
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#define SYSCON_CMD_TRANSMIT_DATA_BASE_LEN 3
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/*
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* This constant indicates that the watch dog timer is not currently counting. For example, this is the case
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* when the timer counter has counted downwards until it reached the value 0, at which point there is nothing
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* left to count. This can indicate that the watchdog timer counter could not be properly resetted.
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*/
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#define WATCHDOG_TIMER_STATUS_NOT_COUNTING 0
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#define WATCHDOG_TIMER_STATUS_COUNTING 1
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#define MAIN_OPERATION_RESULT_STATUS_UNKNOWN_0x80 0x80
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#define MAIN_OPERATION_RESULT_STATUS_UNKNOWN_0x81 0x81 // TODO: perhaps a [retry] indicator -- perhaps SYSCON_BUSY?
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#define MAIN_OPERATION_RESULT_STATUS_SUCCESS 0x82
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#define MAIN_OPERATION_RESULT_STATUS_ERROR 0x83 // TODO: More like: Invalid_Size
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#define MAIN_OPERATION_RESULT_STATUS_NOT_SUPPORTED 0x84
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#define MAIN_OPERATION_RESULT_STATUS_INVALID_ID 0x87
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#define MAIN_OPERATIONS_ID_START PSP_SYSCON_CMD_WRITE_CLOCK
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#define PERIPHERAL_OPERATIONS_ID_START PSP_SYSCON_CMD_GET_POMMEL_VERSION
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/* SYSCON's internal scratchpad buffer size. */
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#define SCRATCH_PAD_SIZE 32
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/*
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* Macros to obtain SYSCON's scratchpad destination ("index") and size of data to read/write from the received
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* encoded data (first byte of g_mainOperationPayloadReceiveBuffer).
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*/
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#define SYSCON_SCRATCHPAD_GET_DST(enc) (((enc) >> 2) & 0x3F)
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#define SYSCON_SCRATCHPAD_GET_DATA_SIZE(enc) ((enc) & 0x3)
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#define SYSCON_SCRATCHPAD_SET_DATA_SIZE(enc, s) (((enc) & ~0x3) | ((s) & 0x3))
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#endif // FIRMWARE_H
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2015
src/syscon_firmware/firmware_ta096.c
Normal file
2015
src/syscon_firmware/firmware_ta096.c
Normal file
File diff suppressed because it is too large
Load Diff
451
src/syscon_firmware/sfr.h
Normal file
451
src/syscon_firmware/sfr.h
Normal file
@ -0,0 +1,451 @@
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/* Copyright (C) The uOFW team
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See the file COPYING for copying permission.
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*/
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#ifndef SFR_H
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#define SFR_H
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/* Special Function Registers (SFR) */
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/* Port register 1 */
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#define P0 (*(u8 *)0xFF00)
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/* Port register 1 */
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#define P1 (*(u8 *)0xFF01)
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/* Port register 2 */
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#define P2 (*(u8 *)0xFF02)
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/* Port register 3 */
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#define P3 (*(u8 *)0xFF03)
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/* Port register 4 */
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#define P4 (*(u8 *)0xFF04)
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/* Port register 5 */
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#define P5 (*(u8 *)0xFF05)
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/* Port register 6 */
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#define P6 (*(u8 *)0xFF06)
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/* Port register 7 */
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#define P7 (*(u8 *)0xFF07)
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/* 10-bit A/D conversion result register */
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#define ADCR (*(const u16 *)0xFF08)
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/* 8-bit A/D conversion result register */
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#define ADCRH (*(const u8 *)0xFF09)
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/* Receive buffer register 6 */
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#define RXB6 (*(const u8 *)0xFF0A)
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/* Transmit buffer register 6 */
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#define TXB6 (*(u8 *)0xFF0B))
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/* Port register 12 */
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#define P12 (*(u8 *)0xFF0C)
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/* Port register 14 */
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#define P14 (*(u8 *)0xFF0E)
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/* Serial I/O shift register 10 */
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#define SIO10 (*(const u8 *)0xFF0F)
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/* 16-bit timer counter 00 */
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#define TM00 (*(const u16 *)0xFF10)
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/* 16-bit timer capture/compare register 000 */
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#define CR000 (*(u16 *)0xFF12)
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/* 16-bit timer capture/compare register 010 */
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#define CR010 (*(u16 *)0xFF14)
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/* 8-bit timer counter 50 */
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#define TM50 (*(const u8 *)0xFF16)
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/* 8-bit timer compare register 50 */
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#define CR50 (*(u8 *)0xFF17)
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/* 8-bit timer H compare register 00 */
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#define CMP00 (*(u8 *)0xFF18)
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/* 8-bit timer H compare register 10 */
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#define CMP10 (*(u8 *)0xFF19)
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/* 8-bit timer H compare register 01 */
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#define CMP01 (*(u8 *)0xFF1A)
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/* 8-bit timer H compare register 11 */
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#define CMP11 (*(u8 *)0xFF1B)
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/* 16-bit processor register SP (stack pointer) */
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#define PROCESSOR_REGISTER_SP ((u16 *)0xFF1C)
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/* 8-bit processor register PSW (Program Status Word) */
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#define PROCESSOR_REGISTER_PSW ((u8 *)0xFF1E)
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/* 8-bit timer counter 51 */
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#define TM51 (*(const u8 *)0xFF1F
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/* Port mode register 0 */
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#define PM0 (*(u8 *)0xFF20)
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/* Port mode register 1 */
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#define PM1 (*(u8 *)0xFF21)
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/* Port mode register 2 */
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#define PM2 (*(u8 *)0xFF22)
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/* Port mode register 3 */
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#define PM3 (*(u8 *)0xFF23)
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/* Port mode register 4 */
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#define PM4 (*(u8 *)0xFF24)
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/* Port mode register 5 */
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#define PM5 (*(u8 *)0xFF25)
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/* Port mode register 6 */
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#define PM6 (*(u8 *)0xFF26)
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/* Port mode register 7 */
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#define PM7 (*(u8 *)0xFF27)
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/* A/D converter mode register */
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#define ADM (*(u8 *)0xFF28)
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/* Analog input channel specification register */
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#define ADS (*(u8 *)0xFF29)
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/* Port mode register 12 */
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#define PM12 (*(u8 *)0xFF2C)
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/* Port mode register 14 */
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#define PM14 (*(u8 *)0xFF2E)
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/* A/D port configuration register */
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#define ADPC (*(u8 *)0xFF2F)
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/* Pull-up resistor option register 0 */
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#define PU0 (*(u8 *)0xFF30)
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/* Pull-up resistor option register 1 */
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#define PU1 (*(u8 *)0xFF31)
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/* Pull-up resistor option register 3 */
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#define PU3 (*(u8 *)0xFF33)
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/* Pull-up resistor option register 4 */
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#define PU4 (*(u8 *)0xFF34)
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/* Pull-up resistor option register 5 */
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#define PU5 (*(u8 *)0xFF35)
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/* Pull-up resistor option register 7 */
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#define PU7 (*(u8 *)0xFF37)
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/* Pull-up resistor option register 12 */
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#define PU12 (*(u8 *)0xFF3C)
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/* Pull-up resistor option register 14 */
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#define PU14 (*(u8 *)0xFF3E)
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/* Clock output selection register */
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#define CKS (*(u8 *)0xFF40)
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/* 8-bit timer compare register 51 */
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#define CR51 (*(u8 *)0xFF41)
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/* 8-bit timer mode control register 51 */
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#define TMC51 (*(u8 *)0xFF43)
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/* External interrupt rising edge enable register */
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#define EGP (*(u8 *)0xFF48)
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/* External interrupt falling edge enable register */
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#define EGN (*(u8 *)0xFF49)
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/* Serial I/O shift register 11 */
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#define SIO11 (*(const u8 *)0xFF4A)
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/* Transmit buffer register 11 */
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#define SOTB11 (*(u8 *)0xFF4C)
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/* Input switch control register */
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#define ISC (*(u8 *)0xFF4F)
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/* Asynchronous serial interface operation mode register 6 */
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#define ASIM6 (*(u8 *)0xFF50)
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/* Asynchronous serial interface reception error status register 6 */
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#define ASIS6 (*(const u8 *)0xFF53)
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/* Asynchronous serial interface transmission status register 6 */
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#define ASIF6 (*(const u8 *)0xFF55)
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/* Clock selection register 6 */
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#define CKSR6 (*(u8 *)0xFF56)
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/* Baud rate generator control register 6 */
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#define BRGC6 (*(u8 *)0xFF57)
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/* Asynchronous serial interface control register 6 */
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#define ASICL6 (*(u8 *)0xFF58)
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/* Remainder data register 0 */
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#define SDR0 (*(const u8 *)0xFF60)
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/* Multiplication/division data register A0 */
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/* A0 low */
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/* A0 low low */
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#define MDA0LL (*(u8 *)0xFF62)
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/* A0 low high */
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#define MDA0LH (*(u8 *)0xFF63)
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/* A0 high */
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/* A0 high low */
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#define MDA0HL (*(u8 *)0xFF64)
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/* A0 high high */
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#define MDA0HH (*(u8 *)0xFF65)
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/* Multiplication/division data register B0 */
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/* B0 low */
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#define MDB0L (*(u8 *)0xFF66)
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/* B0 High */
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#define MDB0H (*(u8 *)0xFF66)
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/* Multiplier/divider control register 0 */
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#define DMUC0 (*(u8 *)0xFF68)
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/* 8-bit timer H mode register 0 */
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#define TMHMD0 (*(u8 *)0xFF69)
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/* Timer clock selection register 50 */
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#define TCL50 (*(u8 *)0xFF6A)
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/* 8-bit timer mode control register 50 */
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#define TMC50 (*(u8 *)0xFF6B)
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/* 8-bit timer H mode register 1 */
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#define TMHMD1 (*(u8 *)0xFF6C)
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/* 8-bit timer H carrier control register 1 */
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#define TMCYC1 (*(u8 *)0xFF6D)
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/* Key return mode register */
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#define KRM (*(u8 *)0xFF6E)
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/* Watch timer operation mode register */
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#define WTM (*(u8 *)0xFF6F)
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/* Asynchronous serial interface operation mode register 0 */
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#define ASIM0 (*(u8 *)0xFF70)
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/* Baud rate generator control register 0 */
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#define BRGC0 (*(u8 *)0xFF71)
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/* Receive buffer register 0 */
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#define RXB0 (*(const u8 *)0xFF72)
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/* Asynchronous serial interface reception error status register 0 */
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#define ASIS0 (*(const u8 *)0xFF73)
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/* Transmit shift register 0 (write-only) */
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#define TXS0 (*(u8 *)0xFF74)
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/* Serial operation mode register 10 */
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#define CSIM10 (*(u8 *)0xFF80)
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/* Serial clock selection register 10 */
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#define CSIC10 (*(u8 *)0xFF81)
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/* Transmit buffer register 10 */
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#define SOTB10 (*(u8 *)0xFF84)
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/* Serial operation mode register 11 */
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#define CSIM11 (*(u8 *)0xFF88)
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/* Serial clock selection register 11 */
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#define CSIC11 (*(u8 *)0xFF89)
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/* Timer clock selection register 51 */
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#define TCL51 (*(u8 *)0xFF8C)
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/*
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* When this constant is written to the WDTE register, the watchdog timer counter is cleared and couting starts
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* again.
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*/
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#define WATCHDOG_TIMER_ENABLE_REGISTER_RESET_WATCHDOG_TIMER 0xAC
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/* Watchdog timer enable register */
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#define WDTE (*(u8 *)0xFF99)
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/* Clock operation mode select register */
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#define OSCCTL (*(u8 *)0xFF9F)
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/* Internal oscillation mode register */
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#define RCM (*(u8 *)0xFFA0)
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/* Main clock mode register */
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#define MCM (*(u8 *)0xFFA1)
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/* Main OSC control register */
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#define MOC (*(u8 *)0xFFA2)
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/* Oscillation stabilization time counter status register */
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#define OSTC (*(const u8 *)0xFFA3)
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/* Oscillation stabilization time select register */
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#define OSTS (*(u8 *)0xFFA4)
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/* IIC shift register 0 */
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#define IIC0 (*(u8 *)0xFFA5)
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/* IIC control register 0 */
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#define IICC0 (*(u8 *)0xFFA6)
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/* Slave address register 0 */
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#define SVA0 (*(u8 *)0xFFA7)
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/* IIC clock selection register 0 */
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#define IICCL0 (*(u8 *)0xFFA8)
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/* IIC function expansion register 0 */
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#define IICX0 (*(u8 *)0xFFA9)
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/* IIC status register 0 */
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#define IICS0 (*(const u8 *)0xFFAA)
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/* IIC flag register 0 */
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#define IICF0 (*(u8 *)0xFFAB)
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/* Reset control flag register */
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#define RESF (*(const u8 *)0xFFAC)
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/* 16-bit timer counter 01 */
|
||||
#define IICF0 (*(const u16 *)0xFFB0)
|
||||
|
||||
/* 16-bit timer capture/compare register 001 */
|
||||
#define CR001 (*(u16 *)0xFFB2)
|
||||
|
||||
/* 16-bit timer capture/compare register 011 */
|
||||
#define CR011 (*(u16 *)0xFFB4)
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||||
|
||||
/* 16-bit timer mode control register 01 */
|
||||
#define TMC01 (*(u8 *)0xFFB6)
|
||||
|
||||
/* Prescaler mode register 01 */
|
||||
#define PRM01 (*(u8 *)0xFFB7)
|
||||
|
||||
/* Capture/compare control register 01 */
|
||||
#define CRC01 (*(u8 *)0xFFB8)
|
||||
|
||||
/* 16-bit timer output control register 01 */
|
||||
#define TOC01 (*(u8 *)0xFFB9)
|
||||
|
||||
/* 16-bit timer mode control register 00 */
|
||||
#define TMC00 (*(u8 *)0xFFBA)
|
||||
|
||||
/* Prescaler mode register 00 */
|
||||
#define PRM00 (*(u8 *)0xFFBB)
|
||||
|
||||
/* Capture/compare control register 00 */
|
||||
#define CRC00 (*(u8 *)0xFFBC)
|
||||
|
||||
/* 16-bit timer output control register 00 */
|
||||
#define TOC00 (*(u8 *)0xFFBD)
|
||||
|
||||
/* Low-voltage detection register */
|
||||
#define LVIM (*(u8 *)0xFFBE)
|
||||
|
||||
/* Low-voltage detection level selection register */
|
||||
#define LVIS (*(u8 *)0xFFBF)
|
||||
|
||||
#define PFCMD (*(u8 *)0xFFC0)
|
||||
|
||||
#define FLPMC (*(u8 *)0xFFC4)
|
||||
|
||||
#define IF0L_INTR_REQ_FLAG_LVI (1 << 0)
|
||||
#define IF0L_INTR_REQ_FLAG_PO (1 << 1)
|
||||
#define IF0L_INTR_REQ_FLAG_P1 (1 << 2)
|
||||
#define IF0L_INTR_REQ_FLAG_P2 (1 << 3) /* Interrupt request flag for input pin 2 (P31) */
|
||||
#define IF0L_INTR_REQ_FLAG_P3 (1 << 4)
|
||||
#define IF0L_INTR_REQ_FLAG_P4 (1 << 5)
|
||||
#define IF0L_INTR_REQ_FLAG_P5 (1 << 6)
|
||||
#define IF0L_INTR_REQ_FLAG_SRE6 (1 << 7)
|
||||
|
||||
/* Interrupt request flag register 0L */
|
||||
#define IF0L (*(u8 *)0xFFE0)
|
||||
|
||||
#define IF0H_INTR_REQ_FLAG_SR6 (1 << 0)
|
||||
#define IF0H_INTR_REQ_FLAG_ST6 (1 << 1)
|
||||
#define IF0H_INTR_REQ_FLAG_CSI10 (1 << 2)
|
||||
#define IF0H_INTR_REQ_FLAG_TMH1 (1 << 3)
|
||||
#define IF0H_INTR_REQ_FLAG_TMH0 (1 << 4)
|
||||
#define IF0H_INTR_REQ_FLAG_TM50 (1 << 5)
|
||||
#define IF0H_INTR_REQ_FLAG_TM000 (1 << 6)
|
||||
#define IF0H_INTR_REQ_FLAG_TM010 (1 << 7)
|
||||
|
||||
/* Interrupt request flag register 0H */
|
||||
#define IF0H (*(u8 *)0xFFE1)
|
||||
|
||||
/* Interrupt request flag register 1L */
|
||||
#define IF1L (*(u8 *)0xFFE2)
|
||||
|
||||
/* Interrupt request flag register 1H */
|
||||
#define IF1H (*(u8 *)0xFFE3)
|
||||
|
||||
#define MK0L_INTR_MASK_FLAG_LVI (1 << 0)
|
||||
#define MK0L_INTR_MASK_FLAG_P0 (1 << 1)
|
||||
#define MK0L_INTR_MASK_FLAG_P1 (1 << 2)
|
||||
#define MK0L_INTR_MASK_FLAG_P2 (1 << 3) /* Interrupt mask bit for input pin 2 (P31) */
|
||||
#define MK0L_INTR_MASK_FLAG_P3 (1 << 4)
|
||||
#define MK0L_INTR_MASK_FLAG_P4 (1 << 5)
|
||||
#define MK0L_INTR_MASK_FLAG_P5 (1 << 6)
|
||||
#define MK0L_INTR_MASK_FLAG_SRE6 (1 << 7)
|
||||
|
||||
/* Interrupt mask flag register 0L */
|
||||
#define MK0L (*(u8 *)0xFFE4)
|
||||
|
||||
/* Interrupt mask flag register 0H */
|
||||
#define MK0H (*(u8 *)0xFFE5)
|
||||
|
||||
/* Interrupt mask flag register 1L */
|
||||
#define MK1L (*(u8 *)0xFFE6)
|
||||
|
||||
/* Interrupt mask flag register 1H */
|
||||
#define MK1H (*(u8 *)0xFFE7)
|
||||
|
||||
/* Priority specification flag register 0L */
|
||||
#define PR0L (*(u8 *)0xFFE8)
|
||||
|
||||
/* Priority specification flag register 0H */
|
||||
#define PR0H (*(u8 *)0xFFE9)
|
||||
|
||||
/* Priority specification flag register 1L */
|
||||
#define PR1L (*(u8 *)0xFFEA)
|
||||
|
||||
/* Priority specification flag register 1H */
|
||||
#define PR1H (*(u8 *)0xFFEB)
|
||||
|
||||
/* Internal memory size switching register */
|
||||
#define IMS (*(u8 *)0xFFF0)
|
||||
|
||||
/* Memory bank select register */
|
||||
#define BANK (*(u8 *)0xFFF3)
|
||||
|
||||
/* Internal expansion RAM size switching register */
|
||||
#define IXS (*(u8 *)0xFFF4)
|
||||
|
||||
/* Processor clock control register */
|
||||
#define PCC (*(u8 *)0xFFFB)
|
||||
|
||||
#endif /* SFR_H */
|
||||
Loading…
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Reference in New Issue
Block a user