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https://github.com/keystone-engine/keystone.git
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cleanup and formatting
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@@ -23,6 +23,7 @@ samples/sample
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_sample*.txt
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tmp
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MANIFEST
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.vscode
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bindings/python/dist/
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bindings/python/src/
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Vendored
-18
@@ -1,18 +0,0 @@
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{
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"configurations": [
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{
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"name": "Linux",
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"includePath": [
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"${workspaceFolder}/**",
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"${workspaceFolder}/include",
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"${workspaceFolder}/llvm/lib/Target/**"
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],
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"defines": [],
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"compilerPath": "/usr/bin/gcc",
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"cStandard": "c17",
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"cppStandard": "gnu++17",
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"intelliSenseMode": "linux-gcc-x64"
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}
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],
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"version": 4
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}
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Vendored
-59
@@ -1,59 +0,0 @@
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{
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// Use IntelliSense to learn about possible attributes.
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// Hover to view descriptions of existing attributes.
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// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
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"version": "0.2.0",
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"configurations": [
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{
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"name": "(gdb) MIPS Launch",
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"type": "cppdbg",
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"request": "launch",
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"program": "/home/kali/keystone/build/kstool/kstool",
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"args": ["mips", "'nop'"],
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"stopAtEntry": false,
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"cwd": "${workspaceFolder}",
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"environment": [],
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"externalConsole": false,
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"MIMode": "gdb",
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"miDebuggerPath": "/usr/bin/gdb",
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"setupCommands": [
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{
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"description": "Enable pretty-printing for gdb",
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"text": "-enable-pretty-printing",
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"ignoreFailures": true
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},
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{
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"description": "Set Disassembly Flavor to Intel",
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"text": "-gdb-set disassembly-flavor intel",
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"ignoreFailures": true
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}
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]
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},
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{
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"name": "(gdb) RISCVLaunch",
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"type": "cppdbg",
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"request": "launch",
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"program": "/home/kali/keystone/build/kstool/kstool",
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"args": ["riscv64", "'mul a2, a1, a1'"],
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"stopAtEntry": true,
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"cwd": "${workspaceFolder}",
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"environment": [],
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"externalConsole": false,
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"MIMode": "gdb",
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"miDebuggerPath": "/usr/bin/gdb",
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"setupCommands": [
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{
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"description": "Enable pretty-printing for gdb",
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"text": "-enable-pretty-printing",
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"ignoreFailures": true
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},
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{
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"description": "Set Disassembly Flavor to Intel",
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"text": "-gdb-set disassembly-flavor intel",
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"ignoreFailures": true
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}
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]
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}
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]
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}
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Vendored
-66
@@ -1,66 +0,0 @@
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{
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"files.associations": {
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"*.inc": "c",
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"*.tcc": "cpp",
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"bitset": "cpp",
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"lanebitmask.h": "c",
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"cctype": "cpp",
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"clocale": "cpp",
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"cmath": "cpp",
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"cstdarg": "cpp",
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"cstddef": "cpp",
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"cstdio": "cpp",
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"cstdlib": "cpp",
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"cstring": "cpp",
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"ctime": "cpp",
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"cwchar": "cpp",
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"cwctype": "cpp",
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"array": "cpp",
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"atomic": "cpp",
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"bit": "cpp",
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"chrono": "cpp",
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"cinttypes": "cpp",
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"compare": "cpp",
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"concepts": "cpp",
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"condition_variable": "cpp",
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"cstdint": "cpp",
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"deque": "cpp",
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"list": "cpp",
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"map": "cpp",
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"set": "cpp",
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"string": "cpp",
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"unordered_map": "cpp",
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"vector": "cpp",
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"exception": "cpp",
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"algorithm": "cpp",
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"functional": "cpp",
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"iterator": "cpp",
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"memory": "cpp",
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"memory_resource": "cpp",
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"numeric": "cpp",
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"random": "cpp",
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"ratio": "cpp",
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"string_view": "cpp",
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"system_error": "cpp",
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"tuple": "cpp",
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"type_traits": "cpp",
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"utility": "cpp",
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"future": "cpp",
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"initializer_list": "cpp",
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"iosfwd": "cpp",
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"istream": "cpp",
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"limits": "cpp",
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"mutex": "cpp",
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"new": "cpp",
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"numbers": "cpp",
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"ostream": "cpp",
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"semaphore": "cpp",
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"sstream": "cpp",
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"stdexcept": "cpp",
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"stop_token": "cpp",
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"streambuf": "cpp",
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"thread": "cpp",
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"typeinfo": "cpp"
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},
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"C_Cpp.dimInactiveRegions": false
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}
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@@ -5,7 +5,7 @@ OBJDIR = ./build
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else
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OBJDIR = $(abspath $(BUILDDIR))/obj/bindings/python
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endif
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.PHONY: gen_const install install3 clean
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gen_const:
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@@ -1,95 +0,0 @@
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//===- llvm/MC/LaneBitmask.h ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// A common definition of LaneBitmask for use in TableGen and CodeGen.
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///
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/// A lane mask is a bitmask representing the covering of a register with
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/// sub-registers.
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///
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/// This is typically used to track liveness at sub-register granularity.
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/// Lane masks for sub-register indices are similar to register units for
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/// physical registers. The individual bits in a lane mask can't be assigned
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/// any specific meaning. They can be used to check if two sub-register
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/// indices overlap.
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///
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/// Iff the target has a register such that:
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///
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/// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
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///
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/// then:
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///
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/// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0
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#ifndef LLVM_MC_LANEBITMASK_H
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#define LLVM_MC_LANEBITMASK_H
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm_ks {
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struct LaneBitmask {
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// When changing the underlying type, change the format string as well.
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using Type = unsigned;
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enum : unsigned { BitWidth = 8*sizeof(Type) };
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constexpr static const char *const FormatStr = "%08X";
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constexpr LaneBitmask() = default;
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explicit constexpr LaneBitmask(Type V) : Mask(V) {}
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constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; }
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constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
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constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
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constexpr bool none() const { return Mask == 0; }
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constexpr bool any() const { return Mask != 0; }
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constexpr bool all() const { return ~Mask == 0; }
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constexpr LaneBitmask operator~() const {
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return LaneBitmask(~Mask);
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}
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constexpr LaneBitmask operator|(LaneBitmask M) const {
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return LaneBitmask(Mask | M.Mask);
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}
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constexpr LaneBitmask operator&(LaneBitmask M) const {
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return LaneBitmask(Mask & M.Mask);
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}
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LaneBitmask &operator|=(LaneBitmask M) {
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Mask |= M.Mask;
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return *this;
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}
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LaneBitmask &operator&=(LaneBitmask M) {
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Mask &= M.Mask;
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return *this;
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}
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constexpr Type getAsInteger() const { return Mask; }
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unsigned getNumLanes() const {
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return countPopulation(Mask);
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}
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unsigned getHighestLane() const {
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return Log2_32(Mask);
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}
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static constexpr LaneBitmask getNone() { return LaneBitmask(0); }
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static constexpr LaneBitmask getAll() { return ~LaneBitmask(0); }
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static constexpr LaneBitmask getLane(unsigned Lane) {
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return LaneBitmask(Type(1) << Lane);
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}
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private:
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Type Mask = 0;
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};
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} // end namespace llvm
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#endif // LLVM_MC_LANEBITMASK_H
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@@ -89,17 +89,6 @@ public:
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/// appropriate.
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virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel, unsigned int &KsError) const = 0;
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/* /// Apply the \p Value for given \p Fixup into the provided data fragment, at
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/// the offset specified by the fixup and following the fixup kind as
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/// appropriate. Errors (such as an out of range fixup value) should be
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/// reported via \p Ctx.
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/// The \p STI is present only for fragments of type MCRelaxableFragment and
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/// MCDataFragment with hasInstructions() == true.
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virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI, unsigned int &KsError) const = 0; */
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/// @}
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@@ -310,7 +310,7 @@ enum {
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EM_NORC = 218, // Nanoradio Optimized RISC
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EM_CSR_KALIMBA = 219, // CSR Kalimba architecture family
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EM_AMDGPU = 224, // AMD GPU architecture
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EM_RISCV = 243, // RISC-V
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EM_RISCV = 243, // RISC-V
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// A request has been made to the maintainer of the official registry for
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// such numbers for an official value for WebAssembly. As soon as one is
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@@ -5,7 +5,6 @@
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#include "llvm/MC/LaneBitmask.h"
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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