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179 Commits
Author SHA1 Message Date
Samir Shetty 0d9567f08c Fix build compatibility with CMake 4, GCC 15, and MSVC (#600) 
* Support building with CMake 4

Adapted from https://github.com/NixOS/nixpkgs/pull/450265

* Support building with GCC 15

Adapted from https://github.com/NixOS/nixpkgs/pull/450265

* Fix building with MSVC

* RISCV: Add RegSize/Alignment fields to RISCVGenRegisterInfo.inc initializers

Keystone's MCRegisterClass retains the RegSize and Alignment fields from
the LLVM 4.0 era, before they were moved to TargetRegisterInfo in LLVM 5.0
(D31783) and eventually removed from MCRegisterClass entirely in LLVM 7.0
(rL339350).

The RISCV backend was ported from a newer LLVM snapshot where these fields
no longer existed, so RISCVGenRegisterInfo.inc was generated without them,
causing a member count mismatch against keystone's MCRegisterClass definition
and a compile error on MSVC (C3852).

Add the missing RegSize and Alignment values to each register class
initializer to match the layout expected by MCRegisterClass. The values
chosen reflect the natural register width of each class (4 bytes for FPR32,
8 bytes for all others). These fields are structurally required to satisfy
the initializer but are never consulted by the assembler — spill slot
calculations belong to the codegen layer which keystone does not include.

All other architectures in keystone were ported from pre-LLVM-5.0 and have
correct initializers. This change makes RISCV consistent with them.
 2026-07-18 17:28:10 -04:00
null-cell 2a611d9a8c adds documentation for porting, resolves PR comments 2023-05-15 11:05:31 +02:00
null-cell 796d0c0f35 cleanup and formatting 2023-03-28 14:09:12 +02:00
null-cell d973e0c0ce cleanup comments 2023-03-28 12:50:20 +02:00
null-cell d1eee1b6b1 adds support for relaxation, compression, code cleanup 2023-03-28 12:01:25 +02:00
null-cell 49b11315cc fixes required extensions per processor, adds procsched 2023-03-27 15:13:12 +02:00
null-cell 6efbce1a7a fixes FeatureBitset implemetation 2023-03-27 13:48:54 +02:00
null-cell 8700fab143 adds correct ABI selection for RISCV 2023-03-27 12:33:14 +02:00
null-cell d026e349d3 fixes runtime errors, first clean build that runs kstool correctly 2023-03-21 15:24:30 +01:00
null-cell 0dd179e142 compiles without errors 2023-03-21 10:30:56 +01:00
null-cell fca8bdd04b fixes most errors with FeatureBitset, bugfixes 2023-03-20 20:08:53 +01:00
null-cell e32e4aed6c port write statements, fix applyFixup and adjustFixupValue, bugfix 2023-03-20 11:02:36 +01:00
null-cell 7563c9fa50 adds RISCV e-flags and backports writeNopData 2023-03-17 14:33:54 +01:00
null-cell aa2ba719a8 backport createObjectWriter return type 2023-03-17 13:32:31 +01:00
null-cell 647c901717 change createObjectTargetWriter to createObjectWriter 2023-03-17 13:29:34 +01:00
null-cell 6b207adbeb overloads applyFixup with RISCV definition and extends KsError 2023-03-17 13:23:10 +01:00
null-cell c2e56b3f72 pruned RISCV.h, adds .inc files and fixes createRISCVELFObjectWriter 2023-03-17 13:19:28 +01:00
null-cell b45b16a725 edits config to support RISCV - known from v4 2023-03-16 17:29:33 +01:00
null-cell 29042efd2c removes unused files (disassembler, target lowering, ..) 2023-03-16 16:29:59 +01:00
null-cell 6190add45f adds RISCV compiled from LLVM 9.0.1 2023-03-16 16:18:41 +01:00
Saagar Jha 1475885daa Cherry-pick https://reviews.llvm.org/D25112 (#505) 
This fixes #504.
 2021-07-21 02:37:42 +08:00
jan2642 c0e77dea8d test+fix thumb backwards branching with sym_resolver (#355) (#377) 2020-06-13 13:16:55 +08:00
Edward Larson 4d060561fa Remove bounds check on ppc branch instructions target address (fix issue 423) (#428) 
(cherry picked from commit 06afb493e0)
 2020-02-15 08:18:12 +08:00
Michael Mohr 105761ffe7 Update the Python binding's Debian packaging to build for Python 3 (#442) 2019-11-22 09:15:38 +08:00
brendabrandy c4de98f71f Updated AsmParser deconstructor to restore saved diagnostic handlers back to srcmgr (#419) 2019-08-02 21:45:03 +08:00
Trey Keown 622fe09217 Fix ADRP instruction encoding (#396) 
* Fix ADRP instruction encoding

* Trigger checks on PR again, it failed for some reason unrelated to my code

* Add correct offset checks back in
 2019-01-21 17:03:23 +08:00
Catena cyber 2c1a40b495 Limit recursion in AsmParser::parsePrimaryExpr (#379) 2018-09-24 20:19:16 +08:00
Christian Sharpsten 4733bab91b Fix x86 instruction prefix ordering (#340) 
A REX prefix byte must immediately precede the opcode byte or the
opcode escape byte. Emit segment override and address size prefix
bytes before a REX prefix byte.
 2018-04-01 00:48:51 +08:00
Christian Sharpsten ae8d127e34 Fix spelling errors in libkeystone (#346) 2018-04-01 00:39:46 +08:00
Peter Matula 1815d79beb rename namespace "llvm" to "llvm_ks" (#333) 
This prevents symbol collisions when the Keystone library is linked with the LLVM libraries.

Renaming was done by the following repository-wide substitutions:
* `namespace llvm` -> `namespace llvm_ks`
* `llvm::` -> `llvm_ks::`
 2018-01-23 11:29:52 +08:00
Brian Kearns 5a874f6fd4 Test+fix ARM Thumb2 ADR calculations (#329) 2017-11-30 00:42:13 +08:00
Brian Kearns e7212da5a6 Test/fix ARM Thumb B.W addresses (#326) 
* add ARM Thumb branch address testcases

* fix ARM Thumb B.W addresses (issue #298)
 2017-11-30 00:20:52 +08:00
fidgetingbits c474c6c4b2 Fix issue #293 (#300) 2017-06-01 21:42:52 +08:00
xiaohuajiao 35accb128f fixed Mips 'jal imm' segmentation fault (#294) 2017-04-17 14:59:39 +08:00
noword 51ea7aff4e ARM64, fix issue for PC-relative offset (#291) 
b.cond/cbz/cbnz/tbz/tbnz/adrp
 2017-04-08 14:17:03 +08:00
Nguyen Anh Quynh f5bbdf6215 arm64: fix some warnings reported by MSVC 2017-03-13 20:54:34 +08:00
noword d97ece972b fix imm value in AArch64MCCodeEmitter::getLoadLiteralOpValue 
for issue #284
 2017-03-09 10:06:29 +08:00
noword 58916b5e2c ARM64(llvm): Disable range checking on instructions with a PC-relative offset (b/bl/cbz/cbnz/tbz/tbnz/ldr/ldrsw/prfm) 2017-03-07 10:06:01 +08:00
Jatin Kataria c513bef6f2 added support to get current fragment size in the streamer interface. This fixes the address update issue in case of directive emitting values in between instructions and breaking the follow up relative jumps 2017-01-16 16:53:50 -05:00
Nguyen Anh Quynh 1c95fb5ed4 arm: fix instruction address report in issue #257 2016-11-21 01:35:37 +08:00
Nguyen Anh Quynh 735d3fc4c7 arm: fix target address of BLX in Thumb mode (issue #248) 2016-10-15 12:06:20 +08:00
Nguyen Anh Quynh 605d67ace0 arm: fix target address of BLX (issue #248) 2016-10-13 22:16:17 +08:00
Nguyen Anh Quynh 308e70b7ba arm: fix target address of BL (issue #248) 2016-10-13 22:08:58 +08:00
Nguyen Anh Quynh 7623db887d support symbol resolving at run-time by adding new setup option KS_OPT_SYM_RESOLVER. see issue #244 2016-10-02 13:54:37 +08:00
Nguyen Anh Quynh eac9cc9d67 support new syntax RADIX16. see issue #11 2016-09-10 02:04:54 +08:00
Nguyen Anh Quynh f8a3eba08c handle hexa number with 0X prefix, not just 0x 2016-08-09 00:06:43 +08:00
Nguyen Anh Quynh 1074142c75 x86: handle loope & loopne 2016-07-26 14:09:55 +08:00
Nguyen Anh Quynh da566800d0 x86: fix issue #230 2016-07-26 14:03:24 +08:00
Nguyen Anh Quynh faf9451898 Revert "x86: sysret does not need REX prefix. this fixes issue #94" 
This reverts commit f18b6e19cc.
 2016-07-26 12:43:57 +08:00
Nguyen Anh Quynh ac83ba2295 cleanup 2016-07-19 18:04:08 +08:00