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git-svn-id: http://svn.purei.org/purei/trunk@137 b36208d7-6611-0410-8bec-b1987f11c4a2

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This commit is contained in:
jpd002 2007-03-28 00:43:39 +00:00
parent 794d99503a
commit 00bd1c1978
2 changed files with 91 additions and 0 deletions
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37
Source/MipsAssemblerDefinitions.cpp
View File

@ -45,6 +45,41 @@ namespace MipsAssemblerDefinitions
AssemblerFunctionType m_Assembler;
};
//RdRsRt Parser
//-----------------------------
struct RdRsRt
{
typedef void (CMIPSAssembler::*AssemblerFunctionType) (unsigned int, unsigned int, unsigned int);
RdRsRt(AssemblerFunctionType Assembler) :
m_Assembler(Assembler)
{
}
void operator ()(tokenizer<>& Tokens, tokenizer<>::iterator& itToken, CMIPSAssembler* pAssembler)
{
unsigned int nRT, nRS, nRD;
if(itToken == Tokens.end()) throw exception();
nRD = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
if(itToken == Tokens.end()) throw exception();
nRS = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
if(itToken == Tokens.end()) throw exception();
nRT = CMIPSAssembler::GetRegisterIndex((*(++itToken)).c_str());
if(nRT == -1) throw exception();
if(nRS == -1) throw exception();
if(nRD == -1) throw exception();
bind(m_Assembler, pAssembler, _1, _2, _3)(nRD, nRS, nRT);
}
AssemblerFunctionType m_Assembler;
};
//RtImm Parser
//-----------------------------
struct RtImm
@ -134,6 +169,7 @@ namespace MipsAssemblerDefinitions
SpecInstruction<RtRsImm> Instruction_ADDIU = SpecInstruction<RtRsImm>("ADDIU", RtRsImm(&CMIPSAssembler::ADDIU));
SpecInstruction<RtImm> Instruction_LUI = SpecInstruction<RtImm>("LUI", RtImm(&CMIPSAssembler::LUI));
SpecInstruction<RtRsSa> Instruction_SLL = SpecInstruction<RtRsSa>("SLL", RtRsSa(&CMIPSAssembler::SLL));
SpecInstruction<RdRsRt> Instruction_SLTU = SpecInstruction<RdRsRt>("SLTU", RdRsRt(&CMIPSAssembler::SLTU));
SpecInstruction<RtRsSa> Instruction_SRA = SpecInstruction<RtRsSa>("SRA", RtRsSa(&CMIPSAssembler::SRA));
Instruction* g_Instructions[] =
@ -141,6 +177,7 @@ namespace MipsAssemblerDefinitions
&Instruction_ADDIU,
&Instruction_LUI,
&Instruction_SLL,
&Instruction_SLTU,
&Instruction_SRA,
NULL,
};

54
tests/SLTU.xml Normal file
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@ -0,0 +1,54 @@
<Test>
<Inputs>
<!-- Less Than -->
<ValueSet InputId="0">
<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T1" Value0="0x00000001" />
</ValueSet>
<!-- Greater Than -->
<ValueSet InputId="1">
<Register Name="T0" Value0="0x00000001" />
<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
</ValueSet>
<!-- Equal -->
<ValueSet InputId="2">
<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
</ValueSet>
</Inputs>
<Instances>
<Instance Id="0">
SLTU T2, T1, T0
</Instance>
</Instances>
<Outputs>
<ValueSet InputId="0" InstanceId="0">
<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T1" Value0="0x00000001" />
<Register Name="T2" Value0="0x00000001" />
</ValueSet>
<ValueSet InputId="1" InstanceId="0">
<Register Name="T0" Value0="0x00000001" />
<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T2" Value0="0x00000000" />
</ValueSet>
<ValueSet InputId="2" InstanceId="0">
<Register Name="T0" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T1" Value0="0xFFFFFFFF" Value1="0xFFFFFFFF"/>
<Register Name="T2" Value0="0x00000000" />
</ValueSet>
</Outputs>
</Test>