mame-memory: leave read-only banks of 1 MiB or more out of the save state (#2178)

register_banks() registers the RAM behind every bank that appears in a
memory map. Banks that only ever show up in read maps are ROM (the ST-V
cartridge bank, 48 MB, or the CAGE sound-board ROM banks, 2 + 16 MB),
but they were still copied into every save state, so states were
20-53 MB for those boards, and netplay, rewind and run-ahead keep many
states at once.

Remember whether each bank appears in a write map and skip a bank of
0x100000 bytes or more that never does. RAM banks and smaller banks are
unchanged, so the state layout of other drivers stays the same. An INFO
log line reports each skipped bank.

Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>

src/mame-memory.c

@@ -1641,11 +1641,13 @@ void register_banks(void)
 	int cpunum, i;
 	int banksize[MAX_BANKS];
 	int bankcpu[MAX_BANKS];
+	int bankwrite[MAX_BANKS]; /* bank appears in a write map */
 
 	for (i=0; i<MAX_BANKS; i++)
 	{
 		banksize[i] = 0;
 		bankcpu[i] = -1;
+		bankwrite[i] = 0;
 	}
 
 	/* loop over CPUs */
@@ -1726,6 +1728,7 @@ void register_banks(void)
 						if (banksize[HANDLER_TO_BANK(h)] < size)
 							banksize[HANDLER_TO_BANK(h)] = size;
 						bankcpu[HANDLER_TO_BANK(h)] = cpunum;
+						bankwrite[HANDLER_TO_BANK(h)] = 1;
 						mode = RG_DROP_WRITE;;
 					}
 					else
@@ -1770,6 +1773,14 @@ void register_banks(void)
 
 	for (i=0; i<MAX_BANKS; i++)
 		if (banksize[i])
+		{
+			/* a large bank that no write map touches is ROM (ST-V cart 48MB, CAGE sound ROM 18MB).
+			   Its bytes never change, so keep them out of the save state (netplay keeps dozens of states). */
+			if (!bankwrite[i] && banksize[i] >= 0x100000)
+			{
+				log_cb(RETRO_LOG_INFO, LOGPRE "read-only bank %d (%d bytes) left out of the save state\n", i, banksize[i]);
+				continue;
+			}
 			switch (cpunum_databus_width(bankcpu[i]))
 			{
 			case 8:
@@ -1782,6 +1793,7 @@ void register_banks(void)
 				state_save_register_UINT32("bank", i, "ram", (UINT32 *)cpu_bankbase[i], banksize[i]/4);
 				break;
 			}
+		}
 
 }