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zanacandClaude Opus 5.5
34988bc120
Replaces the old namcos22 driver (no DSPs, every game not working) with a C89 backport of the current MAME driver: - new Namco C71 core (TMS320C25 with internal ROM) for the master and slave DSPs: MAME's tms320c2x instructions, a page table memory system; - Super System 22 (68EC020, M37710 MCU with C352 and MB87078 volume) and System 22 (68020, C74 MCU with internal BIOS); - the video: display list simulation, z-sorted polygons and sprites, text layer, fog, fades, alpha, spot RAM, gamma; MAME's rasterizer rules, single threaded, with 1/z every 8 pixels and fast paths; - the "Threaded Video" option (was "ST-V Threaded Video") draws the frame in bands on 2 to 4 threads (3D scene, text layer, mix, gamma), same picture; - M37710: timer A event counters count up or down (output pin or up/down register, as MAME), for the Prop Cycle pedal and the Armadillo Racing trackball; - C352: optional routing of the four outputs to the stereo stream (rear speakers, cabinet speakers), as current MAME maps them to stereo; off unless a driver asks for it, System 11/12 unchanged; - game I/O as MAME: driving games and Cyber Commando on System 22, Alpine Racer steplock motor, Alpine Surfer ROM banking, Armadillo Racing trackball, default EEPROMs. System 22 sets (namcoc74 BIOS): ridgerac, ridgeraca, ridgeracb, ridgeracc, ridgeracj, ridgera2, ridgera2j, ridgera2ja, ridgera28, cybrcomm, raverace, raveracej, raveraceja, acedrive, victlap, victlapa, victlapj. Super System 22 sets: alpinerd, alpinerc, alpinerjc, airco22b, cybrcycc, cybrcyccj, dirtdash, dirtdasha, dirtdashb, dirtdashj, timecris, timecrisa, timecrisj, propcycl, propcyclj, alpines, tokyowar, tokyowarj, aquajet, alpinr2b, alpinr2a, adillor, adillorj. Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX Co-authored-by: Claude Opus 5.5 <[email protected]>
76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/***************************************************************************
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Namco C71 (TMS320C25 with Namco internal ROM) - fast DSP core
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Written for Namco System 22 / Super System 22. The instruction
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semantics follow the TMS320C2x core of current MAME; the memory
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system is a page table set up by the driver, so the core does not
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go through the generic memory handlers.
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Word addresses everywhere: program, data and I/O are 16-bit word
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spaces.
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***************************************************************************/
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#ifndef C71_H
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#define C71_H
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#include "osd_cpu.h"
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#include "cpuintrf.h"
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#include "memory.h"
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/* interrupt lines (IFR bits) */
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#define C71_INT0 0
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#define C71_INT1 1
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#define C71_INT2 2
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#define C71_TINT 3
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#define C71_RINT 4
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#define C71_XINT 5
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enum
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{
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C71_PC=1,
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C71_PFC, C71_STR0, C71_STR1, C71_IFR,
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C71_RPTC, C71_ACC, C71_PREG, C71_TREG,
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C71_AR0, C71_AR1, C71_AR2, C71_AR3,
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C71_AR4, C71_AR5, C71_AR6, C71_AR7,
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C71_STK0, C71_STK1, C71_STK2, C71_STK3,
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C71_STK4, C71_STK5, C71_STK6, C71_STK7,
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C71_DRR, C71_DXR, C71_TIM, C71_PRD,
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C71_IMR, C71_GREG
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};
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/* the generic memory interface is not used: give the CPU empty maps */
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#define NAMCOC71_PGM_OFFSET 0
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typedef data16_t (*c71_read_fn)(offs_t offset);
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typedef void (*c71_write_fn)(offs_t offset, data16_t data);
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/* driver configuration, by CPU number; call from DRIVER_INIT or MACHINE_INIT */
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void c71_set_internal_rom(int cpunum, const data16_t *rom); /* 0x1000 words, native order (a CPU region) */
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void c71_map_data(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
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void c71_map_program(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
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void c71_set_data_handlers(int cpunum, c71_read_fn rd, c71_write_fn wr); /* everything not mapped */
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void c71_set_io(int cpunum, int port, c71_read_fn rd, c71_write_fn wr);
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void c71_set_bio(int cpunum, int (*bio)(void));
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void c71_set_serial(int cpunum, data16_t (*dr_in)(void), void (*dx_out)(data16_t));
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/* the DSP spins in [pc_start, pc_end] waiting for BIO or an interrupt: burn the timeslice there */
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void c71_set_idle_loop(int cpunum, int slot, UINT16 pc_start, UINT16 pc_end);
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extern int c71_icount;
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void c71_init(void);
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void c71_reset(void *param);
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void c71_exit(void);
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int c71_execute(int cycles);
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unsigned c71_get_context(void *dst);
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void c71_set_context(void *src);
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unsigned c71_get_reg(int regnum);
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void c71_set_reg(int regnum, unsigned val);
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void c71_set_irq_line(int irqline, int state);
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void c71_set_irq_callback(int (*callback)(int irqline));
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const char *c71_info(void *context, int regnum);
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unsigned c71_dasm(char *buffer, unsigned pc);
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#endif
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