Namco System 22 / Super System 22 from current MAME (#2206)

Replaces the old namcos22 driver (no DSPs, every game not working) with a
C89 backport of the current MAME driver:

- new Namco C71 core (TMS320C25 with internal ROM) for the master and
  slave DSPs: MAME's tms320c2x instructions, a page table memory system;
- Super System 22 (68EC020, M37710 MCU with C352 and MB87078 volume) and
  System 22 (68020, C74 MCU with internal BIOS);
- the video: display list simulation, z-sorted polygons and sprites,
  text layer, fog, fades, alpha, spot RAM, gamma; MAME's rasterizer
  rules, single threaded, with 1/z every 8 pixels and fast paths;
- the "Threaded Video" option (was "ST-V Threaded Video") draws the
  frame in bands on 2 to 4 threads (3D scene, text layer, mix, gamma),
  same picture;
- M37710: timer A event counters count up or down (output pin or up/down
  register, as MAME), for the Prop Cycle pedal and the Armadillo Racing
  trackball;
- C352: optional routing of the four outputs to the stereo stream (rear
  speakers, cabinet speakers), as current MAME maps them to stereo; off
  unless a driver asks for it, System 11/12 unchanged;
- game I/O as MAME: driving games and Cyber Commando on System 22,
  Alpine Racer steplock motor, Alpine Surfer ROM banking, Armadillo
  Racing trackball, default EEPROMs.

System 22 sets (namcoc74 BIOS): ridgerac, ridgeraca, ridgeracb,
ridgeracc, ridgeracj, ridgera2, ridgera2j, ridgera2ja, ridgera28,
cybrcomm, raverace, raveracej, raveraceja, acedrive, victlap, victlapa,
victlapj.

Super System 22 sets: alpinerd, alpinerc, alpinerjc, airco22b, cybrcycc,
cybrcyccj, dirtdash, dirtdasha, dirtdashb, dirtdashj, timecris,
timecrisa, timecrisj, propcycl, propcyclj, alpines, tokyowar, tokyowarj,
aquajet, alpinr2b, alpinr2a, adillor, adillorj.


Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX

Co-authored-by: Claude Opus 5.5 <[email protected]>

Makefile.common

@@ -172,6 +172,7 @@ CPUS+=TMS9995@
 CPUS+=Z8000@
 CPUS+=TMS32010@
 CPUS+=TMS32025@
+CPUS+=NAMCOC71@
 CPUS+=TMS32031@
 CPUS+=I960@
 CPUS+=MB86233@
@@ -1866,6 +1867,15 @@ else
 CPUDEFS += -DHAS_TMS32010=0
 endif
 
+CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
+ifneq ($(CPU),)
+OBJDIRS += $(CORE_DIR)/cpu/namcoc71
+CPUDEFS += -DHAS_NAMCOC71=1
+SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
+else
+CPUDEFS += -DHAS_NAMCOC71=0
+endif
+
 CPU=$(strip $(findstring TMS32025@,$(CPUS)))
 ifneq ($(CPU),)
 OBJDIRS += $(CORE_DIR)/cpu/tms32025

Makefile.split

@@ -1821,6 +1821,15 @@ else
 CPUDEFS += -DHAS_TMS32010=0
 endif
 
+CPU=$(strip $(findstring NAMCOC71@,$(CPUS)))
+ifneq ($(CPU),)
+OBJDIRS += $(CORE_DIR)/cpu/namcoc71
+CPUDEFS += -DHAS_NAMCOC71=1
+SOURCES_C += $(CORE_DIR)/cpu/namcoc71/c71.c
+else
+CPUDEFS += -DHAS_NAMCOC71=0
+endif
+
 CPU=$(strip $(findstring TMS32025@,$(CPUS)))
 ifneq ($(CPU),)
 OBJDIRS += $(CORE_DIR)/cpu/tms32025

src/cpu/m37710/m37710.c

@@ -413,6 +413,9 @@ static void m37710_timer_b2_cb(int param)
 	cpuintrf_pop_context();
 }
 
+/* timer A output pins (set by the driver just before it clocks the timer, not saved) */
+static int m37710_timer_out[5];
+
 static void m37710_external_tick(int timer, int state)
 {
 	/* we only care if the state is "on" */
@@ -426,15 +429,22 @@ static void m37710_external_tick(int timer, int state)
 	{
 		if ((m37710i_cpu.m37710_regs[0x56+timer] & 0x3) == 1)
 		{
-			if (m37710i_cpu.m37710_regs[0x46+(timer*2)] == 0xff)
+			/* the count direction, as current MAME: timer B counts down; timer A
+			   follows its output pin (mode bit 4) or the up/down register */
+			int upcount = 0;
+			UINT16 count = m37710i_cpu.m37710_regs[0x46+(timer*2)] | (m37710i_cpu.m37710_regs[0x46+(timer*2)+1] << 8);
+
+			if (timer <= 4)
 			{
-				m37710i_cpu.m37710_regs[0x46+(timer*2)] = 0;
-				m37710i_cpu.m37710_regs[0x46+(timer*2)+1]++;
-			}
-			else
-			{
-				m37710i_cpu.m37710_regs[0x46+(timer*2)]++;
+				if (m37710i_cpu.m37710_regs[0x56+timer] & 0x10)
+					upcount = m37710_timer_out[timer];
+				else
+					upcount = (m37710i_cpu.m37710_regs[0x44] >> timer) & 1;
 			}
+
+			count = upcount ? count + 1 : count - 1;
+			m37710i_cpu.m37710_regs[0x46+(timer*2)] = count & 0xff;
+			m37710i_cpu.m37710_regs[0x46+(timer*2)+1] = count >> 8;
 		}
 		else
 		{
@@ -1086,6 +1096,11 @@ void m37710_set_irq_line(int line, int state)
 		m37710_external_tick(line - M37710_LINE_TIMERA0TICK, state);
 		return;
 	}
+	if (line >= M37710_LINE_TIMERA0OUT && line <= M37710_LINE_TIMERA4OUT)
+	{
+		m37710_timer_out[line - M37710_LINE_TIMERA0OUT] = (state != CLEAR_LINE);
+		return;
+	}
 	FTABLE_SET_LINE(line, state);
 }
 

src/cpu/m37710/m37710.h

@@ -63,6 +63,13 @@ enum
 	M37710_LINE_TIMERB1TICK,
 	M37710_LINE_TIMERB2TICK,
 
+	/* timer A output pins: the count direction of an event counter in up/down pin mode */
+	M37710_LINE_TIMERA0OUT,
+	M37710_LINE_TIMERA1OUT,
+	M37710_LINE_TIMERA2OUT,
+	M37710_LINE_TIMERA3OUT,
+	M37710_LINE_TIMERA4OUT,
+
 	M37710_LINE_MAX
 };
 

src/cpu/namcoc71/c71.h

@@ -0,0 +1,75 @@
+/***************************************************************************
+
+    Namco C71 (TMS320C25 with Namco internal ROM) - fast DSP core
+
+    Written for Namco System 22 / Super System 22. The instruction
+    semantics follow the TMS320C2x core of current MAME; the memory
+    system is a page table set up by the driver, so the core does not
+    go through the generic memory handlers.
+
+    Word addresses everywhere: program, data and I/O are 16-bit word
+    spaces.
+
+***************************************************************************/
+
+#ifndef C71_H
+#define C71_H
+
+#include "osd_cpu.h"
+#include "cpuintrf.h"
+#include "memory.h"
+
+/* interrupt lines (IFR bits) */
+#define C71_INT0		0
+#define C71_INT1		1
+#define C71_INT2		2
+#define C71_TINT		3
+#define C71_RINT		4
+#define C71_XINT		5
+
+enum
+{
+	C71_PC=1,
+	C71_PFC,  C71_STR0, C71_STR1, C71_IFR,
+	C71_RPTC, C71_ACC,  C71_PREG, C71_TREG,
+	C71_AR0,  C71_AR1,  C71_AR2,  C71_AR3,
+	C71_AR4,  C71_AR5,  C71_AR6,  C71_AR7,
+	C71_STK0, C71_STK1, C71_STK2, C71_STK3,
+	C71_STK4, C71_STK5, C71_STK6, C71_STK7,
+	C71_DRR,  C71_DXR,  C71_TIM,  C71_PRD,
+	C71_IMR,  C71_GREG
+};
+
+/* the generic memory interface is not used: give the CPU empty maps */
+#define NAMCOC71_PGM_OFFSET 0
+
+typedef data16_t (*c71_read_fn)(offs_t offset);
+typedef void (*c71_write_fn)(offs_t offset, data16_t data);
+
+/* driver configuration, by CPU number; call from DRIVER_INIT or MACHINE_INIT */
+void c71_set_internal_rom(int cpunum, const data16_t *rom);		/* 0x1000 words, native order (a CPU region) */
+void c71_map_data(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
+void c71_map_program(int cpunum, offs_t start, offs_t end, data16_t *base, int writable);
+void c71_set_data_handlers(int cpunum, c71_read_fn rd, c71_write_fn wr);	/* everything not mapped */
+void c71_set_io(int cpunum, int port, c71_read_fn rd, c71_write_fn wr);
+void c71_set_bio(int cpunum, int (*bio)(void));
+void c71_set_serial(int cpunum, data16_t (*dr_in)(void), void (*dx_out)(data16_t));
+/* the DSP spins in [pc_start, pc_end] waiting for BIO or an interrupt: burn the timeslice there */
+void c71_set_idle_loop(int cpunum, int slot, UINT16 pc_start, UINT16 pc_end);
+
+extern int c71_icount;
+
+void c71_init(void);
+void c71_reset(void *param);
+void c71_exit(void);
+int c71_execute(int cycles);
+unsigned c71_get_context(void *dst);
+void c71_set_context(void *src);
+unsigned c71_get_reg(int regnum);
+void c71_set_reg(int regnum, unsigned val);
+void c71_set_irq_line(int irqline, int state);
+void c71_set_irq_callback(int (*callback)(int irqline));
+const char *c71_info(void *context, int regnum);
+unsigned c71_dasm(char *buffer, unsigned pc);
+
+#endif

src/cpuintrf.c

@@ -124,6 +124,9 @@
 #if (HAS_TMS32025)
 #include "cpu/tms32025/tms32025.h"
 #endif
+#if (HAS_NAMCOC71)
+#include "cpu/namcoc71/c71.h"
+#endif
 #if (HAS_I960)
 #include "cpu/i960/i960.h"
 #endif
@@ -573,6 +576,10 @@ const struct cpu_interface cpuintrf[] =
 #if (HAS_TMS32025)
 	CPU3(TMS32025,tms32025,  3,  0,1.00,16,18bew, -1,18,BE,2, 4	),
 #endif
+#if (HAS_NAMCOC71)
+	#define c71_ICount c71_icount
+	CPU0(NAMCOC71, c71,      6,  0,1.00,16,16bew, -1,16,BE,2, 4	),
+#endif
 #if (HAS_TMS32031)
 	#define tms32031_ICount tms32031_icount
 	CPU0(TMS32031,tms32031,  4,  0,1.00,32,26ledw,-2,26,LE,4, 4 ),

src/cpuintrf.h

@@ -235,6 +235,9 @@ enum
 #if (HAS_TMS32025)
 	CPU_TMS32025,
 #endif
+#if (HAS_NAMCOC71)
+	CPU_NAMCOC71,
+#endif
 #if (HAS_TMS32031)
 	CPU_TMS32031,
 #endif

src/driver.c

@@ -748,18 +748,49 @@ const struct GameDriver *test_drivers[] =
 	DRIVER( cybsled )	/* (c) 1993 */
 
 	/* Namco System 22 games */
+	DRIVER( namcoc74 )	/* C74 BIOS */
+	DRIVER( ridgerac )	/* (c) 1993 */
+	DRIVER( ridgeraca )	/* (c) 1993 */
+	DRIVER( ridgeracb )	/* (c) 1993 */
+	DRIVER( ridgeracc )	/* (c) 1993 */
+	DRIVER( ridgeracj )	/* (c) 1993 */
+	DRIVER( ridgera2 )	/* (c) 1994 */
+	DRIVER( ridgera2j )	/* (c) 1994 */
+	DRIVER( ridgera2ja )	/* (c) 1994 */
+	DRIVER( ridgera28 )	/* (c) 1994 */
+	DRIVER( cybrcomm )	/* (c) 1994 */
+	DRIVER( raverace )	/* (c) 1995 */
+	DRIVER( raveracej )	/* (c) 1995 */
+	DRIVER( raveraceja )	/* (c) 1995 */
+	DRIVER( acedrive )	/* (c) 1994 */
+	DRIVER( victlap )	/* (c) 1996 */
+	DRIVER( victlapa )	/* (c) 1996 */
+	DRIVER( victlapj )	/* (c) 1996 */
+
+	/* Namco Super System 22 games */
 	DRIVER( alpinerd )	/* (c) 1994 */
 	DRIVER( alpinerc )	/* (c) 1994 */
-	DRIVER( raveracw )	/* (c) 1995 */
-	DRIVER( ridgeraj )
-	DRIVER( ridger2j )
-	DRIVER( acedrvrw )
-	DRIVER( victlapw )
-	DRIVER( cybrcomm )
-	DRIVER( airco22b )
-	DRIVER( cybrcycc )
-	DRIVER( timecrsa )
+	DRIVER( alpinerjc )	/* (c) 1994 */
+	DRIVER( airco22b )	/* (c) 1995 */
+	DRIVER( cybrcycc )	/* (c) 1995 */
+	DRIVER( cybrcyccj )	/* (c) 1995 */
+	DRIVER( dirtdash )	/* (c) 1995 */
+	DRIVER( dirtdasha )	/* (c) 1995 */
+	DRIVER( dirtdashb )	/* (c) 1995 */
+	DRIVER( dirtdashj )	/* (c) 1995 */
+	DRIVER( timecris )	/* (c) 1996 */
+	DRIVER( timecrisa )	/* (c) 1996 */
+	DRIVER( timecrisj )	/* (c) 1996 */
 	DRIVER( propcycl )	/* (c) 1996 */
+	DRIVER( propcyclj )	/* (c) 1996 */
+	DRIVER( alpines )	/* (c) 1996 */
+	DRIVER( tokyowar )	/* (c) 1996 */
+	DRIVER( tokyowarj )	/* (c) 1996 */
+	DRIVER( aquajet )	/* (c) 1996 */
+	DRIVER( alpinr2b )	/* (c) 1996 */
+	DRIVER( alpinr2a )	/* (c) 1996 */
+	DRIVER( adillor )	/* (c) 1997 */
+	DRIVER( adillorj )	/* (c) 1997 */
 
 
 	/* Universal games */

src/includes/namcos22.h

@@ -1,7 +1,16 @@
-#include "driver.h"
-#include "vidhrdw/generic.h"
+/***************************************************************************
 
-extern enum namcos22_gametype
+    Namco System 22 / Super System 22
+
+    Backported from current MAME (Phil Stroffolino, hap, R. Belmont and
+    others, BSD-3-Clause).
+
+***************************************************************************/
+
+#ifndef NAMCOS22_H
+#define NAMCOS22_H
+
+enum
 {
 	NAMCOS22_AIR_COMBAT22,
 	NAMCOS22_ALPINE_RACER,
@@ -10,38 +19,70 @@ extern enum namcos22_gametype
 	NAMCOS22_PROP_CYCLE,
 	NAMCOS22_RAVE_RACER,
 	NAMCOS22_RIDGE_RACER,
+	NAMCOS22_RIDGE_RACER2,
 	NAMCOS22_TIME_CRISIS,
 	NAMCOS22_VICTORY_LAP,
-	NAMCOS22_ACE_DRIVER
-} namcos22_gametype;
+	NAMCOS22_ACE_DRIVER,
+	NAMCOS22_ALPINE_RACER_2,
+	NAMCOS22_ALPINE_SURFER,
+	NAMCOS22_TOKYO_WARS,
+	NAMCOS22_AQUA_JET,
+	NAMCOS22_DIRT_DASH,
+	NAMCOS22_ARMADILLO_RACING
+};
 
-#define NAMCOS22_NUM_ROWS 30
-#define NAMCOS22_NUM_COLS 40
-#define NAMCOS22_ALPHA_GFX 1
+/* big endian views of the 32-bit RAMs (stored as native data32_t) */
+#define NTHBYTE32(base, n)	(((base)[(n) >> 2] >> (8 * (~(n) & 3))) & 0xff)
+#define NTHWORD32(base, n)	(((base)[(n) >> 1] >> (16 * (~(n) & 1))) & 0xffff)
 
-#define NAMCOS22_PALETTE_SIZE 0x8000
+#define SIGNED12(v)	((INT32)((UINT32)(v) << 20) >> 20)
+#define SIGNED18(v)	((INT32)((UINT32)(v) << 14) >> 14)
+#define SIGNED24(v)	((INT32)((UINT32)(v) << 8) >> 8)
 
-extern data32_t *namcos22_cgram;
-extern data32_t *namcos22_textram;
-extern data32_t *namcos22_polygonram;
-extern data32_t *namcos22_gamma;
-
-READ32_HANDLER( namcos22_cgram_r );
-WRITE32_HANDLER( namcos22_cgram_w );
-
-READ32_HANDLER( namcos22_paletteram_r );
-WRITE32_HANDLER( namcos22_paletteram_w );
-
-READ32_HANDLER( namcos22_textram_r );
-WRITE32_HANDLER( namcos22_textram_w );
-
-READ32_HANDLER( namcos22_gamma_r );
-WRITE32_HANDLER( namcos22_gamma_w );
-
-READ32_HANDLER( namcos22_dspram_r );
-WRITE32_HANDLER( namcos22_dspram_w );
-
-VIDEO_UPDATE( namcos22 );
+/* drivers/namcos22.c */
+extern int namcos22_gametype;
+extern int namcos22_is_ss22;
+extern data32_t *namcos22_polygonram;		/* 0x8000 dwords, 24 bits connected */
+extern data32_t *namcos22_spriteram;
+extern data32_t *namcos22_vics_data;
+extern data32_t *namcos22_vics_control;
+extern data32_t *namcos22_mixer;
+extern data32_t *namcos22_paletteram;
+extern data32_t *namcos22_cgram;			/* text layer tiles; the tilemap is at 0x1e000 */
+extern data32_t *namcos22_czram;			/* System 22 */
+extern data16_t *namcos22_shareram;
+extern data8_t *namcos22_gamma_proms;		/* System 22 */
+extern int namcos22_pdp_render_done;
+extern int namcos22_render_refresh;
+extern int namcos22_slave_simulation_active;
+extern UINT32 namcos22_pdp_frame;
+extern INT32 namcos22_point_read(offs_t offs);
+extern void namcos22_pdp_handle_commands(UINT16 offs);
+extern UINT8 namcos22_syscontrol[0x20];
+extern int namcos22_irq_enabled, namcos22_irq_state;
 
+/* vidhrdw/namcos22_vidhrdw.c */
 VIDEO_START( namcos22s );
+VIDEO_START( namcos22 );
 VIDEO_UPDATE( namcos22s );
+VIDEO_UPDATE( namcos22 );
+VIDEO_STOP( namcos22 );
+int namcos22_video_threads_available(void);
+void namcos22_video_reset(void);
+void namcos22_draw_direct_poly(const UINT16 *src);
+
+WRITE32_HANDLER( namcos22_paletteram_w );
+WRITE32_HANDLER( namcos22_cgram_w );
+READ32_HANDLER( namcos22_tilemapattr_r );
+WRITE32_HANDLER( namcos22_tilemapattr_w );
+READ32_HANDLER( namcos22s_czattr_r );
+WRITE32_HANDLER( namcos22s_czattr_w );
+READ32_HANDLER( namcos22s_czram_r );
+WRITE32_HANDLER( namcos22s_czram_w );
+READ32_HANDLER( namcos22s_spotram_r );
+WRITE32_HANDLER( namcos22s_spotram_w );
+READ32_HANDLER( namcos22s_vics_control_r );
+WRITE32_HANDLER( namcos22s_vics_control_w );
+WRITE32_HANDLER( namcos22s_chipselect_w );
+
+#endif

src/mame.h

@@ -229,7 +229,7 @@ struct GameOptions
   bool     sh3_dynarec;	       /* 1 to let drivers enable the SH-3 recompiler */
   int      tx1_screens;	       /* TX-1 / Buggy Boy: 3 screens side by side, or 1 (the middle one) */
   bool     sh2_dynarec;	       /* 1 to let drivers enable the SH-2 recompiler */
-  int      stv_video_threads;    /* ST-V: threads drawing the VDP2 screen in bands (0 or 1 = the main thread only) */
+  int      stv_video_threads;    /* ST-V, Namco System 22: threads drawing the screen in bands (0 or 1 = the main thread only) */
   bool     use_alt_sound;	       /* 1 to enable alternate ost samples */
 
   float	   brightness;		       /* brightness of the display */

src/mame2003/core_options.c

@@ -817,9 +817,9 @@ static struct retro_core_option_v2_definition option_def_sh2_dynarec = {
 
 static struct retro_core_option_v2_definition option_def_stv_video_threads = {
    APPNAME"_stv_video_threads",
-   "ST-V Threaded Video",
+   "Threaded Video",
    NULL,
-   "Draw the ST-V screen in horizontal bands on several threads (same picture, faster on multi-core hosts).",
+   "ST-V and Namco System 22: draw the screen in horizontal bands on several threads (same picture, faster on multi-core hosts).",
    NULL,
    NULL,
    {
@@ -1654,6 +1654,13 @@ void set_content_flags(void)
       options.content_flags[CONTENT_STV_VIDEO_THREADS] = true;
   }
 #endif
+#if (HAS_NAMCOC71)
+  {
+    extern int namcos22_video_threads_available(void);
+    if (game_driver->source_file && strstr(game_driver->source_file, "namcos22.c") && namcos22_video_threads_available())
+      options.content_flags[CONTENT_STV_VIDEO_THREADS] = true;
+  }
+#endif
 
   /************ DRIVERS WITH MULTIPLE BIOS OPTIONS ************/
 #ifndef SPLIT_CORE

src/sound/c352.c

@@ -18,7 +18,8 @@
 
     mame2003-plus: backported from current MAME (c352.cpp) to the 0.78
     sound interface.  Only the front (L/R) outputs are mixed, as on
-    System 12 where the second DAC is not populated.
+    System 12 where the second DAC is not populated, unless the driver
+    asks for a routing of the four outputs (c352_set_routing).
 */
 
 #include <stddef.h>
@@ -177,12 +178,94 @@ static INLINE INT16 c352_clamp(int val)
 	return val;
 }
 
+/* optional four output routing (see c352.h); set before the sound starts */
+static int c352_route_pending[4][2];
+static int c352_routed;
+static int c352_route[4][2];
+static int c352_gain[4];
+
+void c352_set_routing(const int route[4][2])
+{
+	memcpy(c352_route_pending, route, sizeof(c352_route_pending));
+}
+
+void c352_set_output_gain(int output, int gain)
+{
+	if (output < 0 || output > 3)
+		return;
+	if (c352.stream)
+		stream_update(c352.stream, 0);
+	c352_gain[output] = gain;
+}
+
+static void c352_update_routed(INT16 **buffer, int length)
+{
+	INT16 *bufl = buffer[0];
+	INT16 *bufr = buffer[1];
+	int i, j, n;
+
+	for (i = 0; i < length; i++)
+	{
+		int out[4] = { 0, 0, 0, 0 };
+		int l = 0, r = 0;
+
+		for (j = 0; j < 32; j++)
+		{
+			c352_voice_t *v = &c352.v[j];
+			INT16 s = 0;
+
+			if (V_FLAGS(v) & C352_FLG_BUSY)
+			{
+				INT32 next_counter = v->counter + V_FREQ(v);
+
+				if (next_counter & 0x10000)
+					c352_fetch_sample(v);
+
+				if ((next_counter ^ v->counter) & 0x18000)
+				{
+					c352_ramp_volume(v, 0, V_VOL_F(v) >> 8);
+					c352_ramp_volume(v, 1, V_VOL_F(v) & 0xff);
+					c352_ramp_volume(v, 2, V_VOL_R(v) >> 8);
+					c352_ramp_volume(v, 3, V_VOL_R(v) & 0xff);
+				}
+
+				v->counter = next_counter & 0xffff;
+
+				s = v->sample;
+
+				if ((V_FLAGS(v) & C352_FLG_FILTER) == 0)
+					s = v->last_sample + (INT32)(((INT64)v->counter * (v->sample - v->last_sample)) >> 16);
+			}
+
+			out[0] += (((V_FLAGS(v) & C352_FLG_PHASEFL) ? -s : s) * v->curr_vol[0]) >> 8;
+			out[2] += (((V_FLAGS(v) & C352_FLG_PHASERL) ? -s : s) * v->curr_vol[2]) >> 8;
+			out[1] += (((V_FLAGS(v) & C352_FLG_PHASEFR) ? -s : s) * v->curr_vol[1]) >> 8;
+			out[3] += (((V_FLAGS(v) & C352_FLG_PHASEFR) ? -s : s) * v->curr_vol[3]) >> 8;
+		}
+
+		for (n = 0; n < 4; n++)
+		{
+			int o = (c352_clamp(out[n] >> 3) * c352_gain[n]) >> 8;
+			l += o * c352_route[n][0];
+			r += o * c352_route[n][1];
+		}
+		bufl[i] = c352_clamp(l >> 8);
+		bufr[i] = c352_clamp(r >> 8);
+	}
+}
+
 static void c352_update(int param, INT16 **buffer, int length)
 {
 	INT16 *bufl = buffer[0];
 	INT16 *bufr = buffer[1];
 	int i, j;
 
+	if (c352_routed)
+	{
+		c352_update_routed(buffer, length);
+		return;
+	}
+
 	for (i = 0; i < length; i++)
 	{
 		int out[2] = { 0, 0 };
@@ -301,6 +384,17 @@ int C352_sh_start(const struct MachineSound *msound)
 
 	memset(&c352, 0, sizeof(c352));
 
+	/* the routing asked by this driver, if any; the next game starts without */
+	memcpy(c352_route, c352_route_pending, sizeof(c352_route));
+	memset(c352_route_pending, 0, sizeof(c352_route_pending));
+	c352_routed = 0;
+	for (i = 0; i < 4; i++)
+	{
+		c352_gain[i] = 0x100;
+		if (c352_route[i][0] || c352_route[i][1])
+			c352_routed = 1;
+	}
+
 	vol[0] = MIXER(intf->mixing_level, MIXER_PAN_LEFT);
 	vol[1] = MIXER(intf->mixing_level, MIXER_PAN_RIGHT);
 

src/sound/c352.h

@@ -15,6 +15,15 @@ struct C352interface
 	int mixing_level;	/* master volume */
 };
 
+/* Optional mixing of the four outputs (front left, front right, rear left,
+   rear right) into the stereo stream, as current MAME maps a cabinet's extra
+   speakers to stereo. Call before the sound starts (DRIVER_INIT); without it
+   only the front outputs are used. route[n][0..1]: gain of output n into the
+   left and right stream, 0x100 = 1.0. */
+void c352_set_routing(const int route[4][2]);
+/* per output gain, 0x100 = 1.0 (MB87078 volume on Super System 22); routing only */
+void c352_set_output_gain(int output, int gain);
+
 int C352_sh_start(const struct MachineSound *msound);
 void C352_sh_stop(void);