mirror of
https://github.com/libretro/parallel-dc.git
synced 2026-11-07 12:37:53 -10:00
Rebase hw/mem/vem - backport https://github.com/flyinghead/flycast/commit/632731bedee26e7e786bcfbe83fd09bd6c481958#diff-dd79715fafbaf2391b2b3e848f42f670fc2c45cad4cebd6b13f36253dc6d529e
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twinaphex committed
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8 files changed
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-206
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+25
-49
@@ -49,19 +49,6 @@ void _vmem_get_ptrs(u32 sz,bool write,void*** vmap,void*** func)
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}
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}
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void* _vmem_get_ptr2(u32 addr,u32& mask)
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{
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u32 page=addr>>24;
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size_t iirf=(size_t)_vmem_MemInfo_ptr[page];
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void* ptr=(void*)(iirf&~HANDLER_MAX);
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if (ptr==0)
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return 0;
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mask=0xFFFFFFFF>>iirf;
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return ptr;
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}
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void* _vmem_read_const(u32 addr,bool& ismem,u32 sz)
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{
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u32 page=addr>>24;
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@@ -74,19 +61,15 @@ void* _vmem_read_const(u32 addr,bool& ismem,u32 sz)
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const unat id=iirf;
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if (sz==1)
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{
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return (void*)_vmem_RF8[id/4];
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return (void*)_vmem_RF8[id];
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}
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else if (sz==2)
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{
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return (void*)_vmem_RF16[id/4];
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return (void*)_vmem_RF16[id];
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}
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else if (sz==4)
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{
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return (void*)_vmem_RF32[id/4];
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}
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else
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{
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die("Invalid size");
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return (void*)_vmem_RF32[id];
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}
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}
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else
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@@ -99,7 +82,7 @@ void* _vmem_read_const(u32 addr,bool& ismem,u32 sz)
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}
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die("Invalid memory size");
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return 0;
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return nullptr;
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}
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void* _vmem_write_const(u32 addr,bool& ismem,u32 sz)
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@@ -114,19 +97,15 @@ void* _vmem_write_const(u32 addr,bool& ismem,u32 sz)
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const unat id=iirf;
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if (sz==1)
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{
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return (void*)_vmem_WF8[id/4];
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return (void*)_vmem_WF8[id];
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}
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else if (sz==2)
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{
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return (void*)_vmem_WF16[id/4];
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return (void*)_vmem_WF16[id];
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}
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else if (sz==4)
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{
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return (void*)_vmem_WF32[id/4];
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}
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else
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{
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die("Invalid size");
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return (void*)_vmem_WF32[id];
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}
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}
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else
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@@ -139,7 +118,7 @@ void* _vmem_write_const(u32 addr,bool& ismem,u32 sz)
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}
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die("Invalid memory size");
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return 0;
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return nullptr;
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}
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void* _vmem_page_info(u32 addr,bool& ismem,u32 sz,u32& page_sz,bool rw)
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@@ -155,15 +134,15 @@ void* _vmem_page_info(u32 addr,bool& ismem,u32 sz,u32& page_sz,bool rw)
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page_sz=24;
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if (sz==1)
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{
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return rw?(void*)_vmem_RF8[id/4]:(void*)_vmem_WF8[id/4];
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return rw?(void*)_vmem_RF8[id]:(void*)_vmem_WF8[id];
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}
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else if (sz==2)
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{
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return rw?(void*)_vmem_RF16[id/4]:(void*)_vmem_WF16[id/4];
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return rw?(void*)_vmem_RF16[id]:(void*)_vmem_WF16[id];
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}
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else if (sz==4)
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{
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return rw?(void*)_vmem_RF32[id/4]:(void*)_vmem_WF32[id/4];
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return rw?(void*)_vmem_RF32[id]:(void*)_vmem_WF32[id];
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}
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else
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{
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@@ -205,28 +184,27 @@ INLINE Trv DYNACALL _vmem_readt(u32 addr)
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const u32 id=iirf;
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if (sz==1)
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{
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return (T)_vmem_RF8[id/4](addr);
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return (T)_vmem_RF8[id](addr);
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}
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else if (sz==2)
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{
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return (T)_vmem_RF16[id/4](addr);
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return (T)_vmem_RF16[id](addr);
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}
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else if (sz==4)
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{
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return _vmem_RF32[id/4](addr);
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return _vmem_RF32[id](addr);
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}
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else if (sz==8)
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{
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T rv=_vmem_RF32[id/4](addr);
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rv|=(T)((u64)_vmem_RF32[id/4](addr+4)<<32);
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T rv=_vmem_RF32[id](addr);
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rv|=(T)((u64)_vmem_RF32[id](addr+4)<<32);
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return rv;
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}
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else
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{
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die("Invalid size");
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}
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}
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die("Invalid size");
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return 0;
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}
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template u8 DYNACALL _vmem_readt<u8, u8>(u32 addr);
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template u16 DYNACALL _vmem_readt<u16, u16>(u32 addr);
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@@ -254,20 +232,20 @@ INLINE void DYNACALL _vmem_writet(u32 addr,T data)
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const u32 id=iirf;
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if (sz==1)
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{
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_vmem_WF8[id/4](addr,data);
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_vmem_WF8[id](addr,data);
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}
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else if (sz==2)
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{
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_vmem_WF16[id/4](addr,data);
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_vmem_WF16[id](addr,data);
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}
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else if (sz==4)
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{
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_vmem_WF32[id/4](addr,data);
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_vmem_WF32[id](addr,data);
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}
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else if (sz==8)
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{
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_vmem_WF32[id/4](addr,(u32)data);
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_vmem_WF32[id/4](addr+4,(u32)((u64)data>>32));
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_vmem_WF32[id](addr,(u32)data);
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_vmem_WF32[id](addr+4,(u32)((u64)data>>32));
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}
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else
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{
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@@ -299,8 +277,6 @@ void DYNACALL _vmem_WriteMem64(u32 Address,u64 data) { _vmem_writet<u64>(Address
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//0xDEADC0D3 or 0
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#define MEM_ERROR_RETURN_VALUE 0xDEADC0D3
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//phew .. that was lota asm code ;) lets go back to C :D
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//default mem handlers ;)
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//default read handlers
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u8 DYNACALL _vmem_ReadMem8_not_mapped(u32 addresss)
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{
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@@ -375,7 +351,7 @@ void _vmem_map_handler(_vmem_handler Handler,u32 start,u32 end)
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verify(start<=end);
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for (u32 i=start;i<=end;i++)
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{
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_vmem_MemInfo_ptr[i]=((u8*)0)+(0x00000000 + Handler*4);
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_vmem_MemInfo_ptr[i] = (u8*)nullptr + Handler;
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}
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}
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@@ -94,7 +94,6 @@ void _vmem_release();
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//dynarec helpers
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void _vmem_get_ptrs(u32 sz,bool write,void*** vmap,void*** func);
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void* _vmem_get_ptr2(u32 addr,u32& mask);
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void* _vmem_read_const(u32 addr,bool& ismem,u32 sz);
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void* _vmem_write_const(u32 addr,bool& ismem,u32 sz);
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+55
-36
@@ -217,45 +217,33 @@ void YUV_data(u32* data , u32 count)
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//vram 32-64b
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//read
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u8 DYNACALL pvr_read_area1_8(u32 addr)
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template<typename T>
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T DYNACALL pvr_read_area1(u32 addr)
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{
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return vram[pvr_map32(addr)];
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}
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u16 DYNACALL pvr_read_area1_16(u32 addr)
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{
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return *(u16*)&vram.data[pvr_map32(addr)];
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}
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u32 DYNACALL pvr_read_area1_32(u32 addr)
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{
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return *(u32*)&vram.data[pvr_map32(addr)];
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return *(T *)&vram[pvr_map32(addr)];
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}
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template u8 pvr_read_area1<u8>(u32 addr);
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template u16 pvr_read_area1<u16>(u32 addr);
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template u32 pvr_read_area1<u32>(u32 addr);
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//write
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void DYNACALL pvr_write_area1_8(u32 addr,u8 data)
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template<typename T>
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void DYNACALL pvr_write_area1(u32 addr, T data)
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{
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INFO_LOG(MEMORY, "%08x: 8-bit VRAM writes are not possible", addr);
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}
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void DYNACALL pvr_write_area1_16(u32 addr,u16 data)
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{
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u32 vaddr = addr & VRAM_MASK;
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if (vaddr >= fb_watch_addr_start && vaddr < fb_watch_addr_end)
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if (sizeof(T) == 1)
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{
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fb_dirty = true;
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INFO_LOG(MEMORY, "%08x: 8-bit VRAM writes are not possible", addr);
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return;
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}
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*(u16*)&vram.data[pvr_map32(addr)]=data;
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}
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void DYNACALL pvr_write_area1_32(u32 addr,u32 data)
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{
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u32 vaddr = addr & VRAM_MASK;
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if (vaddr >= fb_watch_addr_start && vaddr < fb_watch_addr_end)
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{
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fb_dirty = true;
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}
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*(u32*)&vram.data[pvr_map32(addr)] = data;
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if (vaddr >= fb_watch_addr_start && vaddr < fb_watch_addr_end)
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fb_dirty = true;
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*(T *)&vram[pvr_map32(addr)] = data;
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}
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template void pvr_write_area1<u8>(u32 addr, u8 data);
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template void pvr_write_area1<u16>(u32 addr, u16 data);
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template void pvr_write_area1<u32>(u32 addr, u32 data);
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void TAWrite(u32 address,u32* data,u32 count)
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{
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@@ -287,7 +275,7 @@ void NOINLINE MemWrite32(void* dst, void* src)
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#if HOST_CPU!=CPU_ARM
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extern "C" void DYNACALL TAWriteSQ(u32 address,u8* sqb)
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{
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u32 address_w=address&0x1FFFFFF;//correct ?
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u32 address_w = address & 0x01FFFFE0;
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u8* sq=&sqb[address&0x20];
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if (likely(address_w<0x800000))//TA poly
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@@ -302,18 +290,17 @@ extern "C" void DYNACALL TAWriteSQ(u32 address,u8* sqb)
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{
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// Used by WinCE
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DEBUG_LOG(MEMORY, "Vram TAWriteSQ 0x%X SB_LMMODE0 %d", address, SB_LMMODE0);
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if (SB_LMMODE0 == 0)
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bool path64b = (address & 0x02000000 ? SB_LMMODE1 : SB_LMMODE0) == 0;
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if (path64b)
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{
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// 64b path
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MemWrite32(&vram[address_w&(VRAM_MASK-0x1F)],sq);
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memcpy(&vram[address_w & VRAM_MASK], sq, 32);
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}
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else
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{
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// 32b path
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for (int i = 0; i < 8; i++, address_w += 4)
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{
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pvr_write_area1_32(address_w, ((u32 *)sq)[i]);
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}
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pvr_write_area1<u32>(address_w, ((u32 *)sq)[i]);
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}
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}
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}
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@@ -352,3 +339,35 @@ u32 vri(u32 addr)
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{
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return *(u32*)&vram.data[pvr_map32(addr)];
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}
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template<typename T, bool upper>
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T pvr_read_area4(u32 addr)
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{
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bool access32 = (upper ? SB_LMMODE1 : SB_LMMODE0) == 1;
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if (access32)
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return pvr_read_area1<T>(addr);
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else
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return *(T*)&vram[addr & VRAM_MASK];
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}
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template u8 pvr_read_area4<u8, false>(u32 addr);
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template u16 pvr_read_area4<u16, false>(u32 addr);
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template u32 pvr_read_area4<u32, false>(u32 addr);
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template u8 pvr_read_area4<u8, true>(u32 addr);
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template u16 pvr_read_area4<u16, true>(u32 addr);
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template u32 pvr_read_area4<u32, true>(u32 addr);
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template<typename T, bool upper>
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void pvr_write_area4(u32 addr, T data)
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{
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bool access32 = (upper ? SB_LMMODE1 : SB_LMMODE0) == 1;
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if (access32)
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pvr_write_area1(addr, data);
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else
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*(T*)&vram[addr & VRAM_MASK] = data;
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}
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template void pvr_write_area4<u8, false>(u32 addr, u8 data);
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template void pvr_write_area4<u16, false>(u32 addr, u16 data);
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template void pvr_write_area4<u32, false>(u32 addr, u32 data);
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template void pvr_write_area4<u8, true>(u32 addr, u8 data);
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template void pvr_write_area4<u16, true>(u32 addr, u16 data);
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template void pvr_write_area4<u32, true>(u32 addr, u32 data);
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@@ -7,14 +7,6 @@ u32 vri(u32 addr);
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//vram 32-64b
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extern VArray2 vram;
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//read
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u8 DYNACALL pvr_read_area1_8(u32 addr);
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u16 DYNACALL pvr_read_area1_16(u32 addr);
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u32 DYNACALL pvr_read_area1_32(u32 addr);
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//write
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void DYNACALL pvr_write_area1_8(u32 addr,u8 data);
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void DYNACALL pvr_write_area1_16(u32 addr,u16 data);
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void DYNACALL pvr_write_area1_32(u32 addr,u32 data);
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//regs
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void pvr_WriteReg(u32 paddr,u32 data);
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@@ -31,5 +23,11 @@ void TAWrite(u32 address,u32* data,u32 count);
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extern "C" void DYNACALL TAWriteSQ(u32 address,u8* sqb);
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void YUV_init();
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template<typename T> T DYNACALL pvr_read_area1(u32 addr);
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template<typename T> void DYNACALL pvr_write_area1(u32 addr, T data);
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template<typename T, bool upper> T pvr_read_area4(u32 addr);
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template<typename T, bool upper> void pvr_write_area4(u32 addr, T data);
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//registers
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#define PVR_BASE 0x005F8000
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@@ -79,9 +79,9 @@ void DMAC_Ch2St()
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// If SB_C2DSTAT reg is inrange from 0x11000000 to 0x11FFFFE0, set 1 in SB_LMMODE0 reg.
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else if((dst >= 0x11000000) && (dst <= 0x11FFFFE0))
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{
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//printf(">>\tDMAC: TEX LNMODE0 Ch2 DMA SRC=%X DST=%X LEN=%X SB_LMMODE0 %d\n", src, dst, len, SB_LMMODE0);
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bool path64b = SB_C2DSTAT & 0x02000000 ? SB_LMMODE1 == 0 : SB_LMMODE0 == 0;
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if (SB_LMMODE0 == 0)
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if (path64b)
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{
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// 64-bit path
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dst=(dst&0xFFFFFF) |0xa4000000;
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@@ -111,7 +111,7 @@ void DMAC_Ch2St()
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while (len > 0)
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{
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u32 v = ReadMem32_nommu(src);
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pvr_write_area1_32(dst, v);
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pvr_write_area1<u32>(dst, v);
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len -= 4;
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src += 4;
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dst += 4;
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@@ -155,7 +155,7 @@ void DMAC_Ch2St()
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while (len > 0)
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||||
{
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u32 v = ReadMem32_nommu(src);
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pvr_write_area1_32(dst, v);
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pvr_write_area1<u32>(dst, v);
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len -= 4;
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src += 4;
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dst += 4;
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@@ -188,23 +188,37 @@ static const InterruptID dmac_itr[] = { sh4_DMAC_DMTE0, sh4_DMAC_DMTE1, sh4_DMAC
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template<u32 ch>
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void WriteCHCR(u32 addr, u32 data)
|
||||
{
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DMAC_CHCR(ch).full=data;
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if (ch == 0 || ch == 1)
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DMAC_CHCR(ch).full = data & 0xff0ffff7;
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else
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||||
// no AL or RL on channels 2 and 3
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||||
DMAC_CHCR(ch).full = data & 0xff0afff7;
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if (DMAC_CHCR(ch).TE == 0 && DMAC_CHCR(ch).DE && DMAC_DMAOR.DME)
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{
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if (DMAC_CHCR(ch).RS == 4)
|
||||
{
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u32 len = DMAC_DMATCR(ch) * 32;
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||||
{
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||||
u32 len = DMAC_DMATCR(ch) * 32;
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||||
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DEBUG_LOG(SH4, "DMAC: Manual DMA ch:%d rs:%d src: %08X dst: %08X len: %08X SM: %d, DM: %d", ch, DMAC_CHCR(ch).RS, DMAC_SAR(ch), DMAC_DAR(ch), DMAC_DMATCR(ch), DMAC_CHCR(ch).SM, DMAC_CHCR(ch).DM);
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for (int ofs = 0; ofs < len; ofs += 4)
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||||
{
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||||
u32 data = ReadMem32_nommu(DMAC_SAR(ch) + ofs);
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||||
WriteMem32_nommu(DMAC_DAR(ch) + ofs, data);
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}
|
||||
DEBUG_LOG(SH4, "DMAC: Manual DMA ch:%d TS:%d src: %08X dst: %08X len: %08X SM: %d, DM: %d", ch, DMAC_CHCR(ch).TS,
|
||||
DMAC_SAR(ch), DMAC_DAR(ch), DMAC_DMATCR(ch), DMAC_CHCR(ch).SM, DMAC_CHCR(ch).DM);
|
||||
verify(DMAC_CHCR(ch).TS == 4);
|
||||
for (int ofs = 0; ofs < len; ofs += 4)
|
||||
{
|
||||
u32 data = ReadMem32_nommu(DMAC_SAR(ch) + ofs);
|
||||
WriteMem32_nommu(DMAC_DAR(ch) + ofs, data);
|
||||
}
|
||||
|
||||
DMAC_CHCR(ch).TE = 1;
|
||||
}
|
||||
DMAC_CHCR(ch).TE = 1;
|
||||
if (DMAC_CHCR(ch).SM == 1)
|
||||
DMAC_SAR(ch) += len;
|
||||
else if (DMAC_CHCR(ch).SM == 2)
|
||||
DMAC_SAR(ch) -= len;
|
||||
if (DMAC_CHCR(ch).DM == 1)
|
||||
DMAC_DAR(ch) += len;
|
||||
else if (DMAC_CHCR(ch).DM == 2)
|
||||
DMAC_DAR(ch) -= len;
|
||||
}
|
||||
|
||||
InterruptPend(dmac_itr[ch], DMAC_CHCR(ch).TE);
|
||||
InterruptMask(dmac_itr[ch], DMAC_CHCR(ch).IE);
|
||||
|
||||
+52
-90
@@ -35,40 +35,35 @@ void _vmem_init();
|
||||
void _vmem_reset();
|
||||
void _vmem_term();
|
||||
|
||||
//MEM MAPPINNGG
|
||||
|
||||
//AREA 1
|
||||
_vmem_handler area1_32b;
|
||||
void map_area1_init()
|
||||
{
|
||||
area1_32b = _vmem_register_handler(pvr_read_area1_8,pvr_read_area1_16,pvr_read_area1_32,
|
||||
pvr_write_area1_8,pvr_write_area1_16,pvr_write_area1_32);
|
||||
area1_32b = _vmem_register_handler_Template(pvr_read_area1, pvr_write_area1);
|
||||
}
|
||||
|
||||
void map_area1(u32 base)
|
||||
{
|
||||
//map vram
|
||||
// VRAM
|
||||
|
||||
//Lower 32 mb map
|
||||
//64b interface
|
||||
_vmem_map_block(vram.data,0x04 | base,0x04 | base,VRAM_SIZE-1);
|
||||
_vmem_map_block(vram.data, 0x04 | base, 0x04 | base, VRAM_MASK);
|
||||
//32b interface
|
||||
_vmem_map_handler(area1_32b,0x05 | base,0x05 | base);
|
||||
_vmem_map_handler(area1_32b, 0x05 | base, 0x05 | base);
|
||||
|
||||
//Upper 32 mb mirror
|
||||
//0x0600 to 0x07FF
|
||||
_vmem_mirror_mapping(0x06|base,0x04|base,0x02);
|
||||
_vmem_mirror_mapping(0x06 | base, 0x04 | base, 0x02);
|
||||
}
|
||||
|
||||
//AREA 2
|
||||
void map_area2_init()
|
||||
{
|
||||
//nothing to map :p
|
||||
}
|
||||
|
||||
void map_area2(u32 base)
|
||||
{
|
||||
//nothing to map :p
|
||||
}
|
||||
|
||||
|
||||
@@ -79,22 +74,28 @@ void map_area3_init()
|
||||
|
||||
void map_area3(u32 base)
|
||||
{
|
||||
//32x2 or 16x4
|
||||
_vmem_map_block_mirror(mem_b.data,0x0C | base,0x0F | base,RAM_SIZE);
|
||||
// System RAM
|
||||
_vmem_map_block_mirror(mem_b.data, 0x0C | base,0x0F | base, RAM_SIZE);
|
||||
}
|
||||
|
||||
//AREA 4
|
||||
static _vmem_handler area4_handler_lower;
|
||||
static _vmem_handler area4_handler_upper;
|
||||
|
||||
void map_area4_init()
|
||||
{
|
||||
|
||||
area4_handler_lower = _vmem_register_handler(pvr_read_area4<u8, false>, pvr_read_area4<u16, false>, pvr_read_area4<u32, false>,
|
||||
pvr_write_area4<u8, false>, pvr_write_area4<u16, false>, pvr_write_area4<u32, false>);
|
||||
area4_handler_upper = _vmem_register_handler(pvr_read_area4<u8, true>, pvr_read_area4<u16, true>, pvr_read_area4<u32, true>,
|
||||
pvr_write_area4<u8, true>, pvr_write_area4<u16, true>, pvr_write_area4<u32, true>);
|
||||
}
|
||||
|
||||
void map_area4(u32 base)
|
||||
{
|
||||
//TODO : map later
|
||||
|
||||
//upper 32mb mirror lower 32 mb
|
||||
_vmem_mirror_mapping(0x12|base,0x10|base,0x02);
|
||||
// VRAM 64b/32b interface
|
||||
_vmem_map_handler(area4_handler_lower, 0x11 | base, 0x11 | base);
|
||||
// upper mirror
|
||||
_vmem_map_handler(area4_handler_upper, 0x13 | base, 0x13 | base);
|
||||
}
|
||||
|
||||
|
||||
@@ -121,34 +122,24 @@ void map_area5_init()
|
||||
|
||||
void map_area5(u32 base)
|
||||
{
|
||||
//map whole region to plugin handler :)
|
||||
//map whole region to plugin handler
|
||||
_vmem_map_handler(area5_handler,base|0x14,base|0x17);
|
||||
}
|
||||
|
||||
//AREA 6 -- Unassigned
|
||||
void map_area6_init()
|
||||
{
|
||||
//nothing to map :p
|
||||
}
|
||||
void map_area6(u32 base)
|
||||
{
|
||||
//nothing to map :p
|
||||
}
|
||||
|
||||
|
||||
//set vmem to default values
|
||||
void mem_map_default()
|
||||
{
|
||||
//vmem - init/reset :)
|
||||
_vmem_init();
|
||||
|
||||
|
||||
//*TEMP*
|
||||
//setup a fallback handler , that calls old code :)
|
||||
//_vmem_handler def_handler =
|
||||
// _vmem_register_handler(ReadMem8_i,ReadMem16_i,ReadMem32_i,WriteMem8_i,WriteMem16_i,WriteMem32_i);
|
||||
//_vmem_map_handler(def_handler,0,0xFFFF);
|
||||
|
||||
//U0/P0
|
||||
//0x0xxx xxxx -> normal memmap
|
||||
//0x2xxx xxxx -> normal memmap
|
||||
@@ -177,27 +168,25 @@ void mem_map_default()
|
||||
map_area6_init();
|
||||
map_area7_init();
|
||||
|
||||
//0x0-0xD : 7 times the normal memmap mirrors :)
|
||||
//some areas can be customised :)
|
||||
for (int i=0x0;i<0xE;i+=0x2)
|
||||
//0x0-0xD : 7 times the normal memmap mirrors
|
||||
for (int i = 0; i < 7; i++)
|
||||
{
|
||||
map_area0(i<<4); //Bios,Flahsrom,i/f regs,Ext. Device,Sound Ram
|
||||
map_area1(i<<4); //VRAM
|
||||
map_area2(i<<4); //Unassigned
|
||||
map_area3(i<<4); //RAM
|
||||
map_area4(i<<4); //TA
|
||||
map_area5(i<<4); //Ext. Device
|
||||
map_area6(i<<4); //Unassigned
|
||||
map_area7(i<<4); //Sh4 Regs
|
||||
map_area0(i << 5); //Bios,Flashrom,i/f regs,Ext. Device,Sound Ram
|
||||
map_area1(i << 5); //VRAM
|
||||
map_area2(i << 5); //Unassigned
|
||||
map_area3(i << 5); //RAM
|
||||
map_area4(i << 5); //TA
|
||||
map_area5(i << 5); //Ext. Device
|
||||
map_area6(i << 5); //Unassigned
|
||||
map_area7(i << 5); //Sh4 Regs
|
||||
}
|
||||
|
||||
//map p4 region :)
|
||||
// E0: p4 region
|
||||
map_p4();
|
||||
}
|
||||
void mem_Init()
|
||||
{
|
||||
//Allocate mem for memory/bios/flash
|
||||
//mem_b.Init(&sh4_reserved_mem[0x0C000000],RAM_SIZE);
|
||||
|
||||
sh4_area0_Init();
|
||||
sh4_mmr_init();
|
||||
@@ -207,7 +196,7 @@ void mem_Init()
|
||||
//Reset Sysmem/Regs -- Pvr is not changed , bios/flash are not zeroed out
|
||||
void mem_Reset(bool hard)
|
||||
{
|
||||
//mem is reseted on hard restart(power on) , not manual...
|
||||
//mem is reset on hard restart (power on) , not soft reset...
|
||||
if (hard)
|
||||
{
|
||||
//fill mem w/ 0's
|
||||
@@ -232,40 +221,31 @@ void mem_Term()
|
||||
_vmem_term();
|
||||
}
|
||||
|
||||
void WriteMemBlock_nommu_dma(u32 dst,u32 src,u32 size)
|
||||
void WriteMemBlock_nommu_dma(u32 dst, u32 src, u32 size)
|
||||
{
|
||||
u32 dst_msk,src_msk;
|
||||
bool dst_ismem, src_ismem;
|
||||
void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
|
||||
void* src_ptr = _vmem_read_const(src, src_ismem, 4);
|
||||
|
||||
void* dst_ptr=_vmem_get_ptr2(dst,dst_msk);
|
||||
void* src_ptr=_vmem_get_ptr2(src,src_msk);
|
||||
|
||||
if (dst_ptr && src_ptr)
|
||||
{
|
||||
memcpy((u8*)dst_ptr+(dst&dst_msk),(u8*)src_ptr+(src&src_msk),size);
|
||||
}
|
||||
else if (src_ptr)
|
||||
{
|
||||
WriteMemBlock_nommu_ptr(dst,(u32*)((u8*)src_ptr+(src&src_msk)),size);
|
||||
}
|
||||
if (dst_ismem && src_ismem)
|
||||
memcpy(dst_ptr, src_ptr, size);
|
||||
else if (src_ismem)
|
||||
WriteMemBlock_nommu_ptr(dst, (u32*)src_ptr, size);
|
||||
else
|
||||
{
|
||||
for (u32 i=0;i<size;i+=4)
|
||||
{
|
||||
WriteMem32_nommu(dst+i,ReadMem32_nommu(src+i));
|
||||
}
|
||||
verify(size % 4 == 0);
|
||||
for (u32 i = 0; i < size; i += 4)
|
||||
WriteMem32_nommu(dst + i, ReadMem32_nommu(src + i));
|
||||
}
|
||||
}
|
||||
void WriteMemBlock_nommu_ptr(u32 dst,u32* src,u32 size)
|
||||
{
|
||||
u32 dst_msk;
|
||||
bool dst_ismem;
|
||||
|
||||
void* dst_ptr=_vmem_get_ptr2(dst,dst_msk);
|
||||
void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
|
||||
|
||||
if (dst_ptr)
|
||||
{
|
||||
dst&=dst_msk;
|
||||
memcpy((u8*)dst_ptr+dst,src,size);
|
||||
}
|
||||
if (dst_ismem)
|
||||
memcpy(dst_ptr, src, size);
|
||||
else
|
||||
{
|
||||
for (u32 i = 0; i < size;)
|
||||
@@ -292,20 +272,15 @@ void WriteMemBlock_nommu_ptr(u32 dst,u32* src,u32 size)
|
||||
|
||||
void WriteMemBlock_nommu_sq(u32 dst,u32* src)
|
||||
{
|
||||
u32 dst_msk;
|
||||
void* dst_ptr=_vmem_get_ptr2(dst,dst_msk);
|
||||
bool dst_ismem;
|
||||
void* dst_ptr = _vmem_write_const(dst, dst_ismem, 4);
|
||||
|
||||
if (dst_ptr)
|
||||
{
|
||||
dst&=dst_msk;
|
||||
memcpy((u8*)dst_ptr+dst,src,32);
|
||||
}
|
||||
if (dst_ismem)
|
||||
memcpy(dst_ptr, src, 32);
|
||||
else
|
||||
{
|
||||
for (u32 i=0;i<32;i+=4)
|
||||
{
|
||||
WriteMem32_nommu(dst+i,src[i>>2]);
|
||||
}
|
||||
for (u32 i = 0; i < 32; i += 4)
|
||||
WriteMem32_nommu(dst + i, src[i >> 2]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -332,19 +307,6 @@ u8* GetMemPtr(u32 Addr,u32 size)
|
||||
}
|
||||
}
|
||||
|
||||
bool IsOnRam(u32 addr)
|
||||
{
|
||||
if (((addr>>26)&0x7)==3)
|
||||
{
|
||||
if ((((addr>>29) &0x7)!=7) && (((addr>>29) &0x7)!=3))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool interpreterRunning = false;
|
||||
|
||||
void SetMemoryHandlers()
|
||||
|
||||
@@ -69,7 +69,11 @@ void mem_map_default();
|
||||
//For debugger(gdb) - dynarec
|
||||
u8* GetMemPtr(u32 Addr,u32 size);
|
||||
|
||||
bool IsOnRam(u32 addr);
|
||||
static inline bool IsOnRam(u32 addr)
|
||||
{
|
||||
// in area 3 but not in P4
|
||||
return ((addr >> 26) & 7) == 3 && ((addr >> 29) & 7) != 7;
|
||||
}
|
||||
|
||||
bool LoadRomFiles(const string& root);
|
||||
void SaveRomFiles(const string& root);
|
||||
|
||||
@@ -878,7 +878,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
{
|
||||
for (int i = 0; i < width; i++)
|
||||
{
|
||||
u16 src = pvr_read_area1_16(addr);
|
||||
u16 src = pvr_read_area1<u16>(addr);
|
||||
*dst++ = (((src >> 10) & 0x1F) << 3) + FB_R_CTRL.fb_concat;
|
||||
*dst++ = (((src >> 5) & 0x1F) << 3) + FB_R_CTRL.fb_concat;
|
||||
*dst++ = (((src >> 0) & 0x1F) << 3) + FB_R_CTRL.fb_concat;
|
||||
@@ -894,7 +894,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
{
|
||||
for (int i = 0; i < width; i++)
|
||||
{
|
||||
u16 src = pvr_read_area1_16(addr);
|
||||
u16 src = pvr_read_area1<u16>(addr);
|
||||
*dst++ = (((src >> 11) & 0x1F) << 3) + FB_R_CTRL.fb_concat;
|
||||
*dst++ = (((src >> 5) & 0x3F) << 2) + (FB_R_CTRL.fb_concat & 3);
|
||||
*dst++ = (((src >> 0) & 0x1F) << 3) + FB_R_CTRL.fb_concat;
|
||||
@@ -909,7 +909,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
{
|
||||
for (int i = 0; i < width; i += 4)
|
||||
{
|
||||
u32 src = pvr_read_area1_32(addr);
|
||||
u32 src = pvr_read_area1<u32>(addr);
|
||||
*dst++ = src >> 16;
|
||||
*dst++ = src >> 8;
|
||||
*dst++ = src;
|
||||
@@ -917,7 +917,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
addr += 4;
|
||||
if (i + 1 >= width)
|
||||
break;
|
||||
u32 src2 = pvr_read_area1_32(addr);
|
||||
u32 src2 = pvr_read_area1<u32>(addr);
|
||||
*dst++ = src2 >> 8;
|
||||
*dst++ = src2;
|
||||
*dst++ = src >> 24;
|
||||
@@ -925,7 +925,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
addr += 4;
|
||||
if (i + 2 >= width)
|
||||
break;
|
||||
u32 src3 = pvr_read_area1_32(addr);
|
||||
u32 src3 = pvr_read_area1<u32>(addr);
|
||||
*dst++ = src3;
|
||||
*dst++ = src2 >> 24;
|
||||
*dst++ = src2 >> 16;
|
||||
@@ -946,7 +946,7 @@ void ReadFramebuffer(PixelBuffer<u32>& pb, int& width, int& height)
|
||||
{
|
||||
for (int i = 0; i < width; i++)
|
||||
{
|
||||
u32 src = pvr_read_area1_32(addr);
|
||||
u32 src = pvr_read_area1<u32>(addr);
|
||||
*dst++ = src >> 16;
|
||||
*dst++ = src >> 8;
|
||||
*dst++ = src;
|
||||
|
||||
Reference in new issue
Block a user