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LibretroAdmin
25a6efb3c4
These were compiled as not-implemented instructions, which request an emulator stop instead of raising the Breakpoint, Coprocessor Unusable or Floating-Point exception and leave the moved register unwritten. Each now calls its interpreter form with the jump flag set, as SYSCALL does. make check-cpu-fallback logs the exceptions and moved values of a test cartridge under the pure interpreter and requires the cached interpreter and Hacktarux to log the same; check-savestate-latch now checks the COP2 latch under Hacktarux too.
340 lines
11 KiB
C
340 lines
11 KiB
C
/* cpu_fallback_test -- instructions a recompiler hands to the interpreter.
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*
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* cpu_fallback_test rom FILE write the test cartridge
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* cpu_fallback_test check RAMDUMP check the reference run's log
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* cpu_fallback_test compare REF RAMDUMP check a run logged what REF did
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*
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* The cartridge's boot code, run from DMEM by the HLE PIF boot, programs the
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* VI's V_SYNC so frames are timed, copies a payload to RDRAM 0x400 and an
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* exception handler to 0x180 by PI DMA, and jumps to the payload. The
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* handler logs Cause.ExcCode, steps EPC past the instruction and returns.
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* The payload runs BREAK, the COP2 moves with COP2 unusable and usable,
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* DCFC1 and DCTC1, logging each exception and each value moved back, then
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* stores how many words it logged and a marker.
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*
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* `make check-cpu-fallback` takes the pure interpreter's log as the
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* reference, checks its exception codes, and requires the cached
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* interpreter and Hacktarux to log the same words.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define ROM_SIZE 0x100000
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#define PAYLOAD_ROM 0x1000
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#define PAYLOAD_RDRAM 0x400
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#define PAYLOAD_WORDS 96
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#define HANDLER_ROM 0x2000
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#define HANDLER_RDRAM 0x180
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#define HANDLER_WORDS 10
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#define LOG_ADDR 0x200
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#define LOG_WORDS 16
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#define COUNT_ADDR 0x1f8
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#define MARKER_ADDR 0x1fc
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#define MARKER 0x600dUL
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#define EXC_BP 0x24UL /* Breakpoint << 2 */
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#define EXC_CPU 0x2cUL /* Coprocessor Unusable << 2 */
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#define EXC_FPE 0x3cUL /* Floating-Point << 2 */
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#define VAL_MOVE 0x1357c2deUL
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#define VAL_DMOVE 0x89abcdefUL /* sign-extends to 64 bits */
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#define VAL_CTRL 0x2468c2c2UL
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define S7 23
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#define K0 26
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#define R(op, rs, rt, rd, sa, fn) (((unsigned long)(op) << 26) | ((unsigned long)(rs) << 21) | ((unsigned long)(rt) << 16) \
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| ((unsigned long)(rd) << 11) | ((unsigned long)(sa) << 6) | (unsigned long)(fn))
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#define I(op, rs, rt, imm) (((unsigned long)(op) << 26) | ((unsigned long)(rs) << 21) | ((unsigned long)(rt) << 16) \
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| ((unsigned long)(imm) & 0xffffUL))
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#define LUI(rt, imm) I(0x0f, 0, rt, imm)
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#define ORI(rt, rs, imm) I(0x0d, rs, rt, imm)
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#define ANDI(rt, rs, imm) I(0x0c, rs, rt, imm)
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#define ADDIU(rt, rs, imm) I(0x09, rs, rt, imm)
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#define LW(rt, off, base) I(0x23, base, rt, off)
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#define SW(rt, off, base) I(0x2b, base, rt, off)
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#define BNE(rs, rt, off) I(0x05, rs, rt, off)
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#define BEQ(rs, rt, off) I(0x04, rs, rt, off)
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#define OR(rd, rs, rt) R(0, rs, rt, rd, 0, 0x25)
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#define AND(rd, rs, rt) R(0, rs, rt, rd, 0, 0x24)
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#define NOR(rd, rs, rt) R(0, rs, rt, rd, 0, 0x27)
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#define DSRL32(rd, rt, sa) R(0, 0, rt, rd, sa, 0x3e)
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#define JR(rs) R(0, rs, 0, 0, 0, 0x08)
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#define BREAK R(0, 0, 0, 0, 0, 0x0d)
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#define MFC0(rt, rd) R(0x10, 0x00, rt, rd, 0, 0)
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#define MTC0(rt, rd) R(0x10, 0x04, rt, rd, 0, 0)
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#define ERET R(0x10, 0x10, 0, 0, 0, 0x18)
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#define DCFC1(rt, rd) R(0x11, 0x03, rt, rd, 0, 0)
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#define DCTC1(rt, rd) R(0x11, 0x07, rt, rd, 0, 0)
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#define MFC2(rt, rd) R(0x12, 0x00, rt, rd, 0, 0)
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#define DMFC2(rt, rd) R(0x12, 0x01, rt, rd, 0, 0)
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#define CFC2(rt, rd) R(0x12, 0x02, rt, rd, 0, 0)
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#define MTC2(rt, rd) R(0x12, 0x04, rt, rd, 0, 0)
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#define DMTC2(rt, rd) R(0x12, 0x05, rt, rd, 0, 0)
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#define CTC2(rt, rd) R(0x12, 0x06, rt, rd, 0, 0)
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#define NOP 0UL
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#define CP0_STATUS 12
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#define CP0_CAUSE 13
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#define CP0_EPC 14
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#define STATUS_CU2 0x4000
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struct emitter
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{
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unsigned char* base;
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unsigned n;
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};
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static void emit(struct emitter* e, unsigned long v)
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{
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unsigned char* p = e->base + 4 * e->n++;
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p[0] = (unsigned char)(v >> 24);
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p[1] = (unsigned char)(v >> 16);
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p[2] = (unsigned char)(v >> 8);
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p[3] = (unsigned char)v;
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}
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static void emit_li(struct emitter* e, unsigned rt, unsigned long v)
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{
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emit(e, LUI(rt, v >> 16));
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emit(e, ORI(rt, rt, v & 0xffff));
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}
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/* PI DMA len bytes from cartridge offset cart to RDRAM dram; $t0 = PI */
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static void emit_dma(struct emitter* e, unsigned long cart, unsigned long dram, unsigned long len)
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{
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unsigned wait;
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emit(e, ORI(T1, 0, dram));
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emit(e, SW(T1, 0x00, T0));
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emit_li(e, T1, 0x10000000UL + cart);
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emit(e, SW(T1, 0x04, T0));
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emit(e, ORI(T1, 0, len - 1));
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emit(e, SW(T1, 0x0c, T0));
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wait = e->n;
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emit(e, LW(T1, 0x10, T0));
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emit(e, ANDI(T1, T1, 3));
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emit(e, BNE(T1, 0, (int)wait - (int)(e->n + 1)));
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emit(e, NOP);
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}
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/* log $rt at $s7 and advance it */
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static void emit_log(struct emitter* e, unsigned rt)
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{
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emit(e, SW(rt, 0, S7));
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emit(e, ADDIU(S7, S7, 4));
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}
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/* Status.CU2 on or off, through $t1/$t2 */
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static void emit_cu2(struct emitter* e, int on)
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{
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emit(e, MFC0(T1, CP0_STATUS));
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emit(e, LUI(T2, STATUS_CU2));
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if (on)
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emit(e, OR(T1, T1, T2));
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else
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{
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emit(e, NOR(T2, T2, 0));
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emit(e, AND(T1, T1, T2));
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}
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emit(e, MTC0(T1, CP0_STATUS));
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}
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static int write_rom(const char* path)
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{
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unsigned char* rom = (unsigned char*)calloc(1, ROM_SIZE);
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struct emitter e;
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FILE* f;
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if (!rom)
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return 1;
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rom[0] = 0x80; rom[1] = 0x37; rom[2] = 0x12; rom[3] = 0x40;
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rom[7] = 0x0f;
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rom[8] = 0x80; rom[10] = 0x04;
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memcpy(rom + 0x20, "CPU FALLBACK ", 20);
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/* boot code at 0x40, run from DMEM */
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e.base = rom + 0x40;
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e.n = 0;
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emit(&e, LUI(T2, 0xa440)); /* VI: frames need V_SYNC */
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emit(&e, ORI(T1, 0, 2));
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emit(&e, SW(T1, 0x0c, T2));
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emit(&e, ORI(T1, 0, 0x20d));
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emit(&e, SW(T1, 0x18, T2));
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emit(&e, LUI(T0, 0xa460));
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emit_dma(&e, HANDLER_ROM, HANDLER_RDRAM, HANDLER_WORDS * 4);
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emit_dma(&e, PAYLOAD_ROM, PAYLOAD_RDRAM, PAYLOAD_WORDS * 4);
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emit_li(&e, T2, 0x80000000UL + PAYLOAD_RDRAM);
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emit(&e, JR(T2));
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emit(&e, NOP);
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/* exception handler: log ExcCode, return past the instruction */
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e.base = rom + HANDLER_ROM;
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e.n = 0;
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emit(&e, MFC0(K0, CP0_CAUSE));
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emit(&e, ANDI(K0, K0, 0x7c));
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emit_log(&e, K0);
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emit(&e, MFC0(K0, CP0_EPC));
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emit(&e, ADDIU(K0, K0, 4));
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emit(&e, MTC0(K0, CP0_EPC));
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emit(&e, NOP);
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emit(&e, ERET);
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emit(&e, NOP);
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if (e.n > HANDLER_WORDS)
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goto overflow;
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/* payload */
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e.base = rom + PAYLOAD_ROM;
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e.n = 0;
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emit_li(&e, S7, 0x80000000UL + LOG_ADDR);
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emit(&e, BREAK); /* Bp */
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emit_cu2(&e, 0);
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emit_li(&e, T3, VAL_MOVE);
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emit(&e, MTC2(T3, 0)); /* CpU */
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emit_cu2(&e, 1);
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emit(&e, MTC2(T3, 0));
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emit(&e, MFC2(T4, 0));
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emit_log(&e, T4); /* VAL_MOVE */
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emit_li(&e, T3, VAL_DMOVE);
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emit(&e, DMTC2(T3, 0));
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emit(&e, DMFC2(T5, 0));
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emit(&e, DSRL32(T6, T5, 0));
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emit_log(&e, T5); /* low word */
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emit_log(&e, T6); /* sign extension */
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emit_li(&e, T3, VAL_CTRL);
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emit(&e, CTC2(T3, 0));
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emit(&e, CFC2(T4, 0));
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emit_log(&e, T4); /* VAL_CTRL */
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emit(&e, DCFC1(T4, 0)); /* FPE */
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emit(&e, DCTC1(T4, 0)); /* FPE */
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emit_cu2(&e, 0);
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emit(&e, MFC2(T4, 0)); /* CpU */
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emit_li(&e, T1, 0x80000000UL);
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emit_li(&e, T2, LOG_ADDR + 0x80000000UL);
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emit(&e, R(0, S7, T2, T2, 0, 0x23)); /* SUBU: bytes logged */
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emit(&e, SW(T2, COUNT_ADDR, T1));
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emit(&e, ORI(T2, 0, MARKER));
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emit(&e, SW(T2, MARKER_ADDR, T1));
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emit(&e, BEQ(0, 0, 0xffff));
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emit(&e, NOP);
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if (e.n > PAYLOAD_WORDS)
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goto overflow;
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f = fopen(path, "wb");
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if (!f || fwrite(rom, 1, ROM_SIZE, f) != ROM_SIZE)
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{
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perror(path);
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if (f)
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fclose(f);
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free(rom);
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return 1;
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}
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fclose(f);
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free(rom);
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return 0;
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overflow:
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fprintf(stderr, "code overflows its DMA\n");
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free(rom);
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return 1;
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}
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/* RETRO_MEMORY_SYSTEM_RAM holds RDRAM as host-order 32-bit words */
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static unsigned long ram_word(const unsigned char* ram, unsigned long addr)
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{
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return (unsigned long)ram[addr] | ((unsigned long)ram[addr + 1] << 8)
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| ((unsigned long)ram[addr + 2] << 16) | ((unsigned long)ram[addr + 3] << 24);
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}
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static int load_log(const char* path, unsigned long* log, unsigned* count)
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{
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unsigned char ram[LOG_ADDR + 4 * LOG_WORDS];
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unsigned i;
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FILE* f = fopen(path, "rb");
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if (!f || fread(ram, 1, sizeof(ram), f) != sizeof(ram))
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{
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perror(path);
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if (f)
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fclose(f);
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return 1;
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}
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fclose(f);
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if (ram_word(ram, MARKER_ADDR) != MARKER)
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{
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fprintf(stderr, "FAIL: %s: the payload did not finish\n", path);
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return 1;
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}
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*count = (unsigned)(ram_word(ram, COUNT_ADDR) / 4);
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if (*count > LOG_WORDS)
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{
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fprintf(stderr, "FAIL: %s: %u log words\n", path, *count);
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return 1;
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}
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for (i = 0; i < *count; ++i)
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log[i] = ram_word(ram, LOG_ADDR + 4 * i);
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return 0;
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}
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int main(int argc, char** argv)
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{
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static const unsigned long expect[] = {
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EXC_BP, EXC_CPU, VAL_MOVE, VAL_DMOVE, 0xffffffffUL, VAL_CTRL, EXC_FPE, EXC_FPE, EXC_CPU
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};
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unsigned long ref[LOG_WORDS], got[LOG_WORDS];
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unsigned nref, ngot, i;
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if (argc == 3 && !strcmp(argv[1], "rom"))
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return write_rom(argv[2]);
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if (argc == 3 && !strcmp(argv[1], "check"))
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{
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if (load_log(argv[2], ref, &nref))
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return 1;
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if (nref != sizeof(expect) / sizeof(expect[0]))
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{
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fprintf(stderr, "FAIL: %s: %u log words, expected %u\n", argv[2], nref,
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(unsigned)(sizeof(expect) / sizeof(expect[0])));
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return 1;
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}
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for (i = 0; i < nref; ++i)
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if (ref[i] != expect[i])
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{
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fprintf(stderr, "FAIL: %s: log word %u is %#lx, expected %#lx\n", argv[2], i, ref[i], expect[i]);
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return 1;
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}
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printf("cpu_fallback_test: %s: reference log as expected\n", argv[2]);
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return 0;
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}
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if (argc == 4 && !strcmp(argv[1], "compare"))
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{
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if (load_log(argv[2], ref, &nref) || load_log(argv[3], got, &ngot))
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return 1;
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for (i = 0; i < nref || i < ngot; ++i)
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if (i >= nref || i >= ngot || ref[i] != got[i])
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{
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fprintf(stderr, "FAIL: %s: log word %u is %#lx, the reference logged %#lx\n", argv[3], i,
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i < ngot ? got[i] : 0UL, i < nref ? ref[i] : 0UL);
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return 1;
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}
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printf("cpu_fallback_test: %s: matches the reference\n", argv[3]);
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return 0;
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}
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fprintf(stderr, "usage: %s rom FILE | check RAMDUMP | compare REF RAMDUMP\n", argv[0]);
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return 2;
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}
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