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hacktarux: run BREAK, the COP2 moves and DCFC1/DCTC1 through the interpreter
These were compiled as not-implemented instructions, which request an emulator stop instead of raising the Breakpoint, Coprocessor Unusable or Floating-Point exception and leave the moved register unwritten. Each now calls its interpreter form with the jump flag set, as SYSCALL does. make check-cpu-fallback logs the exceptions and moved values of a test cartridge under the pure interpreter and requires the cached interpreter and Hacktarux to log the same; check-savestate-latch now checks the COP2 latch under Hacktarux too.
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LibretroAdmin authored and libretroadmin committed
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@@ -45,3 +45,5 @@ new_dynarec_disasm.txt
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/dynarec_block_check.tmp/
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/savestate_latch_test
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/savestate_latch_check.tmp/
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/cpu_fallback_test
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/cpu_fallback_check.tmp/
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@@ -1203,7 +1203,7 @@ clean: clean-tools
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clean-tools:
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rm -f $(ANGRYLION_TOOLS) lrhost$(EXE_EXT) lrhost_vk$(EXE_EXT) angrylion_replay$(EXE_EXT) $(ANGRYLION_CHECKS) dd_ipl_hle_test$(EXE_EXT) \
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$(CORE_CHECKS) dynarec_long_block_test$(EXE_EXT) savestate_latch_test$(EXE_EXT) tools/test_prsp_dmem_wrap.o tools/test_command_ring_rthreads.o tools/test_command_ring_ec.o
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$(CORE_CHECKS) dynarec_long_block_test$(EXE_EXT) savestate_latch_test$(EXE_EXT) cpu_fallback_test$(EXE_EXT) tools/test_prsp_dmem_wrap.o tools/test_command_ring_rthreads.o tools/test_command_ring_ec.o
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# Angrylion benchmark and bit-exactness harnesses (tools/angrylion_*.c),
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# linked against the core's own angrylion objects: `make tools` after a
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@@ -1371,9 +1371,11 @@ check-dynarec-block: $(TARGET) lrhost$(EXE_EXT) dynarec_long_block_test$(EXE_EXT
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# The COP0 and COP2 move latches across a savestate: a state saved between
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# the moves and their read-back is loaded into a fresh boot, with each CPU
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# core. The `saved` step checks the save frame lands in that window; the
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# recompilers do not implement COP2 moves, so they check the COP0 latch.
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# core. The `saved` step checks the save frame lands in that window; ari64
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# does not implement COP2 moves, so its runs check the COP0 latch only.
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# "dynamic_recompiler" is Hacktarux when x86_64 builds both recompilers.
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SAVESTATE_LATCH_CHECK_DIR := savestate_latch_check.tmp
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CHECK_HACKTARUX := $(if $(and $(filter x86_64,$(WITH_DYNAREC)),$(filter 1,$(WANT_HACKTARUX)),$(filter 1,$(HAVE_ARI64_X64))),1,0)
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SAVESTATE_LATCH_SAVE_AT := 16
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savestate_latch_test$(EXE_EXT): tools/savestate_latch_test.c
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@@ -1384,7 +1386,9 @@ check-savestate-latch: $(TARGET) lrhost$(EXE_EXT) savestate_latch_test$(EXE_EXT)
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./savestate_latch_test$(EXE_EXT) rom $(SAVESTATE_LATCH_CHECK_DIR)/latch.z64; \
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for core in pure_interpreter cached_interpreter dynamic_recompiler dynamic_recompiler_ari64; do \
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echo "== $$core"; \
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case $$core in dynamic_*) check=check-cop0 ;; *) check=check ;; esac; \
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case $$core in dynamic_recompiler_ari64) check=check-cop0 ;; \
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dynamic_recompiler) check=check-cop0; [ "$(CHECK_HACKTARUX)" = 1 ] && check=check ;; \
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*) check=check ;; esac; \
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( cd $(SAVESTATE_LATCH_CHECK_DIR) && LRHOST_SAVE=state_$$core.bin LRHOST_SAVE_AT=$(SAVESTATE_LATCH_SAVE_AT) \
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LRHOST_RAMDUMP=saved_$$core.bin ../lrhost$(EXE_EXT) ../$(TARGET) latch.z64 $$(( $(SAVESTATE_LATCH_SAVE_AT) + 1 )) \
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parallel-n64-gfxplugin=angrylion parallel-n64-rspplugin=hle \
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@@ -1397,6 +1401,36 @@ check-savestate-latch: $(TARGET) lrhost$(EXE_EXT) savestate_latch_test$(EXE_EXT)
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./savestate_latch_test$(EXE_EXT) $$check $(SAVESTATE_LATCH_CHECK_DIR)/ram_$$core.bin; \
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done; rm -rf $(SAVESTATE_LATCH_CHECK_DIR)
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# Instructions a recompiler runs through the interpreter (BREAK, the COP2
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# moves, DCFC1/DCTC1): the pure interpreter's exception and value log is the
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# reference, and the cached interpreter and Hacktarux must log the same.
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# ari64 does not implement these yet and is not compared.
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CPU_FALLBACK_CHECK_DIR := cpu_fallback_check.tmp
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CPU_FALLBACK_CORES := cached_interpreter
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ifeq ($(CHECK_HACKTARUX), 1)
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CPU_FALLBACK_CORES += dynamic_recompiler
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endif
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cpu_fallback_test$(EXE_EXT): tools/cpu_fallback_test.c
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$(CC) -O1 -g $< -o $@
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check-cpu-fallback: $(TARGET) lrhost$(EXE_EXT) cpu_fallback_test$(EXE_EXT)
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@set -e; rm -rf $(CPU_FALLBACK_CHECK_DIR); mkdir -p $(CPU_FALLBACK_CHECK_DIR)/lrhost-system; \
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./cpu_fallback_test$(EXE_EXT) rom $(CPU_FALLBACK_CHECK_DIR)/fallback.z64; \
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for core in pure_interpreter $(CPU_FALLBACK_CORES); do \
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echo "== $$core"; \
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( cd $(CPU_FALLBACK_CHECK_DIR) && LRHOST_RAMDUMP=ram_$$core.bin \
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../lrhost$(EXE_EXT) ../$(TARGET) fallback.z64 4 \
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parallel-n64-gfxplugin=angrylion parallel-n64-rspplugin=hle \
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parallel-n64-cpucore=$$core > /dev/null ); \
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if [ $$core = pure_interpreter ]; then \
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./cpu_fallback_test$(EXE_EXT) check $(CPU_FALLBACK_CHECK_DIR)/ram_$$core.bin; \
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else \
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./cpu_fallback_test$(EXE_EXT) compare $(CPU_FALLBACK_CHECK_DIR)/ram_pure_interpreter.bin \
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$(CPU_FALLBACK_CHECK_DIR)/ram_$$core.bin; \
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fi; \
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done; rm -rf $(CPU_FALLBACK_CHECK_DIR)
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# Core self-tests: MMIO register and DMA bounds, the frontend memory map,
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# framebuffer write notifications, COP0 exceptions, PI status, the MusyX
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# voice loaders, the BOSS audio arithmetic and, in a HAVE_PARALLEL_RSP=1
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@@ -1577,7 +1611,7 @@ endif
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check-core: $(CORE_CHECKS)
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@set -e; for t in $(CORE_CHECKS); do echo "== $$t"; ./$$t; done
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.PHONY: clean clean-tools tools check-angrylion check-core check-dynarec-block check-savestate-latch
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.PHONY: clean clean-tools tools check-angrylion check-core check-dynarec-block check-savestate-latch check-cpu-fallback
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-include $(OBJECTS:.o=.d)
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# A header named by an existing .d file but since deleted is not an error:
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@@ -226,6 +226,15 @@ void cached_interp_SCD(void);
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void cached_interp_DMFC0(void);
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void cached_interp_MFC0(void);
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void cached_interp_MTC0(void);
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void cached_interp_BREAK(void);
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void cached_interp_CFC2(void);
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void cached_interp_CTC2(void);
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void cached_interp_DCFC1(void);
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void cached_interp_DCTC1(void);
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void cached_interp_DMFC2(void);
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void cached_interp_DMTC2(void);
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void cached_interp_MFC2(void);
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void cached_interp_MTC2(void);
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void cached_interp_LWC1(void);
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void cached_interp_LDC1(void);
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void cached_interp_SWC1(void);
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@@ -4210,6 +4210,56 @@ void gen_SYSCALL(struct r4300_core* r4300)
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gencallinterp(r4300, (unsigned long long)cached_interp_SYSCALL, 1);
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}
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/* BREAK, the COP2 moves and the doubleword COP1 control moves have no
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* native form: run them through the interpreter. Each can raise an
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* exception (Breakpoint, Coprocessor Unusable, Reserved Instruction), so
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* the jump flag is set, as for SYSCALL. */
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void gen_BREAK(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_BREAK, 1);
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}
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void gen_CFC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_CFC2, 1);
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}
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void gen_CTC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_CTC2, 1);
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}
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void gen_DCFC1(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_DCFC1, 1);
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}
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void gen_DCTC1(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_DCTC1, 1);
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}
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void gen_DMFC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_DMFC2, 1);
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}
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void gen_DMTC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_DMTC2, 1);
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}
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void gen_MFC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_MFC2, 1);
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}
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void gen_MTC2(struct r4300_core* r4300)
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{
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gencallinterp(r4300, (unsigned long long)cached_interp_MTC2, 1);
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}
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/* Trap instructions */
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void gen_TGE(struct r4300_core* r4300)
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@@ -273,6 +273,15 @@ void gen_MFC1(struct r4300_core* r4300);
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void gen_MFHI(struct r4300_core* r4300);
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void gen_MFLO(struct r4300_core* r4300);
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void gen_MTC0(struct r4300_core* r4300);
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void gen_BREAK(struct r4300_core* r4300);
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void gen_CFC2(struct r4300_core* r4300);
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void gen_CTC2(struct r4300_core* r4300);
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void gen_DCFC1(struct r4300_core* r4300);
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void gen_DCTC1(struct r4300_core* r4300);
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void gen_DMFC2(struct r4300_core* r4300);
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void gen_DMTC2(struct r4300_core* r4300);
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void gen_MFC2(struct r4300_core* r4300);
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void gen_MTC2(struct r4300_core* r4300);
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void gen_MTC1(struct r4300_core* r4300);
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void gen_MTHI(struct r4300_core* r4300);
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void gen_MTLO(struct r4300_core* r4300);
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@@ -422,26 +431,17 @@ static void gen_CP1_CVT_S(struct r4300_core* r4300)
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#define gen_BC2TL genni
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#define gen_BC2TL_IDLE genni
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#define gen_BC2TL_OUT genni
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#define gen_BREAK genni
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#define gen_CFC0 genni
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#define gen_CFC2 genni
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#define gen_CTC0 genni
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#define gen_CTC2 genni
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#define gen_DMFC2 genni
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#define gen_DMTC2 genni
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#define gen_JR_IDLE genni
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#define gen_JR_OUT gen_JR
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#define gen_JALR_IDLE genni
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#define gen_JALR_OUT gen_JALR
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#define gen_LDC2 genni
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#define gen_LWC2 genni
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#define gen_MFC2 genni
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#define gen_MTC2 genni
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#define gen_SDC2 genni
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#define gen_SWC2 genni
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#define gen_DCFC1 genni
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#define gen_DCFC2 genni
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#define gen_DCTC1 genni
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#define gen_DCTC2 genni
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#define X(op) gen_##op
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@@ -0,0 +1,339 @@
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/* cpu_fallback_test -- instructions a recompiler hands to the interpreter.
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*
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* cpu_fallback_test rom FILE write the test cartridge
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* cpu_fallback_test check RAMDUMP check the reference run's log
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* cpu_fallback_test compare REF RAMDUMP check a run logged what REF did
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*
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* The cartridge's boot code, run from DMEM by the HLE PIF boot, programs the
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* VI's V_SYNC so frames are timed, copies a payload to RDRAM 0x400 and an
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* exception handler to 0x180 by PI DMA, and jumps to the payload. The
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* handler logs Cause.ExcCode, steps EPC past the instruction and returns.
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* The payload runs BREAK, the COP2 moves with COP2 unusable and usable,
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* DCFC1 and DCTC1, logging each exception and each value moved back, then
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* stores how many words it logged and a marker.
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*
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* `make check-cpu-fallback` takes the pure interpreter's log as the
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* reference, checks its exception codes, and requires the cached
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* interpreter and Hacktarux to log the same words.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define ROM_SIZE 0x100000
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#define PAYLOAD_ROM 0x1000
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#define PAYLOAD_RDRAM 0x400
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#define PAYLOAD_WORDS 96
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#define HANDLER_ROM 0x2000
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#define HANDLER_RDRAM 0x180
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#define HANDLER_WORDS 10
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#define LOG_ADDR 0x200
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#define LOG_WORDS 16
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#define COUNT_ADDR 0x1f8
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#define MARKER_ADDR 0x1fc
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#define MARKER 0x600dUL
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#define EXC_BP 0x24UL /* Breakpoint << 2 */
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#define EXC_CPU 0x2cUL /* Coprocessor Unusable << 2 */
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#define EXC_FPE 0x3cUL /* Floating-Point << 2 */
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#define VAL_MOVE 0x1357c2deUL
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#define VAL_DMOVE 0x89abcdefUL /* sign-extends to 64 bits */
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#define VAL_CTRL 0x2468c2c2UL
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define S7 23
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#define K0 26
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#define R(op, rs, rt, rd, sa, fn) (((unsigned long)(op) << 26) | ((unsigned long)(rs) << 21) | ((unsigned long)(rt) << 16) \
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| ((unsigned long)(rd) << 11) | ((unsigned long)(sa) << 6) | (unsigned long)(fn))
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#define I(op, rs, rt, imm) (((unsigned long)(op) << 26) | ((unsigned long)(rs) << 21) | ((unsigned long)(rt) << 16) \
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| ((unsigned long)(imm) & 0xffffUL))
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#define LUI(rt, imm) I(0x0f, 0, rt, imm)
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#define ORI(rt, rs, imm) I(0x0d, rs, rt, imm)
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#define ANDI(rt, rs, imm) I(0x0c, rs, rt, imm)
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#define ADDIU(rt, rs, imm) I(0x09, rs, rt, imm)
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#define LW(rt, off, base) I(0x23, base, rt, off)
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#define SW(rt, off, base) I(0x2b, base, rt, off)
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#define BNE(rs, rt, off) I(0x05, rs, rt, off)
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#define BEQ(rs, rt, off) I(0x04, rs, rt, off)
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#define OR(rd, rs, rt) R(0, rs, rt, rd, 0, 0x25)
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#define AND(rd, rs, rt) R(0, rs, rt, rd, 0, 0x24)
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#define NOR(rd, rs, rt) R(0, rs, rt, rd, 0, 0x27)
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#define DSRL32(rd, rt, sa) R(0, 0, rt, rd, sa, 0x3e)
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#define JR(rs) R(0, rs, 0, 0, 0, 0x08)
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#define BREAK R(0, 0, 0, 0, 0, 0x0d)
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#define MFC0(rt, rd) R(0x10, 0x00, rt, rd, 0, 0)
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#define MTC0(rt, rd) R(0x10, 0x04, rt, rd, 0, 0)
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#define ERET R(0x10, 0x10, 0, 0, 0, 0x18)
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#define DCFC1(rt, rd) R(0x11, 0x03, rt, rd, 0, 0)
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#define DCTC1(rt, rd) R(0x11, 0x07, rt, rd, 0, 0)
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#define MFC2(rt, rd) R(0x12, 0x00, rt, rd, 0, 0)
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#define DMFC2(rt, rd) R(0x12, 0x01, rt, rd, 0, 0)
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#define CFC2(rt, rd) R(0x12, 0x02, rt, rd, 0, 0)
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#define MTC2(rt, rd) R(0x12, 0x04, rt, rd, 0, 0)
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#define DMTC2(rt, rd) R(0x12, 0x05, rt, rd, 0, 0)
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#define CTC2(rt, rd) R(0x12, 0x06, rt, rd, 0, 0)
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#define NOP 0UL
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#define CP0_STATUS 12
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#define CP0_CAUSE 13
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#define CP0_EPC 14
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#define STATUS_CU2 0x4000
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struct emitter
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{
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unsigned char* base;
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unsigned n;
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};
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static void emit(struct emitter* e, unsigned long v)
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{
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unsigned char* p = e->base + 4 * e->n++;
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p[0] = (unsigned char)(v >> 24);
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p[1] = (unsigned char)(v >> 16);
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p[2] = (unsigned char)(v >> 8);
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p[3] = (unsigned char)v;
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}
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static void emit_li(struct emitter* e, unsigned rt, unsigned long v)
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{
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emit(e, LUI(rt, v >> 16));
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emit(e, ORI(rt, rt, v & 0xffff));
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}
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/* PI DMA len bytes from cartridge offset cart to RDRAM dram; $t0 = PI */
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static void emit_dma(struct emitter* e, unsigned long cart, unsigned long dram, unsigned long len)
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{
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unsigned wait;
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emit(e, ORI(T1, 0, dram));
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emit(e, SW(T1, 0x00, T0));
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emit_li(e, T1, 0x10000000UL + cart);
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emit(e, SW(T1, 0x04, T0));
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emit(e, ORI(T1, 0, len - 1));
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emit(e, SW(T1, 0x0c, T0));
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wait = e->n;
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emit(e, LW(T1, 0x10, T0));
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emit(e, ANDI(T1, T1, 3));
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emit(e, BNE(T1, 0, (int)wait - (int)(e->n + 1)));
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emit(e, NOP);
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}
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/* log $rt at $s7 and advance it */
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static void emit_log(struct emitter* e, unsigned rt)
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{
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emit(e, SW(rt, 0, S7));
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emit(e, ADDIU(S7, S7, 4));
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}
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/* Status.CU2 on or off, through $t1/$t2 */
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static void emit_cu2(struct emitter* e, int on)
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{
|
||||
emit(e, MFC0(T1, CP0_STATUS));
|
||||
emit(e, LUI(T2, STATUS_CU2));
|
||||
if (on)
|
||||
emit(e, OR(T1, T1, T2));
|
||||
else
|
||||
{
|
||||
emit(e, NOR(T2, T2, 0));
|
||||
emit(e, AND(T1, T1, T2));
|
||||
}
|
||||
emit(e, MTC0(T1, CP0_STATUS));
|
||||
}
|
||||
|
||||
static int write_rom(const char* path)
|
||||
{
|
||||
unsigned char* rom = (unsigned char*)calloc(1, ROM_SIZE);
|
||||
struct emitter e;
|
||||
FILE* f;
|
||||
|
||||
if (!rom)
|
||||
return 1;
|
||||
|
||||
rom[0] = 0x80; rom[1] = 0x37; rom[2] = 0x12; rom[3] = 0x40;
|
||||
rom[7] = 0x0f;
|
||||
rom[8] = 0x80; rom[10] = 0x04;
|
||||
memcpy(rom + 0x20, "CPU FALLBACK ", 20);
|
||||
|
||||
/* boot code at 0x40, run from DMEM */
|
||||
e.base = rom + 0x40;
|
||||
e.n = 0;
|
||||
emit(&e, LUI(T2, 0xa440)); /* VI: frames need V_SYNC */
|
||||
emit(&e, ORI(T1, 0, 2));
|
||||
emit(&e, SW(T1, 0x0c, T2));
|
||||
emit(&e, ORI(T1, 0, 0x20d));
|
||||
emit(&e, SW(T1, 0x18, T2));
|
||||
emit(&e, LUI(T0, 0xa460));
|
||||
emit_dma(&e, HANDLER_ROM, HANDLER_RDRAM, HANDLER_WORDS * 4);
|
||||
emit_dma(&e, PAYLOAD_ROM, PAYLOAD_RDRAM, PAYLOAD_WORDS * 4);
|
||||
emit_li(&e, T2, 0x80000000UL + PAYLOAD_RDRAM);
|
||||
emit(&e, JR(T2));
|
||||
emit(&e, NOP);
|
||||
|
||||
/* exception handler: log ExcCode, return past the instruction */
|
||||
e.base = rom + HANDLER_ROM;
|
||||
e.n = 0;
|
||||
emit(&e, MFC0(K0, CP0_CAUSE));
|
||||
emit(&e, ANDI(K0, K0, 0x7c));
|
||||
emit_log(&e, K0);
|
||||
emit(&e, MFC0(K0, CP0_EPC));
|
||||
emit(&e, ADDIU(K0, K0, 4));
|
||||
emit(&e, MTC0(K0, CP0_EPC));
|
||||
emit(&e, NOP);
|
||||
emit(&e, ERET);
|
||||
emit(&e, NOP);
|
||||
if (e.n > HANDLER_WORDS)
|
||||
goto overflow;
|
||||
|
||||
/* payload */
|
||||
e.base = rom + PAYLOAD_ROM;
|
||||
e.n = 0;
|
||||
emit_li(&e, S7, 0x80000000UL + LOG_ADDR);
|
||||
emit(&e, BREAK); /* Bp */
|
||||
emit_cu2(&e, 0);
|
||||
emit_li(&e, T3, VAL_MOVE);
|
||||
emit(&e, MTC2(T3, 0)); /* CpU */
|
||||
emit_cu2(&e, 1);
|
||||
emit(&e, MTC2(T3, 0));
|
||||
emit(&e, MFC2(T4, 0));
|
||||
emit_log(&e, T4); /* VAL_MOVE */
|
||||
emit_li(&e, T3, VAL_DMOVE);
|
||||
emit(&e, DMTC2(T3, 0));
|
||||
emit(&e, DMFC2(T5, 0));
|
||||
emit(&e, DSRL32(T6, T5, 0));
|
||||
emit_log(&e, T5); /* low word */
|
||||
emit_log(&e, T6); /* sign extension */
|
||||
emit_li(&e, T3, VAL_CTRL);
|
||||
emit(&e, CTC2(T3, 0));
|
||||
emit(&e, CFC2(T4, 0));
|
||||
emit_log(&e, T4); /* VAL_CTRL */
|
||||
emit(&e, DCFC1(T4, 0)); /* FPE */
|
||||
emit(&e, DCTC1(T4, 0)); /* FPE */
|
||||
emit_cu2(&e, 0);
|
||||
emit(&e, MFC2(T4, 0)); /* CpU */
|
||||
emit_li(&e, T1, 0x80000000UL);
|
||||
emit_li(&e, T2, LOG_ADDR + 0x80000000UL);
|
||||
emit(&e, R(0, S7, T2, T2, 0, 0x23)); /* SUBU: bytes logged */
|
||||
emit(&e, SW(T2, COUNT_ADDR, T1));
|
||||
emit(&e, ORI(T2, 0, MARKER));
|
||||
emit(&e, SW(T2, MARKER_ADDR, T1));
|
||||
emit(&e, BEQ(0, 0, 0xffff));
|
||||
emit(&e, NOP);
|
||||
if (e.n > PAYLOAD_WORDS)
|
||||
goto overflow;
|
||||
|
||||
f = fopen(path, "wb");
|
||||
if (!f || fwrite(rom, 1, ROM_SIZE, f) != ROM_SIZE)
|
||||
{
|
||||
perror(path);
|
||||
if (f)
|
||||
fclose(f);
|
||||
free(rom);
|
||||
return 1;
|
||||
}
|
||||
fclose(f);
|
||||
free(rom);
|
||||
return 0;
|
||||
|
||||
overflow:
|
||||
fprintf(stderr, "code overflows its DMA\n");
|
||||
free(rom);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* RETRO_MEMORY_SYSTEM_RAM holds RDRAM as host-order 32-bit words */
|
||||
static unsigned long ram_word(const unsigned char* ram, unsigned long addr)
|
||||
{
|
||||
return (unsigned long)ram[addr] | ((unsigned long)ram[addr + 1] << 8)
|
||||
| ((unsigned long)ram[addr + 2] << 16) | ((unsigned long)ram[addr + 3] << 24);
|
||||
}
|
||||
|
||||
static int load_log(const char* path, unsigned long* log, unsigned* count)
|
||||
{
|
||||
unsigned char ram[LOG_ADDR + 4 * LOG_WORDS];
|
||||
unsigned i;
|
||||
FILE* f = fopen(path, "rb");
|
||||
|
||||
if (!f || fread(ram, 1, sizeof(ram), f) != sizeof(ram))
|
||||
{
|
||||
perror(path);
|
||||
if (f)
|
||||
fclose(f);
|
||||
return 1;
|
||||
}
|
||||
fclose(f);
|
||||
|
||||
if (ram_word(ram, MARKER_ADDR) != MARKER)
|
||||
{
|
||||
fprintf(stderr, "FAIL: %s: the payload did not finish\n", path);
|
||||
return 1;
|
||||
}
|
||||
*count = (unsigned)(ram_word(ram, COUNT_ADDR) / 4);
|
||||
if (*count > LOG_WORDS)
|
||||
{
|
||||
fprintf(stderr, "FAIL: %s: %u log words\n", path, *count);
|
||||
return 1;
|
||||
}
|
||||
for (i = 0; i < *count; ++i)
|
||||
log[i] = ram_word(ram, LOG_ADDR + 4 * i);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
static const unsigned long expect[] = {
|
||||
EXC_BP, EXC_CPU, VAL_MOVE, VAL_DMOVE, 0xffffffffUL, VAL_CTRL, EXC_FPE, EXC_FPE, EXC_CPU
|
||||
};
|
||||
unsigned long ref[LOG_WORDS], got[LOG_WORDS];
|
||||
unsigned nref, ngot, i;
|
||||
|
||||
if (argc == 3 && !strcmp(argv[1], "rom"))
|
||||
return write_rom(argv[2]);
|
||||
|
||||
if (argc == 3 && !strcmp(argv[1], "check"))
|
||||
{
|
||||
if (load_log(argv[2], ref, &nref))
|
||||
return 1;
|
||||
if (nref != sizeof(expect) / sizeof(expect[0]))
|
||||
{
|
||||
fprintf(stderr, "FAIL: %s: %u log words, expected %u\n", argv[2], nref,
|
||||
(unsigned)(sizeof(expect) / sizeof(expect[0])));
|
||||
return 1;
|
||||
}
|
||||
for (i = 0; i < nref; ++i)
|
||||
if (ref[i] != expect[i])
|
||||
{
|
||||
fprintf(stderr, "FAIL: %s: log word %u is %#lx, expected %#lx\n", argv[2], i, ref[i], expect[i]);
|
||||
return 1;
|
||||
}
|
||||
printf("cpu_fallback_test: %s: reference log as expected\n", argv[2]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (argc == 4 && !strcmp(argv[1], "compare"))
|
||||
{
|
||||
if (load_log(argv[2], ref, &nref) || load_log(argv[3], got, &ngot))
|
||||
return 1;
|
||||
for (i = 0; i < nref || i < ngot; ++i)
|
||||
if (i >= nref || i >= ngot || ref[i] != got[i])
|
||||
{
|
||||
fprintf(stderr, "FAIL: %s: log word %u is %#lx, the reference logged %#lx\n", argv[3], i,
|
||||
i < ngot ? got[i] : 0UL, i < nref ? ref[i] : 0UL);
|
||||
return 1;
|
||||
}
|
||||
printf("cpu_fallback_test: %s: matches the reference\n", argv[3]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fprintf(stderr, "usage: %s rom FILE | check RAMDUMP | compare REF RAMDUMP\n", argv[0]);
|
||||
return 2;
|
||||
}
|
||||
@@ -14,9 +14,9 @@
|
||||
*
|
||||
* `make check-savestate-latch` saves a state during the second wait, loads
|
||||
* it into a fresh boot that has not reached the latch writes, and checks the
|
||||
* values read back are the ones moved in before the save. Hacktarux and
|
||||
* ari64 run COP2 moves as unimplemented instructions that write nothing, so
|
||||
* their runs check the COP0 latch only.
|
||||
* values read back are the ones moved in before the save. ari64 runs COP2
|
||||
* moves as unimplemented instructions that write nothing, so its runs
|
||||
* check the COP0 latch only.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
Reference in new issue
Block a user