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jit: Actually jit vmtfc/vmfvc.

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Sicne we have them and they are easy.
This commit is contained in:
Unknown W. Brackets 2014-09-01 23:13:07 -07:00
parent fd1b01b573
commit 4459b8f483
8 changed files with 58 additions and 2 deletions
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19
Core/MIPS/ARM/ArmCompVFPU.cpp
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@ -1277,6 +1277,25 @@ namespace MIPSComp
fpr.ReleaseSpillLocksAndDiscardTemps();
}
void Jit::Comp_Vmfvc(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vmtvc);
CONDITIONAL_DISABLE;
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
fpr.MapRegV(vs);
if (imm - 128 == VFPU_CTRL_CC) {
gpr.MapReg(MIPS_REG_VFPUCC, 0);
VMOV(fpr.V(vs), gpr.R(MIPS_REG_VFPUCC));
} else {
ADDI2R(SCRATCHREG1, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4, SCRATCHREG2);
VLDR(fpr.V(vs), SCRATCHREG1, 0);
}
fpr.ReleaseSpillLocksAndDiscardTemps();
}
}
void Jit::Comp_Vmtvc(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vmtvc);
CONDITIONAL_DISABLE;

4
Core/MIPS/ARM/ArmCompVFPUNEON.cpp
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@ -73,6 +73,10 @@ void Jit::CompNEON_Mftv(MIPSOpcode op) {
DISABLE;
}
void Jit::CompNEON_Vmfvc(MIPSOpcode op) {
DISABLE;
}
void Jit::CompNEON_Vmtvc(MIPSOpcode op) {
DISABLE;
}

2
Core/MIPS/ARM/ArmJit.h
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@ -110,6 +110,7 @@ public:
void Comp_VecDo3(MIPSOpcode op);
void Comp_VV2Op(MIPSOpcode op);
void Comp_Mftv(MIPSOpcode op);
void Comp_Vmfvc(MIPSOpcode op);
void Comp_Vmtvc(MIPSOpcode op);
void Comp_Vmmov(MIPSOpcode op);
void Comp_VScl(MIPSOpcode op);
@ -147,6 +148,7 @@ public:
void CompNEON_VecDo3(MIPSOpcode op);
void CompNEON_VV2Op(MIPSOpcode op);
void CompNEON_Mftv(MIPSOpcode op);
void CompNEON_Vmfvc(MIPSOpcode op);
void CompNEON_Vmtvc(MIPSOpcode op);
void CompNEON_Vmmov(MIPSOpcode op);
void CompNEON_VScl(MIPSOpcode op);

4
Core/MIPS/MIPSTables.cpp
View File

@ -763,9 +763,9 @@ const MIPSInstruction tableVFPU9[32] = // 110100 00010 xxxxx . ....... . .......
//16
// TODO: Flags may not be correct (prefixes, etc.)
INSTR("vmfvc", &Jit::Comp_Generic, Dis_Vmftvc, Int_Vmfvc, IN_OTHER|OUT_OTHER|IS_VFPU),
INSTR("vmfvc", &Jit::Comp_Vmfvc, Dis_Vmftvc, Int_Vmfvc, IN_OTHER|OUT_OTHER|IS_VFPU),
// TODO: Flags may not be correct (prefixes, etc.)
INSTR("vmtvc", &Jit::Comp_Generic, Dis_Vmftvc, Int_Vmtvc, IN_OTHER|OUT_OTHER|IS_VFPU),
INSTR("vmtvc", &Jit::Comp_Vmtvc, Dis_Vmftvc, Int_Vmtvc, IN_OTHER|OUT_OTHER|IS_VFPU),
INVALID,
INVALID,

13
Core/MIPS/PPC/PpcCompVFPU.cpp
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@ -712,6 +712,19 @@ namespace MIPSComp
fpr.ReleaseSpillLocksAndDiscardTemps();
}
void Jit::Comp_Vmfvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
fpr.MapRegV(vs);
ADDI(SREG, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4);
LFS(fpr.V(vs), SREG, 0);
fpr.ReleaseSpillLocksAndDiscardTemps();
}
}
void Jit::Comp_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;

1
Core/MIPS/PPC/PpcJit.h
View File

@ -215,6 +215,7 @@ namespace MIPSComp
void Comp_VecDo3(MIPSOpcode op);
void Comp_VV2Op(MIPSOpcode op);
void Comp_Mftv(MIPSOpcode op);
void Comp_Vmfvc(MIPSOpcode op);
void Comp_Vmtvc(MIPSOpcode op);
void Comp_Vmmov(MIPSOpcode op);
void Comp_VScl(MIPSOpcode op);

16
Core/MIPS/x86/CompVFPU.cpp
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@ -1742,6 +1742,22 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
}
}
void Jit::Comp_Vmfvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
fpr.MapRegV(vs, 0);
if (imm - 128 == VFPU_CTRL_CC) {
gpr.MapReg(MIPS_REG_VFPUCC, true, false);
MOVD_xmm(fpr.VX(vs), gpr.R(MIPS_REG_VFPUCC));
} else {
MOVSS(fpr.VX(vs), M(&currentMIPS->vfpuCtrl[imm - 128]));
}
fpr.ReleaseSpillLocks();
}
}
void Jit::Comp_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
int vs = _VS;

1
Core/MIPS/x86/Jit.h
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@ -118,6 +118,7 @@ public:
void Comp_VecDo3(MIPSOpcode op);
void Comp_VV2Op(MIPSOpcode op);
void Comp_Mftv(MIPSOpcode op);
void Comp_Vmfvc(MIPSOpcode op);
void Comp_Vmtvc(MIPSOpcode op);
void Comp_Vmmov(MIPSOpcode op);
void Comp_VScl(MIPSOpcode op);