libretro/ppsspp
1
0
Fork 0
mirror of https://github.com/libretro/ppsspp.git synced 2025-01-26 19:28:52 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Save one instruction on jal, shorten block exits by one instruction (moved to dispatcher).

Browse Source
This commit is contained in:
Henrik Rydgard 2013-02-15 23:33:35 +01:00
parent fdee111bca
commit 81589b67e5
5 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Core/MIPS/ARM/ArmAsm.cpp
View File

@ -140,6 +140,9 @@ void Jit::GenerateFixedCode()
FixupBranch badCoreState = B_CC(CC_NEQ);
FixupBranch skipToRealDispatch2 = B(); //skip the sync and compare first time
dispatcherPCInR0 = GetCodePtr();
MovToPC(R0);
// At this point : flags = EQ. Fine for the next check, no need to jump over it.
dispatcher = GetCodePtr();

9
Core/MIPS/ARM/ArmCompBranch.cpp
View File

@ -146,9 +146,8 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
// Take the branch
if (andLink)
{
ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
MOVI2R(R0, js.compilerPC + 8);
STR(R1, R0);
STR(CTXREG, R0, MIPS_REG_RA * 4);
}
WriteExit(targetAddr, 0);
@ -340,9 +339,8 @@ void Jit::Comp_Jump(u32 op)
break;
case 3: //jal
ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
MOVI2R(R0, js.compilerPC + 8);
STR(R1, R0);
STR(CTXREG, R0, MIPS_REG_RA * 4);
WriteExit(targetAddr, 0);
break;
@ -389,9 +387,8 @@ void Jit::Comp_JumpReg(u32 op)
case 8: //jr
break;
case 9: //jalr
ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
MOVI2R(R0, js.compilerPC + 8);
STR(R1, R0);
STR(CTXREG, R0, MIPS_REG_RA * 4);
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");

2
Core/MIPS/ARM/ArmCompVFPU.cpp
View File

@ -68,6 +68,8 @@ namespace MIPSComp
case 62: //sv.q
{
DISABLE;
gpr.MapReg(rs);
SetR0ToEffectiveAddress(rs, imm);

3
Core/MIPS/ARM/ArmJit.cpp
View File

@ -293,8 +293,7 @@ void Jit::WriteExit(u32 destination, int exit_num)
b->linkStatus[exit_num] = true;
} else {
MOVI2R(R0, destination);
MovToPC(R0);
B((const void *)dispatcher);
B((const void *)dispatcherPCInR0);
}
}

1
Core/MIPS/ARM/ArmJit.h
View File

@ -219,6 +219,7 @@ public:
const u8 *outerLoop;
const u8 *outerLoopPCInR0;
const u8 *dispatcherCheckCoreState;
const u8 *dispatcherPCInR0;
const u8 *dispatcher;
const u8 *dispatcherNoCheck;