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jit-ir: Add div/divu instructions.

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This commit is contained in:
Unknown W. Brackets 2016-05-14 19:21:15 -07:00
parent 6413b44434
commit c606f64f71
2 changed files with 30 additions and 2 deletions
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2
Core/MIPS/IR/IRCompALU.cpp
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@ -348,12 +348,10 @@ void IRFrontend::Comp_MulDivType(MIPSOpcode op) {
break;
case 26: //div
DISABLE;
ir.Write(IROp::Div, 0, rs, rt);
break;
case 27: //divu
DISABLE;
ir.Write(IROp::DivU, 0, rs, rt);
break;

30
Core/MIPS/IR/IRInterpreter.cpp
View File

@ -438,6 +438,36 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
break;
}
case IROp::Div:
{
s32 numerator = (s32)mips->r[inst->src1];
s32 denominator = (s32)mips->r[inst->src2];
if (numerator == (s32)0x80000000 && denominator == -1) {
mips->lo = 0x80000000;
mips->hi = -1;
} else if (denominator != 0) {
mips->lo = (u32)(numerator / denominator);
mips->hi = (u32)(numerator % denominator);
} else {
mips->lo = numerator < 0 ? 1 : -1;
mips->hi = numerator;
}
break;
}
case IROp::DivU:
{
u32 numerator = mips->r[inst->src1];
u32 denominator = mips->r[inst->src2];
if (denominator != 0) {
mips->lo = numerator / denominator;
mips->hi = numerator % denominator;
} else {
mips->lo = numerator <= 0xFFFF ? 0xFFFF : -1;
mips->hi = numerator;
}
break;
}
case IROp::BSwap16:
{
u32 x = mips->r[inst->src1];