Henrik Rydgård
17074f5a7f
Cache fpcond in a register to avoid store/load between compare and branch
2013-11-12 10:33:38 +01:00
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cb3bb73148
armjit: Improve GPR typesafety.
2013-11-09 08:24:15 -08:00
Henrik Rydgard
5a95e267fb
Add an optimization to discard registers at the end of functions when possible.
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Works in some games but crashes many so hiding it for now. Do not add UI.
2013-11-08 12:43:48 +01:00
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da0c9a86e5
Invalidate stubs/var imports when writing them.
2013-09-01 00:32:43 -07:00
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97aa1a631e
Improve typesafety in the x86 regalloc.
2013-08-24 19:41:10 -07:00
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109ad17ac6
Use a typesafe struct for opcodes.
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Also, correctly read delayslots using Read_Instruction on ARM.
2013-08-24 15:36:24 -07:00
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846178a588
Optimize thread switching a bit.
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~2.5% improvement in Zettai Hero Project (while multithreading.)
2013-08-15 01:26:16 -07:00
Henrik Rydgard
c86dc7279e
JIT: Implement VCMP in both JITs. Only the x86 one is tested and enabled.
2013-07-31 22:29:16 +02:00
Henrik Rydgard
51596b636a
Fix numerous ARM JIT bugs. Activate vmtvc and vscl, and vadd/vmul/vdiv/vsub for real this time.
2013-07-31 10:34:58 +02:00
Henrik Rydgard
d8294f025f
More VFPU stuff (nothing new activated)
2013-07-30 01:09:11 +02:00
Henrik Rydgard
afcb5add51
Minor code cleanup/reindent around ARM jit
2013-07-27 22:14:01 +02:00
Henrik Rydgard
e809e39681
Mips interpreter: Use unions instead of ugly casts. Strict-aliasing builds now work, but needs more testing so I don't enable it yet. Also some aliasing fixes for TransformPipeline.
2013-06-11 21:44:37 +02:00
Henrik Rydgard
5877929fe5
Add Mersenne Twister random number generator.
2013-05-20 00:57:45 +02:00
Henrik Rydgard
d22e258943
Don't need separate variables for writemask. Some optimizations.
2013-02-15 22:56:38 +01:00
Xele02
69b837f18b
Add debug dialogs (DisAsm, Memory, VFPU).
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New features : Breakpoint display, thread status, display list status
Update translation and start french translation
2013-02-10 17:33:34 +01:00
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2a6457b6ab
Cut down on h files including PointerWrap.
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This makes changes to it a bit faster to build.
2013-02-04 08:26:59 -08:00
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74cce1439b
Allow downcount to be negative.
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This fixes threads/alarm/alarm and ctrl/sampling2/sampling2, which were
broken in 674911dd
2013-01-17 01:14:49 -08:00
Henrik Rydgard
674911ddba
Move downcount into MIPSState for efficiency, enable block linking.
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On ARM JIT we can now reach it through the cpu context reg.
2013-01-12 00:44:18 +01:00
Henrik Rydgard
dafc9f62df
Regcache fixes, etc. thing still don't work when I turn on addiu :(
2013-01-09 11:20:48 +01:00
Henrik Rydgard
7b4cfb702c
Get rid of CPU class so that MIPSState can be POD, enabling offsetof
2013-01-08 14:20:06 +01:00
Henrik Rydgard
a2ff416534
Rename files. Rewrite ArmRegCache from scratch.
2013-01-07 22:33:09 +01:00
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e3e6f81dfa
Snapshot the CPU state as well.
2012-12-28 13:55:27 -08:00
Henrik Rydgard
8f33837de9
Bug fixing mtv/mfv, add comment
2012-11-22 20:14:24 +01:00
Henrik Rydgård
fb25b7405c
Synchronize the mainloop to the display end-of-frame on nonWindows
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platforms.
2012-11-19 14:16:37 +01:00
Henrik Rydgard
f326c36220
Some cleanup, re-enable some apparently disabled jit ops
2012-11-18 23:14:22 +01:00
Henrik Rydgard
7385113948
Implement sc/ll (llbit is not cleared correctly though)
2012-11-07 17:34:25 +01:00
Henrik Rydgard
aea0580297
More reworking of Callbacks, plus some other little fixes.
2012-11-07 15:44:48 +01:00
Henrik Rydgard
c61d10363a
Rewrite callback handling, part 1. All sorts of other fixes too.
2012-11-06 15:46:46 +01:00
Henrik Rydgard
64cc573703
Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.
2012-11-04 23:24:00 +01:00
Henrik Rydgard
4f7ad15758
Add snapshot of the whole source code.
2012-11-01 16:19:01 +01:00
