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378 Commits

Author SHA1 Message Date
Sacha
6c23e1b6d5 Use flags instead of bools for VCVT. Fix up some spacing. Only Android has ArmEmitterTest. 2013-03-02 11:34:03 +10:00
Henrik Rydgard
253396666c Merge branch 'armjit-fpu' of github.com:hrydgard/ppsspp into armjit-fpu 2013-03-01 18:26:36 +01:00
Sacha
0ca7b2a794 The cvt.s.w has to be signed (as it was before). Also, implement f,sf but untested so it is left commented out. 2013-03-01 16:55:10 +10:00
Sacha
26ebdb4f11 Improve VCMP instruction with option for E. 
Add comment to le JIT about how the VCMP crashes on ARM11, with commented code.
 2013-03-01 15:41:45 +10:00
Sacha
6d3c89e354 Fix up VCVT function to recognise the difference in encoding for to_int and to_float. There is no 'round to zero' option for to_float. cvt.s.w and cvt.w.s should be unsigned. 2013-03-01 13:45:22 +10:00
Henrik Rydgard
516ca8a0c4 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmJit.h
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/Framebuffer.cpp
 2013-02-28 23:56:28 +01:00
Henrik Rydgard
28575d4672 Fix the avoidLoad flag in the arm regalloc 2013-02-28 23:45:47 +01:00
Sacha
35a57be115 ARMJIT: Implement MADD, MADDU. Do bitrev if it takes an immediate. Fix a bug where MULTU was being passed through to the interpreter. 2013-02-28 23:45:46 +01:00
Henrik Rydgård
f311bfba9d Merge pull request #818 from xsacha/cmp-jit 
ARMJIT: min, max implementations.
 2013-02-28 12:01:07 -08:00
Sacha
d3f7def328 ARMJIT: min, max implementations. 2013-03-01 02:17:39 +10:00
Sacha
059abc0d69 ARMJIT: Add floor, ceil, round. Introducing a rounding mode for VCVT. 
The cvt and trunc are tested heavily. Floor, ceil, round aren't tested as much as there are very few games that use it.
 2013-03-01 01:10:07 +10:00
Sacha
61f5fb35bd ARMJIT: Implement cvt.w.s, cvt.s.w and trunc.w.s that are used heavily in Dragonball. 
May need to keep note of FCR to get correct rounding mode? Interpreter doesn't do this either.
 2013-02-28 19:46:07 +10:00
Sacha
fe90d5cd06 Add VNEG and VABS implementations and use in FPU2op. 2013-02-27 23:33:59 +10:00
Sacha
8d4400fba1 ARMJIT: Clean up for load/stores 2013-02-27 22:17:38 +10:00
Sacha
ff14815fda ARMJIT: Combine to one instruction for load/stores. 2013-02-27 19:45:01 +10:00
Sacha
2c59de95e9 JIT the signed load/store variants too 2013-02-27 18:05:45 +10:00
Sacha
fe8b80c12e ARM JIT: Add and simplify some half-word load/store instructions. 2013-02-27 17:09:47 +10:00
Unknown W. Brackets
d3a66d0a90 Android buildfix. 2013-02-25 10:48:32 -08:00
Unknown W. Brackets
4e8359bae2 Fix Comp_ShiftType not using ROR. 
Untested but looks right?  Reported by @xsacha.
 2013-02-24 22:58:31 -08:00
Unknown W. Brackets
06425ae9e7 Correct the more obscure vcmp cases. 2013-02-24 15:07:29 -08:00
Unknown W. Brackets
4d1f07990a Fix some NaN handling in a few funcs. 2013-02-24 14:39:13 -08:00
Unknown W. Brackets
84c95526bc Mark more instructions which eat prefixes. 2013-02-24 14:38:37 -08:00
Unknown W. Brackets
64c42ffaf2 Fix some warnings generated by clang. 2013-02-24 10:23:31 -08:00
Unknown W. Brackets
3fbb5d4388 Avoid using CALL() directly in case of far calls. 
This mainly matters for x64.
 2013-02-24 00:12:55 -08:00
Unknown W. Brackets
7eb9af271b Fix downcount check without fastmem in jr. 2013-02-23 14:30:24 -08:00
Henrik Rydgård
2891576549 Merge pull request #774 from unknownbrackets/savestates 
Wait for jit to exit the runloop in debug, quit, and savestates
 2013-02-23 14:27:05 -08:00
Henrik Rydgård
796a19dfe2 Merge pull request #772 from unknownbrackets/change-reg 
Fix change register feature
 2013-02-23 13:56:42 -08:00
Unknown W. Brackets
2164a7fdf9 Keep track of whether we're in the runloop or not. 2013-02-23 13:01:00 -08:00
Unknown W. Brackets
0c1b6fecfe Allow changing fpu/vfpu regs. 2013-02-23 12:30:18 -08:00
Unknown W. Brackets
608fb85f0d Make changing register values actually work. 2013-02-23 12:25:51 -08:00
Unknown W. Brackets
6c6bd0bd9c Correct prefix handling in vf2h/vh2f. 2013-02-23 12:16:03 -08:00
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42c2313893 Initial implementation of vf2h. 
Fixes Fat Princess and possibly other stuff.
 2013-02-23 12:16:03 -08:00
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313ffdb495 Add a stub for clz/clo in x86 jit. 2013-02-21 01:25:02 -08:00
Unknown W. Brackets
08923c092b Implement ins and ext in the x86 jit. 2013-02-21 01:25:01 -08:00
Unknown W. Brackets
dede852c03 Optimize out slti in the x86 jit. 
I'm kinda surprised this actually happens...
 2013-02-21 01:25:01 -08:00
Unknown W. Brackets
abde404c00 Optimize out some addu/etc. calls against imms. 2013-02-21 01:25:01 -08:00
Unknown W. Brackets
9e479b4391 Optimize addi/addiu to just LEA when possible. 2013-02-21 01:25:00 -08:00
Unknown W. Brackets
2db368c29a Add more imm handling for shifts in x86 jit. 
This is actually hit, and propagates more imms through.
 2013-02-21 01:25:00 -08:00
Henrik Rydgård
4511b11c5a Merge pull request #750 from unknownbrackets/jit-minor 
Some minor x86 jitting
 2013-02-20 14:02:04 -08:00
Unknown W. Brackets
958d95a029 Make bitrev use less instructions in the x86 jit. 
Much less.
 2013-02-20 13:43:17 -08:00
StorMyu
282e5be93e Update Core/MIPS/MIPSDis.cpp 2013-02-20 22:10:54 +01:00
Unknown W. Brackets
7b612cf28d Don't need this with the imm code path. 2013-02-20 12:16:57 -08:00
Unknown W. Brackets
f1f48e26e4 Merge branch 'cpu-minor' into jit-minor 2013-02-20 12:10:29 -08:00
Unknown W. Brackets
2bdc9dc491 Reset llBit on thread switch. 
Never actually seen ll used, though... but this way it should
work as advertized, as long as a syscall doesn't happen in between...
 2013-02-20 12:09:13 -08:00
Unknown W. Brackets
3a365fef64 Protect against some writes to $0. 2013-02-20 12:09:12 -08:00
Unknown W. Brackets
c8f85ace41 Implement bitrev in x86 jit + some imms. 2013-02-20 12:09:02 -08:00
Unknown W. Brackets
c3be50acbb Implement movz/movn in the x86 jit. 2013-02-20 12:09:01 -08:00
Unknown W. Brackets
0d6d58fed4 Add min and max to the x86 jit portfolio. 2013-02-20 12:09:01 -08:00
StorMyu
43da6672bc Merge branch 'master' of https://github.com/StorMyu/ppsspp 2013-02-20 21:06:40 +01:00
StorMyu
197e5fc630 Change %i/%d to %X 
Cause it's just an easier read for every instruction to do Hexadecimal operation on Hexadecimal Immediate.
 2013-02-20 21:04:19 +01:00