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15,213 Commits 19 Branches 54 Tags 247 MiB
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58 Commits

Author SHA1 Message Date
Henrik Rydgard
51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
Henrik Rydgard
28ca8d4818 x86 jit: Use LEA to emulate addu but only when it can save a few bytes 2014-11-16 17:39:47 +01:00
Henrik Rydgard
1c78e29c79 x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX. 
Might have missed a few places.
 2014-11-16 17:38:26 +01:00
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86e3739a3e x86jit: Optimize some cases of ins/ext. 
They happen but are minor.
 2014-11-09 09:22:29 -08:00
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e05263af32 x86jit: Allow EBX sign extension for 32-bit. 2014-11-09 09:07:52 -08:00
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8dbd3c3b9c x86jit: Don't lie about ZERO when it's not an imm. 2014-11-09 08:27:02 -08:00
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d0a2ced2f9 x86jit: Flip cc in stl* to avoid reg loads. 
Unfortunately, this zero thing is now concerning me...
 2014-11-09 08:15:39 -08:00
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59f491eddb x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.

Fixed a small mistake.
 2014-11-09 07:23:44 -08:00
Henrik Rydgard
5888b3bdc4 Revert "x86jit: Micro optimize slt* a bit." 
This reverts commit ee66596b8d.

Broke a lot of games, probably some small bug.

Conflicts:
	Core/MIPS/x86/CompALU.cpp
 2014-11-09 12:07:21 +01:00
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313d9e95c7 Clarify a comment. 2014-11-09 01:05:03 -08:00
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ee66596b8d x86jit: Micro optimize slt* a bit. 
This improves their performance and hopefully latency.  It also avoids
filling registers that are not likely to be used again.
 2014-11-08 22:54:03 -08:00
Henrik Rydgård
f99c2cd010 x86 Jit: Generate nicer code for some cases of addiu 2014-10-12 17:47:53 +02:00
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4a1514730f x86jit/ppcjit: Correct some bad sltiu compares. 2014-09-02 08:04:22 -07:00
Henrik Rydgard
82421f4dcf x86 jit: Further fix for nor, thanks unknown 
See #6638
 2014-07-27 22:26:35 +02:00
Henrik Rydgard
903ddbc513 x86 JIT: Fix bug where NOR would not get computed correctly in corner case 
(CompTriArith can end up not actually mapping rd to a register when taking
a shortcut)

May fix the JIT issue mentioned by CPkmn and located by daniel229 as an aside in #6638
 2014-07-27 21:41:41 +02:00
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27870aa593 x86jit: Map HI/LO as registers. 
Not actually ever cached, but now it's all consistent.
 2014-06-28 00:38:56 -07:00
Henrik Rydgård
aea272a3ce Jit x86: optimize "subu r, 0, r" to NEG r. 2014-03-03 13:42:32 +01:00
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2347498667 x86jit: Use templates to avoid some void * casts. 
Makes it a bit cleaner and potentially safer.
 2014-01-18 09:57:13 -08:00
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dffa35ef2f When ins is used with a zero argument, don't OR. 
Seems it's used effectively to mask out bits with rs=zero.  Makes sense...
 2013-11-29 09:17:12 -08:00
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fd38b10ab6 x86jit: Rename imm funcs to match armjit. 2013-11-10 21:59:49 -08:00
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3a8f0598c4 x86jit: Implement wsbh/wsbw. 2013-11-10 14:38:09 -08:00
Henrik Rydgard
5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
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02dd250354 armjit: Optimize out a few immediate logic cases. 2013-11-08 11:39:24 -08:00
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97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
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109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
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3278b5e373 Handle the immediate case of clz/clo. 2013-07-04 23:07:42 -07:00
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654490566f Implement clz/clo in x86 jit. 2013-07-04 18:01:17 -07:00
Sacha
a26b48fc0b Stub wsbh/wsbw for x86. 2013-06-05 14:55:01 +10:00
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028e85dc92 Cleanup some differences between the two jits. 2013-03-07 02:08:44 -08:00
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313ffdb495 Add a stub for clz/clo in x86 jit. 2013-02-21 01:25:02 -08:00
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08923c092b Implement ins and ext in the x86 jit. 2013-02-21 01:25:01 -08:00
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dede852c03 Optimize out slti in the x86 jit. 
I'm kinda surprised this actually happens...
 2013-02-21 01:25:01 -08:00
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abde404c00 Optimize out some addu/etc. calls against imms. 2013-02-21 01:25:01 -08:00
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9e479b4391 Optimize addi/addiu to just LEA when possible. 2013-02-21 01:25:00 -08:00
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2db368c29a Add more imm handling for shifts in x86 jit. 
This is actually hit, and propagates more imms through.
 2013-02-21 01:25:00 -08:00
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958d95a029 Make bitrev use less instructions in the x86 jit. 
Much less.
 2013-02-20 13:43:17 -08:00
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7b612cf28d Don't need this with the imm code path. 2013-02-20 12:16:57 -08:00
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c8f85ace41 Implement bitrev in x86 jit + some imms. 2013-02-20 12:09:02 -08:00
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c3be50acbb Implement movz/movn in the x86 jit. 2013-02-20 12:09:01 -08:00
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0d6d58fed4 Add min and max to the x86 jit portfolio. 2013-02-20 12:09:01 -08:00
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f6f2927526 Add curlies around DISABLE/CONDITIONAL_DISABLE. 2013-02-15 08:35:33 -08:00
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7c428bfeba Fix immediate div CMP. 2013-02-10 10:02:55 -08:00
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e0ebfd2211 Jit div/divu in x86. 2013-02-10 09:36:41 -08:00
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9bb78ce2ec Jit madd/msub in x86. 2013-02-10 08:45:35 -08:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
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6bee870ac9 Fix CompShiftVar for x86 jit. 
In case rd == rs, need to load ECX first.  I can't find anything
else wrong with it for it to be disabled.
 2013-02-02 14:02:07 -08:00
Henrik Rydgard
90b11bba37 Implement mult, multu, mflo/hi, mtlo/hi in x86 JIT 2013-01-29 00:48:42 +01:00
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db5fa233a8 Make sure we don't mark a reg dirty on noop. 2013-01-25 22:34:01 -08:00
Henrik Rydgard
2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
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a7c6f46829 Optimize and/or 0 to just a mov in x86 jit. 2013-01-25 00:25:40 -08:00