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215 Commits

Author SHA1 Message Date
Henrik Rydgard
c97f63a9d9 Minor armjit opt 2013-01-30 20:01:42 +01:00
Henrik Rydgard
1b4394ac5e ARM jit: jit integer multiplies. ARM is so nice, very clean. 2013-01-30 01:06:14 +01:00
Henrik Rydgard
739b76a55a Armjit: branch code cleanup #1 2013-01-30 01:05:36 +01:00
Henrik Rydgard
90b11bba37 Implement mult, multu, mflo/hi, mtlo/hi in x86 JIT 2013-01-29 00:48:42 +01:00
Unknown W. Brackets
6d7a8d9b1a Apply the memview mask to jit immediates too. 2013-01-26 23:54:43 -08:00
Unknown W. Brackets
a7b5433ba7 Make sure fastmem isn't confused by rs changing. 2013-01-26 23:18:50 -08:00
Unknown W. Brackets
a89d61463e Make the VFPU jit use far jumps for memory access. 2013-01-26 23:08:19 -08:00
Henrik Rydgard
1ed9a6ba56 Small fixes. v0.6. 2013-01-26 21:39:35 +01:00
Unknown W. Brackets
7ba8d1efe9 Android buildfix. 2013-01-26 12:01:23 -08:00
Unknown W. Brackets
0e8e9697c5 Add lv.q/sv.q support to the x86 jit. 2013-01-26 10:09:18 -08:00
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b77ce99d01 Oops, no slow read for immediates usually. 2013-01-26 09:27:52 -08:00
Unknown W. Brackets
9cd5836b85 Rename WriteFinish() to Finish() is safe mem. 
It's nothing to do with writing.
 2013-01-26 09:09:47 -08:00
Unknown W. Brackets
3e419f513a Refactor jit safe memory reads without dup code. 
But, maybe too automagical...
 2013-01-26 08:42:34 -08:00
Unknown W. Brackets
b7ef3e7bef Make sure to log / check bad immediate mem access. 
Although, theoretically, this should never happen.
Also, definitely time to refactor.
 2013-01-25 23:06:43 -08:00
Unknown W. Brackets
3418383917 Immediately break on bad mem access in jit slowmem. 2013-01-25 22:52:51 -08:00
Unknown W. Brackets
db5fa233a8 Make sure we don't mark a reg dirty on noop. 2013-01-25 22:34:01 -08:00
Henrik Rydgard
2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
ad5e2b58c6 Separate the two regcaches before doing major surgery to FPURegCache. 2013-01-26 01:34:18 +01:00
Henrik Rydgård
be12d2efe3 Merge pull request #498 from lioncash/master 
Fix a duplicate branch in Loaders.cpp
 2013-01-25 16:07:51 -08:00
Lioncash
eb84b00a3d Fix a duplicate branch in MIPS/MIPSDis.cpp 
Copypaste error for beql.

Thanks go out to [Unknown] for specifying the correct value of o.
 2013-01-25 17:57:12 -05:00
Henrik Rydgård
67f849a442 Merge pull request #496 from lioncash/master 
Memory leak cleanup. Fixing some small things that were fixed in the Dolphin source, but didn't make it over here.
 2013-01-25 11:17:21 -08:00
Henrik Rydgard
dd149a50a3 Must flush FPR regcache before thrashing the fp regs 2013-01-25 19:55:30 +01:00
Henrik Rydgard
aabc0aa9ef Quick implementation of LV.Q and SV.Q in x86/x64 JIT 2013-01-25 19:50:30 +01:00
Lioncash
1cc74aa6c0 Get rid of unused iterators. 2013-01-25 13:11:06 -05:00
Henrik Rydgård
0f080aeaaa Merge pull request #492 from unknownbrackets/jit-minor 
ALU jit optimizations
 2013-01-25 01:01:34 -08:00
Unknown W. Brackets
a7c6f46829 Optimize and/or 0 to just a mov in x86 jit. 2013-01-25 00:25:40 -08:00
Unknown W. Brackets
ab9bea068c Jit reg+reg compile time, and avoid flushing EDX. 2013-01-25 00:16:55 -08:00
Unknown W. Brackets
ce5f393fb8 Hit immediates in the ALU better and more simply. 2013-01-25 00:16:55 -08:00
Unknown W. Brackets
2748437032 Add support for FPU and VFPU for nice delay slots. 2013-01-24 20:18:18 -08:00
Unknown W. Brackets
f7ebddc4a3 Whitelist common delay slot ops with outreg info. 2013-01-24 19:59:33 -08:00
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d1909a1581 Add a quick disable define for nice delay slots. 2013-01-24 19:11:03 -08:00
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75cbe18afc Simplify nice delay slot detect, and yes for noop. 
NOOP seems very common so this should already benefit speed a bit.
 2013-01-24 08:29:32 -08:00
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2eba209f64 Move around the jit nice delay slot logic. 
Nice delay slots don't not save flags, they run before the CMP.
 2013-01-24 07:31:51 -08:00
Unknown W. Brackets
3444fc8981 Avoid some memory writes on jr. 
Should improve tight mips function loops a bit.
 2013-01-24 01:23:50 -08:00
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c1757ee166 Check downcount in jit after a syscall. 2013-01-23 22:25:35 -08:00
Henrik Rydgard
29f1ae5f70 add skeleton implementation of "cache" instruction 2013-01-22 22:03:41 +01:00
Henrik Rydgard
82d5ae021e VFPU: cap/floor float-to-int conversion instructions 2013-01-22 22:03:40 +01:00
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dbe597ce64 Buildfix Android, darn. 2013-01-22 08:23:27 -08:00
Unknown W. Brackets
0e33923844 Belt and suspenders check for branch ops. 2013-01-22 08:11:37 -08:00
Unknown W. Brackets
c324983340 Make the jit support bltzal and friends. 
Fixes problems with jit in games.  Android changes completely untested.
 2013-01-22 08:04:01 -08:00
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de2df87758 Make interpreter call Advance() the same as jit. 
Probably makes more sense anyway, since the first events will be
more correctly timed, like savestates, sound, etc.
 2013-01-21 23:16:23 -08:00
Unknown W. Brackets
a9d0390426 Adjust downcount before syscalls, not after. 
This makes jit slightly slower for syscalls, but it's minor and makes
sure jit and interpreter timing are determistically the same.
 2013-01-21 22:57:53 -08:00
Unknown W. Brackets
566b7a0910 A branch was missing inDelaySlot, refactor it. 2013-01-21 22:45:07 -08:00
Unknown W. Brackets
c897e6446a Don't over decr downcount when hitting a jit bp. 2013-01-21 19:41:12 -08:00
Unknown W. Brackets
d99d060c2e Decrement downcount in skipped likely slots. 
Pretty sure this is right, it eats up a cycle as a nop.

Also some funny indentation.
 2013-01-21 19:00:09 -08:00
Unknown W. Brackets
8438371941 Read memory in the jit dispatcher same as lw. 
Just for consistency.  One less op, maybe faster, probably same.
 2013-01-21 17:51:14 -08:00
Henrik Rydgård
65203f3833 Merge pull request #459 from unknownbrackets/jit-branch 
Jit branch debugging
 2013-01-21 00:21:00 -08:00
Unknown W. Brackets
49965b7f1d Decrement downcount in the interpreter. 2013-01-20 21:48:38 -08:00
Unknown W. Brackets
1485b0865c Improve the speed of branch debugging a bit. 2013-01-20 19:48:55 -08:00