mirror of
https://github.com/libretro/px68k-libretro.git
synced 2026-11-07 04:25:57 -10:00
libretroadmin
3bb967da25
Some notes to consider: - consider this wip. some vars might not be necessary. - only for C68K cpu core - minimally tested. it works on HD files, and multi-disks but have not tested on anything that switches to another disk yet or drive letter. - M3U/CMD platlist format is necessary to keep track of what content the state is for (filename for .statex tracking for example). Switching disk or switching to another game through ingame menu will break currently loaded state. - in core is use to run in content-less mode, the savestate will be universal or system state (PX68K.state) and will not be based on what content is loaded. - MIDI: Loading patchsets and other midi params from a state file is not implemented. It may take a while to refresh instruments sets until next time MIDI sends new data. Its also required that only load a state after selecting the correct MIDI device from the ingame menu. - requires new px68k_libretro.info file, with savestate support enabled
642 lines
17 KiB
C
642 lines
17 KiB
C
#include "common.h"
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#include "winx68k.h"
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#include "m68000.h"
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#include "x68kmemory.h"
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#include "irqh.h"
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#include "fdc.h"
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#include "sasi.h"
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#include "adpcm.h"
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#include "mercury.h"
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#include "dmac.h"
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dmac_ch DMA[4];
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static int DMA_IntCH = 0;
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static int DMA_LastInt = 0;
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static int (*IsReady[4])(void) = { 0, 0, 0, 0 };
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static uint32_t FASTCALL DMA_Int(uint8_t irq);
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#define DMAINT(ch) if ( DMA[ch].CCR&0x08 ) { DMA_IntCH |= (1<<ch); IRQH_Int(3, &DMA_Int); }
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#define DMAERR(ch,err) DMA[ch].CER = err; \
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DMA[ch].CSR |= 0x10; \
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DMA[ch].CSR &= 0xf7; \
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DMA[ch].CCR &= 0x7f; \
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DMAINT(ch)
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int DMAC_StateAction(StateMem *sm, int load, int data_only)
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{
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SFORMAT StateRegs[] =
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{
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SFVARN(DMA[0].CSR, "CSR0"),
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SFVARN(DMA[0].CER, "CER0"),
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SFVARN(DMA[0].DCR, "DCR0"),
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SFVARN(DMA[0].OCR, "OCR0"),
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SFVARN(DMA[0].SCR, "SCR0"),
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SFVARN(DMA[0].CCR, "CCR0"),
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SFVARN(DMA[0].MTC, "MTC0"),
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SFVARN(DMA[0].MAR, "MAR0"),
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SFVARN(DMA[0].DAR, "DAR0"),
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SFVARN(DMA[0].BTC, "BTC0"),
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SFVARN(DMA[0].BAR, "BAR0"),
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SFVARN(DMA[0].NIV, "NIV0"),
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SFVARN(DMA[0].EIV, "EIV0"),
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SFVARN(DMA[0].MFC, "MFC0"),
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SFVARN(DMA[0].CPR, "CPR0"),
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SFVARN(DMA[0].DFC, "DFC0"),
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SFVARN(DMA[0].BFC, "BFC0"),
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SFVARN(DMA[0].GCR, "GCR0"),
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SFVARN(DMA[1].CSR, "CSR1"),
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SFVARN(DMA[1].CER, "CER1"),
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SFVARN(DMA[1].DCR, "DCR1"),
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SFVARN(DMA[1].OCR, "OCR1"),
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SFVARN(DMA[1].SCR, "SCR1"),
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SFVARN(DMA[1].CCR, "CCR1"),
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SFVARN(DMA[1].MTC, "MTC1"),
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SFVARN(DMA[1].MAR, "MAR1"),
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SFVARN(DMA[1].DAR, "DAR1"),
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SFVARN(DMA[1].BTC, "BTC1"),
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SFVARN(DMA[1].BAR, "BAR1"),
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SFVARN(DMA[1].NIV, "NIV1"),
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SFVARN(DMA[1].EIV, "EIV1"),
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SFVARN(DMA[1].MFC, "MFC1"),
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SFVARN(DMA[1].CPR, "CPR1"),
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SFVARN(DMA[1].DFC, "DFC1"),
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SFVARN(DMA[1].BFC, "BFC1"),
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SFVARN(DMA[1].GCR, "GCR1"),
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SFVARN(DMA[2].CSR, "CSR2"),
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SFVARN(DMA[2].CER, "CER2"),
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SFVARN(DMA[2].DCR, "DCR2"),
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SFVARN(DMA[2].OCR, "OCR2"),
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SFVARN(DMA[2].SCR, "SCR2"),
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SFVARN(DMA[2].CCR, "CCR2"),
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SFVARN(DMA[2].MTC, "MTC2"),
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SFVARN(DMA[2].MAR, "MAR2"),
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SFVARN(DMA[2].DAR, "DAR2"),
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SFVARN(DMA[2].BTC, "BTC2"),
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SFVARN(DMA[2].BAR, "BAR2"),
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SFVARN(DMA[2].NIV, "NIV2"),
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SFVARN(DMA[2].EIV, "EIV2"),
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SFVARN(DMA[2].MFC, "MFC2"),
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SFVARN(DMA[2].CPR, "CPR2"),
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SFVARN(DMA[2].DFC, "DFC2"),
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SFVARN(DMA[2].BFC, "BFC2"),
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SFVARN(DMA[2].GCR, "GCR2"),
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SFVARN(DMA[3].CSR, "CSR3"),
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SFVARN(DMA[3].CER, "CER3"),
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SFVARN(DMA[3].DCR, "DCR3"),
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SFVARN(DMA[3].OCR, "OCR3"),
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SFVARN(DMA[3].SCR, "SCR3"),
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SFVARN(DMA[3].CCR, "CCR3"),
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SFVARN(DMA[3].MTC, "MTC3"),
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SFVARN(DMA[3].MAR, "MAR3"),
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SFVARN(DMA[3].DAR, "DAR3"),
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SFVARN(DMA[3].BTC, "BTC3"),
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SFVARN(DMA[3].BAR, "BAR3"),
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SFVARN(DMA[3].NIV, "NIV3"),
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SFVARN(DMA[3].EIV, "EIV3"),
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SFVARN(DMA[3].MFC, "MFC3"),
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SFVARN(DMA[3].CPR, "CPR3"),
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SFVARN(DMA[3].DFC, "DFC3"),
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SFVARN(DMA[3].BFC, "BFC3"),
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SFVARN(DMA[3].GCR, "GCR3"),
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SFVAR(DMA_IntCH),
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SFVAR(DMA_LastInt),
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SFEND
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};
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int ret = PX68KSS_StateAction(sm, load, data_only, StateRegs, "X68K_DMAC", false);
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return ret;
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}
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static int ADPCM_IsReady(void) { return 1; }
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static int DMA_DummyIsReady(void) { return 0; }
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static void DMA_SetReadyCB(int ch, int (*func)(void))
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{
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if ( (ch>=0)&&(ch<=3) ) IsReady[ch] = func;
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}
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static uint32_t FASTCALL DMA_Int(uint8_t irq)
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{
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uint32_t ret = 0xffffffff;
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int bit = 0;
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int i = DMA_LastInt;
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IRQH_IRQCallBack(irq);
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if ( irq==3 ) {
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do {
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bit = 1<<i;
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if ( DMA_IntCH&bit ) {
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if ( (DMA[i].CSR)&0x10 )
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ret = ((uint32_t)(DMA[i].EIV));
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else
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ret = ((uint32_t)(DMA[i].NIV));
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DMA_IntCH &= ~bit;
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break;
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}
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i = (i+1)&3;
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} while ( i!=DMA_LastInt );
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}
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DMA_LastInt = i;
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if ( DMA_IntCH ) IRQH_Int(3, &DMA_Int);
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return ret;
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}
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uint8_t FASTCALL DMA_Read(uint32_t adr)
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{
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int off = adr & 0x3f;
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int ch = (adr >> 6) & 0x03;
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if (adr >= 0xe84100)
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return 0;
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switch (off)
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{
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case 0x00:
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if ((ch == 2) && (off == 0))
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{
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#ifndef NO_MERCURY
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DMA[ch].CSR = (DMA[ch].CSR & 0xfe) | (Mcry_LRTiming & 1);
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#else
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DMA[ch].CSR = (DMA[ch].CSR & 0xfe);
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Mcry_LRTiming ^= 1;
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#endif
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}
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return DMA[ch].CSR;
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case 0x01:
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return DMA[ch].CER;
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case 0x04:
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return DMA[ch].DCR;
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case 0x05:
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return DMA[ch].OCR;
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case 0x06:
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return DMA[ch].SCR;
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case 0x07:
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return DMA[ch].CCR;
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case 0x0a:
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return (DMA[ch].MTC >> 8) & 0xff;
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case 0x0b:
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return DMA[ch].MTC & 0xff;
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case 0x0c:
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return (DMA[ch].MAR >> 24) & 0xff;
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case 0x0d:
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return (DMA[ch].MAR >> 16) & 0xff;
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case 0x0e:
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return (DMA[ch].MAR >> 8) & 0xff;
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case 0x0f:
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return DMA[ch].MAR & 0xff;
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case 0x14:
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return (DMA[ch].DAR >> 24) & 0xff;
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case 0x15:
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return (DMA[ch].DAR >> 16) & 0xff;
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case 0x16:
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return (DMA[ch].DAR >> 8) & 0xff;
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case 0x17:
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return DMA[ch].DAR & 0xff;
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case 0x1a:
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return (DMA[ch].BTC >> 8) & 0xff;
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case 0x1b:
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return DMA[ch].BTC & 0xff;
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case 0x1c:
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return (DMA[ch].BAR >> 24) & 0xff;
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case 0x1d:
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return (DMA[ch].BAR >> 16) & 0xff;
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case 0x1e:
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return (DMA[ch].BAR >> 8) & 0xff;
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case 0x1f:
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return DMA[ch].BAR & 0xff;
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case 0x25:
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return DMA[ch].NIV;
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case 0x27:
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return DMA[ch].EIV;
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case 0x29:
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return DMA[ch].MFC;
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case 0x2d:
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return DMA[ch].CPR;
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case 0x31:
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return DMA[ch].DFC;
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case 0x39:
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return DMA[ch].BFC;
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case 0x3f:
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return DMA[ch].GCR;
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}
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return 0;
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}
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void FASTCALL DMA_Write(uint32_t adr, uint8_t data)
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{
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int off = adr & 0x3f;
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int ch = (adr >> 6) & 0x03;
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uint8_t old = 0;
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if (adr >= 0xe84100)
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return;
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switch (off)
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{
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case 0x00:
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DMA[ch].CSR &= ((~data) | 0x09);
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break;
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case 0x01:
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DMA[ch].CER &= (~data);
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break;
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case 0x04:
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DMA[ch].DCR = data;
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break;
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case 0x05:
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DMA[ch].OCR = data;
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break;
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case 0x06:
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DMA[ch].SCR = data;
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break;
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case 0x07:
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old = DMA[ch].CCR;
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DMA[ch].CCR = (data & 0xef) | (DMA[ch].CCR & 0x80); /* CCR STR cannot be dropped by writing */
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if ((data & 0x10) && (DMA[ch].CCR & 0x80))
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{
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/* Software Abort */
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DMAERR(ch, 0x11)
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break;
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}
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if (data & 0x20) /* Halt */
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{
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/* Should be correct, but Nemesis'90 will not work properly with it so... */
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/* DMA[ch].CSR &= 0xf7; */
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break;
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}
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if (data & 0x80)
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{
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/* Start DMA */
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if (old & 0x20)
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{
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/* Halt release */
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DMA[ch].CSR |= 0x08;
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DMA_Exec(ch);
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}
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else
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{
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if (DMA[ch].CSR & 0xf8)
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{
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/* Timing errors */
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DMAERR(ch, 0x02)
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break;
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}
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DMA[ch].CSR |= 0x08;
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if ((DMA[ch].OCR & 8) /*&&(!DMA[ch].MTC)*/)
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{
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/* Array/Link Array Chain */
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DMA[ch].MAR = dma_readmem24_dword(DMA[ch].BAR) & 0xffffff;
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DMA[ch].MTC = dma_readmem24_word(DMA[ch].BAR + 4);
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if (DMA[ch].OCR & 4)
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{
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DMA[ch].BAR = dma_readmem24_dword(DMA[ch].BAR + 6);
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}
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else
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{
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DMA[ch].BAR += 6;
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if (!DMA[ch].BTC)
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{
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/* This is also a counting error */
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DMAERR(ch, 0x0f)
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break;
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}
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}
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}
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if (!DMA[ch].MTC)
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{
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/* Counting error */
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DMAERR(ch, 0x0d)
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break;
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}
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DMA[ch].CER = 0x00;
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DMA_Exec(ch); /* Since you may need to check the counter immediately after starting, run it for a little while. */
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}
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}
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if ((data & 0x40) && (!DMA[ch].MTC))
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{
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/* Continuous Op. */
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if (DMA[ch].CCR & 0x80)
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{
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if (DMA[ch].CCR & 0x40)
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{
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DMAERR(ch, 0x02)
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}
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else if (DMA[ch].OCR & 8)
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{
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/* Array/Link Array Chain */
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DMAERR(ch, 0x01)
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}
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else
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{
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DMA[ch].MAR = DMA[ch].BAR;
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DMA[ch].MTC = DMA[ch].BTC;
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DMA[ch].CSR |= 0x08;
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DMA[ch].BAR = 0;
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DMA[ch].BTC = 0;
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if (!DMA[ch].MAR)
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{
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DMA[ch].CSR |= 0x40; /* Block transfer end bit/interrupt? */
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DMAINT(ch)
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break;
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}
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else if (!DMA[ch].MTC)
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{
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DMAERR(ch, 0x0d)
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break;
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}
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DMA[ch].CCR &= 0xbf;
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DMA_Exec(ch);
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}
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}
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else
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{
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/* The CNT bit in non-active mode indicates an operation timing error */
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DMAERR(ch, 0x02)
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}
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}
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break;
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case 0x0a:
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DMA[ch].MTC &= 0x00ff;
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DMA[ch].MTC |= (data << 8);
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break;
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case 0x0b:
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DMA[ch].MTC &= 0xff00;
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DMA[ch].MTC |= data;
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break;
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case 0x0c:
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break;
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case 0x0d:
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DMA[ch].MAR &= 0x0000ffff;
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DMA[ch].MAR |= (data << 16);
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break;
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case 0x0e:
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DMA[ch].MAR &= 0x00ff00ff;
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DMA[ch].MAR |= (data << 8);
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break;
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case 0x0f:
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DMA[ch].MAR &= 0x00ffff00;
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DMA[ch].MAR |= data;
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break;
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case 0x14:
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break;
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case 0x15:
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DMA[ch].DAR &= 0x0000ffff;
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DMA[ch].DAR |= (data << 16);
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break;
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case 0x16:
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DMA[ch].DAR &= 0x00ff00ff;
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DMA[ch].DAR |= (data << 8);
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break;
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case 0x17:
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DMA[ch].DAR &= 0x00ffff00;
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DMA[ch].DAR |= data;
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break;
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case 0x1a:
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DMA[ch].BTC &= 0x00ff;
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DMA[ch].BTC |= (data << 8);
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break;
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case 0x1b:
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DMA[ch].BTC &= 0xff00;
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DMA[ch].BTC |= data;
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break;
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case 0x1c:
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break;
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case 0x1d:
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DMA[ch].BAR &= 0x0000ffff;
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DMA[ch].BAR |= (data << 16);
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break;
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case 0x1e:
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DMA[ch].BAR &= 0x00ff00ff;
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DMA[ch].BAR |= (data << 8);
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break;
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case 0x1f:
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DMA[ch].BAR &= 0x00ffff00;
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DMA[ch].BAR |= data;
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break;
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case 0x25:
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DMA[ch].NIV = data;
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break;
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case 0x27:
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DMA[ch].EIV = data;
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break;
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case 0x29:
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DMA[ch].MFC = data;
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break;
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case 0x2d:
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DMA[ch].CPR = data;
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break;
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case 0x31:
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DMA[ch].DFC = data;
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break;
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case 0x39:
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DMA[ch].BFC = data;
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break;
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case 0x3f:
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if (ch == 3)
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DMA[ch].GCR = data;
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break;
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}
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}
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int FASTCALL DMA_Exec(int ch)
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{
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uint32_t *src, *dst;
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if ( DMA[ch].OCR&0x80 ) { /* Device->Memory */
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src = &DMA[ch].DAR;
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dst = &DMA[ch].MAR;
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} else { /* Memory->Device */
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src = &DMA[ch].MAR;
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dst = &DMA[ch].DAR;
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}
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while ( (DMA[ch].CSR&0x08) && (!(DMA[ch].CCR&0x20)) && (!(DMA[ch].CSR&0x80)) && (DMA[ch].MTC) && (((DMA[ch].OCR&3)!=2)||(IsReady[ch]())) ) {
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BusErrFlag = 0;
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switch ( ((DMA[ch].OCR>>4)&3)+((DMA[ch].DCR>>1)&4) ) {
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case 0:
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case 3:
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dma_writemem24(*dst, dma_readmem24(*src));
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if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
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if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
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break;
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case 1:
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dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
break;
|
|
case 2:
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
break;
|
|
case 4:
|
|
dma_writemem24(*dst, dma_readmem24(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 1; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 1;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 1; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 1;
|
|
break;
|
|
case 5:
|
|
dma_writemem24_word(*dst, dma_readmem24_word(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 2; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 2;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 2; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 2;
|
|
break;
|
|
case 6:
|
|
dma_writemem24_dword(*dst, dma_readmem24_dword(*src));
|
|
if ( DMA[ch].SCR&4 ) DMA[ch].MAR += 4; else if ( DMA[ch].SCR&8 ) DMA[ch].MAR -= 4;
|
|
if ( DMA[ch].SCR&1 ) DMA[ch].DAR += 4; else if ( DMA[ch].SCR&2 ) DMA[ch].DAR -= 4;
|
|
break;
|
|
}
|
|
|
|
if ( BusErrFlag ) {
|
|
switch ( BusErrFlag ) {
|
|
case 1: /* BusErr/Read */
|
|
if ( DMA[ch].OCR&0x80 ) /* Device->Memory */
|
|
DMAERR(ch,0x0a)
|
|
else
|
|
DMAERR(ch,0x09)
|
|
break;
|
|
case 2: /* BusErr/Write */
|
|
if ( DMA[ch].OCR&0x80 ) /* Device->Memory */
|
|
DMAERR(ch,0x09)
|
|
else
|
|
DMAERR(ch,0x0a)
|
|
break;
|
|
case 3: /* AdrErr/Read */
|
|
if ( DMA[ch].OCR&0x80 ) /* Device->Memory */
|
|
DMAERR(ch,0x06)
|
|
else
|
|
DMAERR(ch,0x05)
|
|
break;
|
|
case 4: /* BusErr/Write */
|
|
if ( DMA[ch].OCR&0x80 ) /* Device->Memory */
|
|
DMAERR(ch,0x05)
|
|
else
|
|
DMAERR(ch,0x06)
|
|
break;
|
|
}
|
|
BusErrFlag = 0;
|
|
break;
|
|
}
|
|
|
|
DMA[ch].MTC--;
|
|
if ( !DMA[ch].MTC ) { /* Transfer of specified number of bytes completed */
|
|
if ( DMA[ch].OCR&8 ) { /* If running in chained mode */
|
|
if ( DMA[ch].OCR&4 ) { /* If running in chained mode */
|
|
if ( DMA[ch].BAR ) {
|
|
DMA[ch].MAR = dma_readmem24_dword(DMA[ch].BAR);
|
|
DMA[ch].MTC = dma_readmem24_word(DMA[ch].BAR+4);
|
|
DMA[ch].BAR = dma_readmem24_dword(DMA[ch].BAR+6);
|
|
if ( BusErrFlag ) {
|
|
if ( BusErrFlag==1 )
|
|
DMAERR(ch,0x0b)
|
|
else
|
|
DMAERR(ch,0x07)
|
|
BusErrFlag = 0;
|
|
break;
|
|
} else if ( !DMA[ch].MTC ) {
|
|
DMAERR(ch,0x0d)
|
|
break;
|
|
}
|
|
}
|
|
} else { /* Array chain */
|
|
DMA[ch].BTC--;
|
|
if ( DMA[ch].BTC ) { /* Next block exists */
|
|
DMA[ch].MAR = dma_readmem24_dword(DMA[ch].BAR);
|
|
DMA[ch].MTC = dma_readmem24_word(DMA[ch].BAR+4);
|
|
DMA[ch].BAR += 6;
|
|
if ( BusErrFlag ) {
|
|
if ( BusErrFlag==1 )
|
|
DMAERR(ch,0x0b)
|
|
else
|
|
DMAERR(ch,0x07)
|
|
BusErrFlag = 0;
|
|
break;
|
|
} else if ( !DMA[ch].MTC ) {
|
|
DMAERR(ch,0x0d)
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
} else { /* Normal mode (only one block) finished */
|
|
if ( DMA[ch].CCR&0x40 ) { /* Countinuous action */
|
|
DMA[ch].CSR |= 0x40; /* Block transfer end bit/interrupt */
|
|
DMAINT(ch)
|
|
if ( DMA[ch].BAR ) {
|
|
DMA[ch].MAR = DMA[ch].BAR;
|
|
DMA[ch].MTC = DMA[ch].BTC;
|
|
DMA[ch].CSR |= 0x08;
|
|
DMA[ch].BAR = 0x00;
|
|
DMA[ch].BTC = 0x00;
|
|
if ( !DMA[ch].MTC ) {
|
|
DMAERR(ch,0x0d)
|
|
break;
|
|
}
|
|
DMA[ch].CCR &= 0xbf;
|
|
}
|
|
}
|
|
}
|
|
if ( !DMA[ch].MTC ) {
|
|
DMA[ch].CSR |= 0x80;
|
|
DMA[ch].CSR &= 0xf7;
|
|
DMAINT(ch)
|
|
}
|
|
}
|
|
if ( (DMA[ch].OCR&3)!=1 ) break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void DMA_Init(void)
|
|
{
|
|
int i;
|
|
DMA_IntCH = 0;
|
|
DMA_LastInt = 0;
|
|
for (i=0; i<4; i++) {
|
|
memset(&DMA[i], 0, sizeof(dmac_ch));
|
|
DMA[i].CSR = 0;
|
|
DMA[i].CCR = 0;
|
|
DMA_SetReadyCB(i, DMA_DummyIsReady);
|
|
}
|
|
DMA_SetReadyCB(0, FDC_IsDataReady);
|
|
DMA_SetReadyCB(1, SASI_IsReady);
|
|
#ifndef NO_MERCURY
|
|
DMA_SetReadyCB(2, Mcry_IsReady);
|
|
#endif
|
|
DMA_SetReadyCB(3, ADPCM_IsReady);
|
|
}
|