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extended(core): move to LLVM 23

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This commit is contained in:
lief-agent
2026-10-04 19:59:30 +02:00
parent 351d5f14a1
commit bbf2237dec
35 changed files with 182612 additions and 176632 deletions
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api/python/lief/assembly/aarch64/__init__.pyi
+9163 -9065
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api/python/lief/assembly/arm.pyi
+4442 -4418
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api/python/lief/assembly/ebpf/__init__.pyi
+446 -422
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api/python/lief/assembly/mips/__init__.pyi
+2825 -2819
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api/python/lief/assembly/powerpc/__init__.pyi
+2809 -2797
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api/python/lief/assembly/riscv/__init__.pyi
+18250 -16692
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api/python/lief/assembly/x86/__init__.pyi
+22464 -22194
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api/python/src/asm/aarch64/pyOpcode.cpp
+190 -133
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@@ -108,10 +108,12 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_LOAD", LIEF::assembly::aarch64::OPCODE::G_LOAD)
.value("G_SEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_SEXTLOAD)
.value("G_ZEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_ZEXTLOAD)
.value("G_FPEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_FPEXTLOAD)
.value("G_INDEXED_LOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_LOAD)
.value("G_INDEXED_SEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_SEXTLOAD)
.value("G_INDEXED_ZEXTLOAD", LIEF::assembly::aarch64::OPCODE::G_INDEXED_ZEXTLOAD)
.value("G_STORE", LIEF::assembly::aarch64::OPCODE::G_STORE)
.value("G_FPTRUNCSTORE", LIEF::assembly::aarch64::OPCODE::G_FPTRUNCSTORE)
.value("G_INDEXED_STORE", LIEF::assembly::aarch64::OPCODE::G_INDEXED_STORE)
.value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::aarch64::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
.value("G_ATOMIC_CMPXCHG", LIEF::assembly::aarch64::OPCODE::G_ATOMIC_CMPXCHG)
@@ -132,6 +134,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_ATOMICRMW_FMIN", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMIN)
.value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMAXIMUM)
.value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMINIMUM)
.value("G_ATOMICRMW_FMAXIMUMNUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMAXIMUMNUM)
.value("G_ATOMICRMW_FMINIMUMNUM", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_FMINIMUMNUM)
.value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UINC_WRAP)
.value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_UDEC_WRAP)
.value("G_ATOMICRMW_USUB_COND", LIEF::assembly::aarch64::OPCODE::G_ATOMICRMW_USUB_COND)
@@ -263,12 +267,14 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_STEP_VECTOR", LIEF::assembly::aarch64::OPCODE::G_STEP_VECTOR)
.value("G_VECTOR_COMPRESS", LIEF::assembly::aarch64::OPCODE::G_VECTOR_COMPRESS)
.value("G_CTTZ", LIEF::assembly::aarch64::OPCODE::G_CTTZ)
.value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::aarch64::OPCODE::G_CTTZ_ZERO_UNDEF)
.value("G_CTTZ_ZERO_POISON", LIEF::assembly::aarch64::OPCODE::G_CTTZ_ZERO_POISON)
.value("G_CTLZ", LIEF::assembly::aarch64::OPCODE::G_CTLZ)
.value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::aarch64::OPCODE::G_CTLZ_ZERO_UNDEF)
.value("G_CTLZ_ZERO_POISON", LIEF::assembly::aarch64::OPCODE::G_CTLZ_ZERO_POISON)
.value("G_CTLS", LIEF::assembly::aarch64::OPCODE::G_CTLS)
.value("G_CTPOP", LIEF::assembly::aarch64::OPCODE::G_CTPOP)
.value("G_BSWAP", LIEF::assembly::aarch64::OPCODE::G_BSWAP)
.value("G_BITREVERSE", LIEF::assembly::aarch64::OPCODE::G_BITREVERSE)
.value("G_CLMUL", LIEF::assembly::aarch64::OPCODE::G_CLMUL)
.value("G_FCEIL", LIEF::assembly::aarch64::OPCODE::G_FCEIL)
.value("G_FCOS", LIEF::assembly::aarch64::OPCODE::G_FCOS)
.value("G_FSIN", LIEF::assembly::aarch64::OPCODE::G_FSIN)
@@ -299,14 +305,17 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_STRICT_FMA", LIEF::assembly::aarch64::OPCODE::G_STRICT_FMA)
.value("G_STRICT_FSQRT", LIEF::assembly::aarch64::OPCODE::G_STRICT_FSQRT)
.value("G_STRICT_FLDEXP", LIEF::assembly::aarch64::OPCODE::G_STRICT_FLDEXP)
.value("G_STRICT_FCMP", LIEF::assembly::aarch64::OPCODE::G_STRICT_FCMP);
opcodes.value("G_STRICT_FCMPS", LIEF::assembly::aarch64::OPCODE::G_STRICT_FCMPS)
.value("G_READ_REGISTER", LIEF::assembly::aarch64::OPCODE::G_READ_REGISTER)
.value("G_WRITE_REGISTER", LIEF::assembly::aarch64::OPCODE::G_WRITE_REGISTER)
.value("G_MEMCPY", LIEF::assembly::aarch64::OPCODE::G_MEMCPY)
.value("G_MEMCPY_INLINE", LIEF::assembly::aarch64::OPCODE::G_MEMCPY_INLINE)
.value("G_MEMMOVE", LIEF::assembly::aarch64::OPCODE::G_MEMMOVE)
.value("G_MEMSET", LIEF::assembly::aarch64::OPCODE::G_MEMSET)
.value("G_BZERO", LIEF::assembly::aarch64::OPCODE::G_BZERO);
opcodes.value("G_TRAP", LIEF::assembly::aarch64::OPCODE::G_TRAP)
.value("G_BZERO", LIEF::assembly::aarch64::OPCODE::G_BZERO)
.value("G_MEMSET_INLINE", LIEF::assembly::aarch64::OPCODE::G_MEMSET_INLINE)
.value("G_TRAP", LIEF::assembly::aarch64::OPCODE::G_TRAP)
.value("G_DEBUGTRAP", LIEF::assembly::aarch64::OPCODE::G_DEBUGTRAP)
.value("G_UBSANTRAP", LIEF::assembly::aarch64::OPCODE::G_UBSANTRAP)
.value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::aarch64::OPCODE::G_VECREDUCE_SEQ_FADD)
@@ -352,6 +361,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("ADD_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4ZZ_S_PSEUDO)
.value("ADD_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_D_PSEUDO)
.value("ADD_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_VG4_M4Z_S_PSEUDO)
.value("ADD_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_ZI_B_PSEUDO)
.value("ADD_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_ZI_D_PSEUDO)
.value("ADD_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_ZI_H_PSEUDO)
.value("ADD_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::ADD_ZI_S_PSEUDO)
.value("ADD_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_B_ZERO)
.value("ADD_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_D_ZERO)
.value("ADD_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::ADD_ZPZZ_H_ZERO)
@@ -365,6 +378,7 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("ANDSXrr", LIEF::assembly::aarch64::OPCODE::ANDSXrr)
.value("ANDWrr", LIEF::assembly::aarch64::OPCODE::ANDWrr)
.value("ANDXrr", LIEF::assembly::aarch64::OPCODE::ANDXrr)
.value("AND_ZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::AND_ZI_PSEUDO)
.value("AND_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_B_ZERO)
.value("AND_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_D_ZERO)
.value("AND_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::AND_ZPZZ_H_ZERO)
@@ -392,10 +406,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("AUTH_TCRETURN", LIEF::assembly::aarch64::OPCODE::AUTH_TCRETURN)
.value("AUTH_TCRETURN_BTI", LIEF::assembly::aarch64::OPCODE::AUTH_TCRETURN_BTI)
.value("AUTPAC", LIEF::assembly::aarch64::OPCODE::AUTPAC)
.value("AUTPCPAC", LIEF::assembly::aarch64::OPCODE::AUTPCPAC)
.value("AUTRELLOADPAC", LIEF::assembly::aarch64::OPCODE::AUTRELLOADPAC)
.value("AUTx16x17", LIEF::assembly::aarch64::OPCODE::AUTx16x17)
.value("AUTxMxN", LIEF::assembly::aarch64::OPCODE::AUTxMxN)
.value("AllocateSMESaveBuffer", LIEF::assembly::aarch64::OPCODE::AllocateSMESaveBuffer)
.value("AllocateZABuffer", LIEF::assembly::aarch64::OPCODE::AllocateZABuffer)
.value("BFADD_VG2_M2Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFADD_VG2_M2Z_H_PSEUDO)
.value("BFADD_VG4_M4Z_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::BFADD_VG4_M4Z_H_PSEUDO)
.value("BFADD_ZPZZ_UNDEF", LIEF::assembly::aarch64::OPCODE::BFADD_ZPZZ_UNDEF)
@@ -530,13 +544,16 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("COALESCER_BARRIER_FPR16", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR16)
.value("COALESCER_BARRIER_FPR32", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR32)
.value("COALESCER_BARRIER_FPR64", LIEF::assembly::aarch64::OPCODE::COALESCER_BARRIER_FPR64)
.value("COPY_INTO_TRANSPOSED_TUPLE", LIEF::assembly::aarch64::OPCODE::COPY_INTO_TRANSPOSED_TUPLE)
.value("CommitZASavePseudo", LIEF::assembly::aarch64::OPCODE::CommitZASavePseudo)
.value("EMITBKEY", LIEF::assembly::aarch64::OPCODE::EMITBKEY)
.value("EMITMTETAGGED", LIEF::assembly::aarch64::OPCODE::EMITMTETAGGED)
.value("EONWrr", LIEF::assembly::aarch64::OPCODE::EONWrr)
.value("EONXrr", LIEF::assembly::aarch64::OPCODE::EONXrr)
.value("EON_ZZZ", LIEF::assembly::aarch64::OPCODE::EON_ZZZ)
.value("EORWrr", LIEF::assembly::aarch64::OPCODE::EORWrr)
.value("EORXrr", LIEF::assembly::aarch64::OPCODE::EORXrr)
.value("EOR_ZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::EOR_ZI_PSEUDO)
.value("EOR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_B_ZERO)
.value("EOR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_D_ZERO)
.value("EOR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::EOR_ZPZZ_H_ZERO)
@@ -588,8 +605,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FCVTZU_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_DtoS_UNDEF)
.value("FCVTZU_ZPmZ_HtoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoD_UNDEF)
.value("FCVTZU_ZPmZ_HtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoH_UNDEF)
.value("FCVTZU_ZPmZ_HtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoS_UNDEF)
.value("FCVTZU_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoD_UNDEF)
.value("FCVTZU_ZPmZ_HtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_HtoS_UNDEF);
opcodes.value("FCVTZU_ZPmZ_StoD_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoD_UNDEF)
.value("FCVTZU_ZPmZ_StoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVTZU_ZPmZ_StoS_UNDEF)
.value("FCVT_ZPmZ_DtoH_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoH_UNDEF)
.value("FCVT_ZPmZ_DtoS_UNDEF", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoS_UNDEF)
@@ -605,8 +622,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FDIV_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_H_UNDEF)
.value("FDIV_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_H_ZERO)
.value("FDIV_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_S_UNDEF)
.value("FDIV_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_S_ZERO);
opcodes.value("FDOT_VG2_M2Z2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoH_PSEUDO)
.value("FDIV_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FDIV_ZPZZ_S_ZERO)
.value("FDOT_VG2_M2Z2Z_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoH_PSEUDO)
.value("FDOT_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_BtoS_PSEUDO)
.value("FDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2Z2Z_HtoS_PSEUDO)
.value("FDOT_VG2_M2ZZI_BtoH_PSEUDO", LIEF::assembly::aarch64::OPCODE::FDOT_VG2_M2ZZI_BtoH_PSEUDO)
@@ -888,8 +905,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FSUB_ZPZI_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_S_UNDEF)
.value("FSUB_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZI_S_ZERO)
.value("FSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_D_UNDEF)
.value("FSUB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_D_ZERO)
.value("FSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_H_UNDEF)
.value("FSUB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_D_ZERO);
opcodes.value("FSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_H_UNDEF)
.value("FSUB_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_H_ZERO)
.value("FSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_S_UNDEF)
.value("FSUB_ZPZZ_S_ZERO", LIEF::assembly::aarch64::OPCODE::FSUB_ZPZZ_S_ZERO)
@@ -905,8 +922,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_AARCH64_PREFETCH", LIEF::assembly::aarch64::OPCODE::G_AARCH64_PREFETCH)
.value("G_AARCH64_RANGE_PREFETCH", LIEF::assembly::aarch64::OPCODE::G_AARCH64_RANGE_PREFETCH)
.value("G_ADD_LOW", LIEF::assembly::aarch64::OPCODE::G_ADD_LOW)
.value("G_BSP", LIEF::assembly::aarch64::OPCODE::G_BSP);
opcodes.value("G_DUP", LIEF::assembly::aarch64::OPCODE::G_DUP)
.value("G_BSP", LIEF::assembly::aarch64::OPCODE::G_BSP)
.value("G_DUP", LIEF::assembly::aarch64::OPCODE::G_DUP)
.value("G_DUPLANE16", LIEF::assembly::aarch64::OPCODE::G_DUPLANE16)
.value("G_DUPLANE32", LIEF::assembly::aarch64::OPCODE::G_DUPLANE32)
.value("G_DUPLANE64", LIEF::assembly::aarch64::OPCODE::G_DUPLANE64)
@@ -917,7 +934,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_FCMGT", LIEF::assembly::aarch64::OPCODE::G_FCMGT)
.value("G_FPTRUNC_ODD", LIEF::assembly::aarch64::OPCODE::G_FPTRUNC_ODD)
.value("G_PMULL", LIEF::assembly::aarch64::OPCODE::G_PMULL)
.value("G_REV16", LIEF::assembly::aarch64::OPCODE::G_REV16)
.value("G_REV32", LIEF::assembly::aarch64::OPCODE::G_REV32)
.value("G_REV64", LIEF::assembly::aarch64::OPCODE::G_REV64)
.value("G_SADDLP", LIEF::assembly::aarch64::OPCODE::G_SADDLP)
@@ -944,7 +960,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("G_VLSHR", LIEF::assembly::aarch64::OPCODE::G_VLSHR)
.value("G_ZIP1", LIEF::assembly::aarch64::OPCODE::G_ZIP1)
.value("G_ZIP2", LIEF::assembly::aarch64::OPCODE::G_ZIP2)
.value("GetSMESaveSize", LIEF::assembly::aarch64::OPCODE::GetSMESaveSize)
.value("HOM_Epilog", LIEF::assembly::aarch64::OPCODE::HOM_Epilog)
.value("HOM_Prolog", LIEF::assembly::aarch64::OPCODE::HOM_Prolog)
.value("HWASAN_CHECK_MEMACCESS", LIEF::assembly::aarch64::OPCODE::HWASAN_CHECK_MEMACCESS)
@@ -963,7 +978,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("INSERT_MXIPZ_V_PSEUDO_S", LIEF::assembly::aarch64::OPCODE::INSERT_MXIPZ_V_PSEUDO_S)
.value("IRGstack", LIEF::assembly::aarch64::OPCODE::IRGstack)
.value("InOutZAUsePseudo", LIEF::assembly::aarch64::OPCODE::InOutZAUsePseudo)
.value("InitTPIDR2Obj", LIEF::assembly::aarch64::OPCODE::InitTPIDR2Obj)
.value("JumpTableDest16", LIEF::assembly::aarch64::OPCODE::JumpTableDest16)
.value("JumpTableDest32", LIEF::assembly::aarch64::OPCODE::JumpTableDest32)
.value("JumpTableDest8", LIEF::assembly::aarch64::OPCODE::JumpTableDest8)
@@ -1130,14 +1144,20 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("MSR_FPMR", LIEF::assembly::aarch64::OPCODE::MSR_FPMR)
.value("MSR_FPSR", LIEF::assembly::aarch64::OPCODE::MSR_FPSR)
.value("MSRpstatePseudo", LIEF::assembly::aarch64::OPCODE::MSRpstatePseudo)
.value("MUL_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::MUL_ZI_B_PSEUDO)
.value("MUL_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::MUL_ZI_D_PSEUDO)
.value("MUL_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::MUL_ZI_H_PSEUDO)
.value("MUL_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::MUL_ZI_S_PSEUDO)
.value("MUL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_B_UNDEF)
.value("MUL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_D_UNDEF)
.value("MUL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_H_UNDEF)
.value("MUL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::MUL_ZPZZ_S_UNDEF)
.value("NAND_ZZZ", LIEF::assembly::aarch64::OPCODE::NAND_ZZZ)
.value("NEG_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_B_UNDEF)
.value("NEG_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_D_UNDEF)
.value("NEG_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_H_UNDEF)
.value("NEG_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::NEG_ZPmZ_S_UNDEF)
.value("NOR_ZZZ", LIEF::assembly::aarch64::OPCODE::NOR_ZZZ)
.value("NOT_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_B_UNDEF)
.value("NOT_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_D_UNDEF)
.value("NOT_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::NOT_ZPmZ_H_UNDEF)
@@ -1146,6 +1166,7 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("ORNXrr", LIEF::assembly::aarch64::OPCODE::ORNXrr)
.value("ORRWrr", LIEF::assembly::aarch64::OPCODE::ORRWrr)
.value("ORRXrr", LIEF::assembly::aarch64::OPCODE::ORRXrr)
.value("ORR_ZI_PSEUDO", LIEF::assembly::aarch64::OPCODE::ORR_ZI_PSEUDO)
.value("ORR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_B_ZERO)
.value("ORR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_D_ZERO)
.value("ORR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::ORR_ZPZZ_H_ZERO)
@@ -1158,6 +1179,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("PROBED_STACKALLOC_VAR", LIEF::assembly::aarch64::OPCODE::PROBED_STACKALLOC_VAR)
.value("PTEST_PP_ANY", LIEF::assembly::aarch64::OPCODE::PTEST_PP_ANY)
.value("PTEST_PP_FIRST", LIEF::assembly::aarch64::OPCODE::PTEST_PP_FIRST)
.value("READ_REGISTER_FPR64", LIEF::assembly::aarch64::OPCODE::READ_REGISTER_FPR64)
.value("READ_REGISTER_GPR64", LIEF::assembly::aarch64::OPCODE::READ_REGISTER_GPR64)
.value("RET_ReallyLR", LIEF::assembly::aarch64::OPCODE::RET_ReallyLR)
.value("RequiresZASavePseudo", LIEF::assembly::aarch64::OPCODE::RequiresZASavePseudo)
.value("RequiresZT0SavePseudo", LIEF::assembly::aarch64::OPCODE::RequiresZT0SavePseudo)
@@ -1182,8 +1205,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SDOT_VG2_M2ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HToS_PSEUDO)
.value("SDOT_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZI_HtoD_PSEUDO)
.value("SDOT_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_BtoS_PSEUDO)
.value("SDOT_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoD_PSEUDO)
.value("SDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoS_PSEUDO)
.value("SDOT_VG2_M2ZZ_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoD_PSEUDO);
opcodes.value("SDOT_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG2_M2ZZ_HtoS_PSEUDO)
.value("SDOT_VG4_M4Z4Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_BtoS_PSEUDO)
.value("SDOT_VG4_M4Z4Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoD_PSEUDO)
.value("SDOT_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::SDOT_VG4_M4Z4Z_HtoS_PSEUDO)
@@ -1205,8 +1228,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SEH_SaveAnyRegQP", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegQP)
.value("SEH_SaveAnyRegQPX", LIEF::assembly::aarch64::OPCODE::SEH_SaveAnyRegQPX)
.value("SEH_SaveFPLR", LIEF::assembly::aarch64::OPCODE::SEH_SaveFPLR)
.value("SEH_SaveFPLR_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFPLR_X);
opcodes.value("SEH_SaveFReg", LIEF::assembly::aarch64::OPCODE::SEH_SaveFReg)
.value("SEH_SaveFPLR_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFPLR_X)
.value("SEH_SaveFReg", LIEF::assembly::aarch64::OPCODE::SEH_SaveFReg)
.value("SEH_SaveFRegP", LIEF::assembly::aarch64::OPCODE::SEH_SaveFRegP)
.value("SEH_SaveFRegP_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFRegP_X)
.value("SEH_SaveFReg_X", LIEF::assembly::aarch64::OPCODE::SEH_SaveFReg_X)
@@ -1222,11 +1245,19 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SHSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_D_UNDEF)
.value("SHSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_H_UNDEF)
.value("SHSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SHSUB_ZPZZ_S_UNDEF)
.value("SMAX_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_B_PSEUDO)
.value("SMAX_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_D_PSEUDO)
.value("SMAX_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_H_PSEUDO)
.value("SMAX_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMAX_ZI_S_PSEUDO)
.value("SMAX_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_B_UNDEF)
.value("SMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_D_UNDEF)
.value("SMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_H_UNDEF)
.value("SMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SMAX_ZPZZ_S_UNDEF)
.value("SMEStateAllocPseudo", LIEF::assembly::aarch64::OPCODE::SMEStateAllocPseudo)
.value("SMIN_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_B_PSEUDO)
.value("SMIN_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_D_PSEUDO)
.value("SMIN_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_H_PSEUDO)
.value("SMIN_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SMIN_ZI_S_PSEUDO)
.value("SMIN_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_B_UNDEF)
.value("SMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_D_UNDEF)
.value("SMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SMIN_ZPZZ_H_UNDEF)
@@ -1318,6 +1349,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQABS_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_D_UNDEF)
.value("SQABS_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_H_UNDEF)
.value("SQABS_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQABS_ZPmZ_S_UNDEF)
.value("SQADD_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_B_PSEUDO)
.value("SQADD_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_D_PSEUDO)
.value("SQADD_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_H_PSEUDO)
.value("SQADD_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_S_PSEUDO)
.value("SQNEG_ZPmZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_B_UNDEF)
.value("SQNEG_ZPmZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_D_UNDEF)
.value("SQNEG_ZPmZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQNEG_ZPmZ_H_UNDEF)
@@ -1342,6 +1377,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_D_UNDEF)
.value("SQSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_H_UNDEF)
.value("SQSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPZZ_S_UNDEF)
.value("SQSUB_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_B_PSEUDO)
.value("SQSUB_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_D_PSEUDO)
.value("SQSUB_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_H_PSEUDO)
.value("SQSUB_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SQSUB_ZI_S_PSEUDO)
.value("SRSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_B_UNDEF)
.value("SRSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_D_UNDEF)
.value("SRSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::SRSHL_ZPZZ_H_UNDEF)
@@ -1350,6 +1389,7 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SRSHR_ZPZI_D_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_D_ZERO)
.value("SRSHR_ZPZI_H_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_H_ZERO)
.value("SRSHR_ZPZI_S_ZERO", LIEF::assembly::aarch64::OPCODE::SRSHR_ZPZI_S_ZERO)
.value("STACK_GUARD_UNMIX", LIEF::assembly::aarch64::OPCODE::STACK_GUARD_UNMIX)
.value("STGloop", LIEF::assembly::aarch64::OPCODE::STGloop)
.value("STGloop_wback", LIEF::assembly::aarch64::OPCODE::STGloop_wback)
.value("STMOPA_M2ZZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::STMOPA_M2ZZZI_BtoS_PSEUDO)
@@ -1363,6 +1403,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("STR_ZZZZXI_STRIDED_CONTIGUOUS", LIEF::assembly::aarch64::OPCODE::STR_ZZZZXI_STRIDED_CONTIGUOUS)
.value("STZGloop", LIEF::assembly::aarch64::OPCODE::STZGloop)
.value("STZGloop_wback", LIEF::assembly::aarch64::OPCODE::STZGloop_wback)
.value("SUBR_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_B_PSEUDO)
.value("SUBR_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_D_PSEUDO)
.value("SUBR_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_H_PSEUDO)
.value("SUBR_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUBR_ZI_S_PSEUDO)
.value("SUBR_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_B_ZERO)
.value("SUBR_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_D_ZERO)
.value("SUBR_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::SUBR_ZPZZ_H_ZERO)
@@ -1383,6 +1427,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SUB_VG4_M4ZZ_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4ZZ_S_PSEUDO)
.value("SUB_VG4_M4Z_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_D_PSEUDO)
.value("SUB_VG4_M4Z_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_VG4_M4Z_S_PSEUDO)
.value("SUB_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_ZI_B_PSEUDO)
.value("SUB_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_ZI_D_PSEUDO)
.value("SUB_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_ZI_H_PSEUDO)
.value("SUB_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::SUB_ZI_S_PSEUDO)
.value("SUB_ZPZZ_B_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_B_ZERO)
.value("SUB_ZPZZ_D_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_D_ZERO)
.value("SUB_ZPZZ_H_ZERO", LIEF::assembly::aarch64::OPCODE::SUB_ZPZZ_H_ZERO)
@@ -1457,8 +1505,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UDIV_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UDIV_ZPZZ_S_UNDEF)
.value("UDOT_VG2_M2Z2Z_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_BtoS_PSEUDO)
.value("UDOT_VG2_M2Z2Z_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoD_PSEUDO)
.value("UDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoS_PSEUDO)
.value("UDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_BToS_PSEUDO)
.value("UDOT_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2Z2Z_HtoS_PSEUDO);
opcodes.value("UDOT_VG2_M2ZZI_BToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_BToS_PSEUDO)
.value("UDOT_VG2_M2ZZI_HToS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HToS_PSEUDO)
.value("UDOT_VG2_M2ZZI_HtoD_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZI_HtoD_PSEUDO)
.value("UDOT_VG2_M2ZZ_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UDOT_VG2_M2ZZ_BtoS_PSEUDO)
@@ -1477,10 +1525,18 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UHSUB_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_D_UNDEF)
.value("UHSUB_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_H_UNDEF)
.value("UHSUB_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UHSUB_ZPZZ_S_UNDEF)
.value("UMAX_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_B_PSEUDO)
.value("UMAX_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_D_PSEUDO)
.value("UMAX_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_H_PSEUDO)
.value("UMAX_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMAX_ZI_S_PSEUDO)
.value("UMAX_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_B_UNDEF)
.value("UMAX_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_D_UNDEF)
.value("UMAX_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_H_UNDEF)
.value("UMAX_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UMAX_ZPZZ_S_UNDEF)
.value("UMIN_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_B_PSEUDO)
.value("UMIN_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_D_PSEUDO)
.value("UMIN_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_H_PSEUDO)
.value("UMIN_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMIN_ZI_S_PSEUDO)
.value("UMIN_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_B_UNDEF)
.value("UMIN_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_D_UNDEF)
.value("UMIN_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMIN_ZPZZ_H_UNDEF)
@@ -1505,8 +1561,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UMLAL_MZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_MZZ_HtoS_PSEUDO)
.value("UMLAL_VG2_M2Z2Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2Z2Z_HtoS_PSEUDO)
.value("UMLAL_VG2_M2ZZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZI_S_PSEUDO)
.value("UMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZ_HtoS_PSEUDO);
opcodes.value("UMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4Z4Z_HtoS_PSEUDO)
.value("UMLAL_VG2_M2ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG2_M2ZZ_HtoS_PSEUDO)
.value("UMLAL_VG4_M4Z4Z_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4Z4Z_HtoS_PSEUDO)
.value("UMLAL_VG4_M4ZZI_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZI_HtoS_PSEUDO)
.value("UMLAL_VG4_M4ZZ_HtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLAL_VG4_M4ZZ_HtoS_PSEUDO)
.value("UMLSLL_MZZI_BtoS_PSEUDO", LIEF::assembly::aarch64::OPCODE::UMLSLL_MZZI_BtoS_PSEUDO)
@@ -1567,6 +1623,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UMULH_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_D_UNDEF)
.value("UMULH_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_H_UNDEF)
.value("UMULH_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UMULH_ZPZZ_S_UNDEF)
.value("UQADD_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_B_PSEUDO)
.value("UQADD_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_D_PSEUDO)
.value("UQADD_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_H_PSEUDO)
.value("UQADD_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQADD_ZI_S_PSEUDO)
.value("UQRSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_B_UNDEF)
.value("UQRSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_D_UNDEF)
.value("UQRSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UQRSHL_ZPZZ_H_UNDEF)
@@ -1583,6 +1643,10 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UQSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_D_UNDEF)
.value("UQSHL_ZPZZ_H_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_H_UNDEF)
.value("UQSHL_ZPZZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::UQSHL_ZPZZ_S_UNDEF)
.value("UQSUB_ZI_B_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_B_PSEUDO)
.value("UQSUB_ZI_D_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_D_PSEUDO)
.value("UQSUB_ZI_H_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_H_PSEUDO)
.value("UQSUB_ZI_S_PSEUDO", LIEF::assembly::aarch64::OPCODE::UQSUB_ZI_S_PSEUDO)
.value("URECPE_ZPmZ_S_UNDEF", LIEF::assembly::aarch64::OPCODE::URECPE_ZPmZ_S_UNDEF)
.value("URSHL_ZPZZ_B_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_B_UNDEF)
.value("URSHL_ZPZZ_D_UNDEF", LIEF::assembly::aarch64::OPCODE::URSHL_ZPZZ_D_UNDEF)
@@ -1741,8 +1805,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("ADDXrs", LIEF::assembly::aarch64::OPCODE::ADDXrs)
.value("ADDXrx", LIEF::assembly::aarch64::OPCODE::ADDXrx)
.value("ADDXrx64", LIEF::assembly::aarch64::OPCODE::ADDXrx64)
.value("ADD_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_B)
.value("ADD_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_D)
.value("ADD_VG2_2ZZ_B", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_B);
opcodes.value("ADD_VG2_2ZZ_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_D)
.value("ADD_VG2_2ZZ_H", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_H)
.value("ADD_VG2_2ZZ_S", LIEF::assembly::aarch64::OPCODE::ADD_VG2_2ZZ_S)
.value("ADD_VG2_M2Z2Z_D", LIEF::assembly::aarch64::OPCODE::ADD_VG2_M2Z2Z_D)
@@ -1805,8 +1869,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("AESDIMC_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESDIMC_4ZZI_B)
.value("AESD_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESD_2ZZI_B)
.value("AESD_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESD_4ZZI_B)
.value("AESD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::AESD_ZZZ_B);
opcodes.value("AESDrr", LIEF::assembly::aarch64::OPCODE::AESDrr)
.value("AESD_ZZZ_B", LIEF::assembly::aarch64::OPCODE::AESD_ZZZ_B)
.value("AESDrr", LIEF::assembly::aarch64::OPCODE::AESDrr)
.value("AESEMC_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESEMC_2ZZI_B)
.value("AESEMC_4ZZI_B", LIEF::assembly::aarch64::OPCODE::AESEMC_4ZZI_B)
.value("AESE_2ZZI_B", LIEF::assembly::aarch64::OPCODE::AESE_2ZZI_B)
@@ -1843,7 +1907,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("AND_ZZZ", LIEF::assembly::aarch64::OPCODE::AND_ZZZ)
.value("ANDv16i8", LIEF::assembly::aarch64::OPCODE::ANDv16i8)
.value("ANDv8i8", LIEF::assembly::aarch64::OPCODE::ANDv8i8)
.value("APAS", LIEF::assembly::aarch64::OPCODE::APAS)
.value("ASRD_ZPmI_B", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_B)
.value("ASRD_ZPmI_D", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_D)
.value("ASRD_ZPmI_H", LIEF::assembly::aarch64::OPCODE::ASRD_ZPmI_H)
@@ -2042,8 +2105,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("BFMUL_ZZZ", LIEF::assembly::aarch64::OPCODE::BFMUL_ZZZ)
.value("BFMUL_ZZZI", LIEF::assembly::aarch64::OPCODE::BFMUL_ZZZI)
.value("BFMWri", LIEF::assembly::aarch64::OPCODE::BFMWri)
.value("BFMXri", LIEF::assembly::aarch64::OPCODE::BFMXri)
.value("BFSCALE_2Z2Z", LIEF::assembly::aarch64::OPCODE::BFSCALE_2Z2Z)
.value("BFMXri", LIEF::assembly::aarch64::OPCODE::BFMXri);
opcodes.value("BFSCALE_2Z2Z", LIEF::assembly::aarch64::OPCODE::BFSCALE_2Z2Z)
.value("BFSCALE_2ZZ", LIEF::assembly::aarch64::OPCODE::BFSCALE_2ZZ)
.value("BFSCALE_4Z4Z", LIEF::assembly::aarch64::OPCODE::BFSCALE_4Z4Z)
.value("BFSCALE_4ZZ", LIEF::assembly::aarch64::OPCODE::BFSCALE_4ZZ)
@@ -2093,8 +2156,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("BRAAZ", LIEF::assembly::aarch64::OPCODE::BRAAZ)
.value("BRAB", LIEF::assembly::aarch64::OPCODE::BRAB)
.value("BRABZ", LIEF::assembly::aarch64::OPCODE::BRABZ)
.value("BRB_IALL", LIEF::assembly::aarch64::OPCODE::BRB_IALL)
.value("BRB_INJ", LIEF::assembly::aarch64::OPCODE::BRB_INJ)
.value("BRK", LIEF::assembly::aarch64::OPCODE::BRK)
.value("BRKAS_PPzP", LIEF::assembly::aarch64::OPCODE::BRKAS_PPzP)
.value("BRKA_PPmP", LIEF::assembly::aarch64::OPCODE::BRKA_PPmP)
@@ -2105,8 +2166,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("BRKNS_PPzP", LIEF::assembly::aarch64::OPCODE::BRKNS_PPzP)
.value("BRKN_PPzP", LIEF::assembly::aarch64::OPCODE::BRKN_PPzP)
.value("BRKPAS_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPAS_PPzPP)
.value("BRKPA_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPA_PPzPP);
opcodes.value("BRKPBS_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPBS_PPzPP)
.value("BRKPA_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPA_PPzPP)
.value("BRKPBS_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPBS_PPzPP)
.value("BRKPB_PPzPP", LIEF::assembly::aarch64::OPCODE::BRKPB_PPzPP)
.value("BSL1N_ZZZZ", LIEF::assembly::aarch64::OPCODE::BSL1N_ZZZZ)
.value("BSL2N_ZZZZ", LIEF::assembly::aarch64::OPCODE::BSL2N_ZZZZ)
@@ -2344,8 +2405,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("CMLTv2i32rz", LIEF::assembly::aarch64::OPCODE::CMLTv2i32rz)
.value("CMLTv2i64rz", LIEF::assembly::aarch64::OPCODE::CMLTv2i64rz)
.value("CMLTv4i16rz", LIEF::assembly::aarch64::OPCODE::CMLTv4i16rz)
.value("CMLTv4i32rz", LIEF::assembly::aarch64::OPCODE::CMLTv4i32rz)
.value("CMLTv8i16rz", LIEF::assembly::aarch64::OPCODE::CMLTv8i16rz)
.value("CMLTv4i32rz", LIEF::assembly::aarch64::OPCODE::CMLTv4i32rz);
opcodes.value("CMLTv8i16rz", LIEF::assembly::aarch64::OPCODE::CMLTv8i16rz)
.value("CMLTv8i8rz", LIEF::assembly::aarch64::OPCODE::CMLTv8i8rz)
.value("CMPEQ_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_B)
.value("CMPEQ_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPEQ_PPzZI_D)
@@ -2405,8 +2466,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("CMPLE_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_B)
.value("CMPLE_PPzZI_D", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_D)
.value("CMPLE_PPzZI_H", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_H)
.value("CMPLE_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_S);
opcodes.value("CMPLE_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_B)
.value("CMPLE_PPzZI_S", LIEF::assembly::aarch64::OPCODE::CMPLE_PPzZI_S)
.value("CMPLE_WIDE_PPzZZ_B", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_B)
.value("CMPLE_WIDE_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_H)
.value("CMPLE_WIDE_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::CMPLE_WIDE_PPzZZ_S)
.value("CMPLO_PPzZI_B", LIEF::assembly::aarch64::OPCODE::CMPLO_PPzZI_B)
@@ -2644,8 +2705,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("DUPQ_ZZI_B", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_B)
.value("DUPQ_ZZI_D", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_D)
.value("DUPQ_ZZI_H", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_H)
.value("DUPQ_ZZI_S", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_S)
.value("DUP_ZI_B", LIEF::assembly::aarch64::OPCODE::DUP_ZI_B)
.value("DUPQ_ZZI_S", LIEF::assembly::aarch64::OPCODE::DUPQ_ZZI_S);
opcodes.value("DUP_ZI_B", LIEF::assembly::aarch64::OPCODE::DUP_ZI_B)
.value("DUP_ZI_D", LIEF::assembly::aarch64::OPCODE::DUP_ZI_D)
.value("DUP_ZI_H", LIEF::assembly::aarch64::OPCODE::DUP_ZI_H)
.value("DUP_ZI_S", LIEF::assembly::aarch64::OPCODE::DUP_ZI_S)
@@ -2705,8 +2766,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("EOR_ZI", LIEF::assembly::aarch64::OPCODE::EOR_ZI)
.value("EOR_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_B)
.value("EOR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_D)
.value("EOR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_H);
opcodes.value("EOR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_S)
.value("EOR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_H)
.value("EOR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::EOR_ZPmZ_S)
.value("EOR_ZZZ", LIEF::assembly::aarch64::OPCODE::EOR_ZZZ)
.value("EORv16i8", LIEF::assembly::aarch64::OPCODE::EORv16i8)
.value("EORv8i8", LIEF::assembly::aarch64::OPCODE::EORv8i8)
@@ -2944,8 +3005,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FCMGTv1i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv1i32rz)
.value("FCMGTv1i64rz", LIEF::assembly::aarch64::OPCODE::FCMGTv1i64rz)
.value("FCMGTv2f32", LIEF::assembly::aarch64::OPCODE::FCMGTv2f32)
.value("FCMGTv2f64", LIEF::assembly::aarch64::OPCODE::FCMGTv2f64)
.value("FCMGTv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv2i32rz)
.value("FCMGTv2f64", LIEF::assembly::aarch64::OPCODE::FCMGTv2f64);
opcodes.value("FCMGTv2i32rz", LIEF::assembly::aarch64::OPCODE::FCMGTv2i32rz)
.value("FCMGTv2i64rz", LIEF::assembly::aarch64::OPCODE::FCMGTv2i64rz)
.value("FCMGTv4f16", LIEF::assembly::aarch64::OPCODE::FCMGTv4f16)
.value("FCMGTv4f32", LIEF::assembly::aarch64::OPCODE::FCMGTv4f32)
@@ -3005,8 +3066,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FCMPHri", LIEF::assembly::aarch64::OPCODE::FCMPHri)
.value("FCMPHrr", LIEF::assembly::aarch64::OPCODE::FCMPHrr)
.value("FCMPSri", LIEF::assembly::aarch64::OPCODE::FCMPSri)
.value("FCMPSrr", LIEF::assembly::aarch64::OPCODE::FCMPSrr);
opcodes.value("FCMUO_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_D)
.value("FCMPSrr", LIEF::assembly::aarch64::OPCODE::FCMPSrr)
.value("FCMUO_PPzZZ_D", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_D)
.value("FCMUO_PPzZZ_H", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_H)
.value("FCMUO_PPzZZ_S", LIEF::assembly::aarch64::OPCODE::FCMUO_PPzZZ_S)
.value("FCPY_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FCPY_ZPmI_D)
@@ -3244,8 +3305,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FCVTZSv2i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv2i32_shift)
.value("FCVTZSv2i64_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv2i64_shift)
.value("FCVTZSv4f16", LIEF::assembly::aarch64::OPCODE::FCVTZSv4f16)
.value("FCVTZSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTZSv4f32)
.value("FCVTZSv4i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv4i16_shift)
.value("FCVTZSv4f32", LIEF::assembly::aarch64::OPCODE::FCVTZSv4f32);
opcodes.value("FCVTZSv4i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv4i16_shift)
.value("FCVTZSv4i32_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv4i32_shift)
.value("FCVTZSv8f16", LIEF::assembly::aarch64::OPCODE::FCVTZSv8f16)
.value("FCVTZSv8i16_shift", LIEF::assembly::aarch64::OPCODE::FCVTZSv8i16_shift)
@@ -3305,8 +3366,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FCVT_Z2Z_StoH", LIEF::assembly::aarch64::OPCODE::FCVT_Z2Z_StoH)
.value("FCVT_Z4Z_StoB", LIEF::assembly::aarch64::OPCODE::FCVT_Z4Z_StoB)
.value("FCVT_ZPmZ_DtoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoH)
.value("FCVT_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoS);
opcodes.value("FCVT_ZPmZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoD)
.value("FCVT_ZPmZ_DtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_DtoS)
.value("FCVT_ZPmZ_HtoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoD)
.value("FCVT_ZPmZ_HtoS", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_HtoS)
.value("FCVT_ZPmZ_StoD", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoD)
.value("FCVT_ZPmZ_StoH", LIEF::assembly::aarch64::OPCODE::FCVT_ZPmZ_StoH)
@@ -3544,8 +3605,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FMINQV_H", LIEF::assembly::aarch64::OPCODE::FMINQV_H)
.value("FMINQV_S", LIEF::assembly::aarch64::OPCODE::FMINQV_S)
.value("FMINSrr", LIEF::assembly::aarch64::OPCODE::FMINSrr)
.value("FMINV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_D)
.value("FMINV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_H)
.value("FMINV_VPZ_D", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_D);
opcodes.value("FMINV_VPZ_H", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_H)
.value("FMINV_VPZ_S", LIEF::assembly::aarch64::OPCODE::FMINV_VPZ_S)
.value("FMINVv4i16v", LIEF::assembly::aarch64::OPCODE::FMINVv4i16v)
.value("FMINVv4i32v", LIEF::assembly::aarch64::OPCODE::FMINVv4i32v)
@@ -3605,8 +3666,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FMLALL_VG2_M2ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZI_BtoS)
.value("FMLALL_VG2_M2ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG2_M2ZZ_BtoS)
.value("FMLALL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4Z4Z_BtoS)
.value("FMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZI_BtoS);
opcodes.value("FMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZ_BtoS)
.value("FMLALL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZI_BtoS)
.value("FMLALL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::FMLALL_VG4_M4ZZ_BtoS)
.value("FMLALT_ZZZ", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZ)
.value("FMLALT_ZZZI", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZI)
.value("FMLALT_ZZZI_SHH", LIEF::assembly::aarch64::OPCODE::FMLALT_ZZZI_SHH)
@@ -3844,8 +3905,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FMUL_2ZZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_2ZZ_S)
.value("FMUL_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_D)
.value("FMUL_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_H)
.value("FMUL_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_S)
.value("FMUL_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_D)
.value("FMUL_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::FMUL_4Z4Z_S);
opcodes.value("FMUL_4ZZ_D", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_D)
.value("FMUL_4ZZ_H", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_H)
.value("FMUL_4ZZ_S", LIEF::assembly::aarch64::OPCODE::FMUL_4ZZ_S)
.value("FMUL_ZPmI_D", LIEF::assembly::aarch64::OPCODE::FMUL_ZPmI_D)
@@ -3905,8 +3966,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FNMSUBDrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBDrrr)
.value("FNMSUBHrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBHrrr)
.value("FNMSUBSrrr", LIEF::assembly::aarch64::OPCODE::FNMSUBSrrr)
.value("FNMULDrr", LIEF::assembly::aarch64::OPCODE::FNMULDrr);
opcodes.value("FNMULHrr", LIEF::assembly::aarch64::OPCODE::FNMULHrr)
.value("FNMULDrr", LIEF::assembly::aarch64::OPCODE::FNMULDrr)
.value("FNMULHrr", LIEF::assembly::aarch64::OPCODE::FNMULHrr)
.value("FNMULSrr", LIEF::assembly::aarch64::OPCODE::FNMULSrr)
.value("FRECPE_ZZ_D", LIEF::assembly::aarch64::OPCODE::FRECPE_ZZ_D)
.value("FRECPE_ZZ_H", LIEF::assembly::aarch64::OPCODE::FRECPE_ZZ_H)
@@ -4144,8 +4205,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("FSUBR_ZPmI_S", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmI_S)
.value("FSUBR_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_D)
.value("FSUBR_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_H)
.value("FSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_S)
.value("FSUBSrr", LIEF::assembly::aarch64::OPCODE::FSUBSrr)
.value("FSUBR_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::FSUBR_ZPmZ_S);
opcodes.value("FSUBSrr", LIEF::assembly::aarch64::OPCODE::FSUBSrr)
.value("FSUB_VG2_M2Z_D", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_D)
.value("FSUB_VG2_M2Z_H", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_H)
.value("FSUB_VG2_M2Z_S", LIEF::assembly::aarch64::OPCODE::FSUB_VG2_M2Z_S)
@@ -4205,8 +4266,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("GLD1D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_SCALED)
.value("GLD1D_SXTW", LIEF::assembly::aarch64::OPCODE::GLD1D_SXTW)
.value("GLD1D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_SXTW_SCALED)
.value("GLD1D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW);
opcodes.value("GLD1D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW_SCALED)
.value("GLD1D_UXTW", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW)
.value("GLD1D_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1D_UXTW_SCALED)
.value("GLD1H_D", LIEF::assembly::aarch64::OPCODE::GLD1H_D)
.value("GLD1H_D_IMM", LIEF::assembly::aarch64::OPCODE::GLD1H_D_IMM)
.value("GLD1H_D_SCALED", LIEF::assembly::aarch64::OPCODE::GLD1H_D_SCALED)
@@ -4324,6 +4385,7 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("GLDFF1W_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::GLDFF1W_UXTW_SCALED)
.value("GMI", LIEF::assembly::aarch64::OPCODE::GMI)
.value("HINT", LIEF::assembly::aarch64::OPCODE::HINT)
.value("HINTE", LIEF::assembly::aarch64::OPCODE::HINTE)
.value("HISTCNT_ZPzZZ_D", LIEF::assembly::aarch64::OPCODE::HISTCNT_ZPzZZ_D)
.value("HISTCNT_ZPzZZ_S", LIEF::assembly::aarch64::OPCODE::HISTCNT_ZPzZZ_S)
.value("HISTSEG_ZZZ", LIEF::assembly::aarch64::OPCODE::HISTSEG_ZZZ)
@@ -4443,8 +4505,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LD1Fourv2d_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv2d_POST)
.value("LD1Fourv2s", LIEF::assembly::aarch64::OPCODE::LD1Fourv2s)
.value("LD1Fourv2s_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv2s_POST)
.value("LD1Fourv4h", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h)
.value("LD1Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h_POST)
.value("LD1Fourv4h", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h);
opcodes.value("LD1Fourv4h_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv4h_POST)
.value("LD1Fourv4s", LIEF::assembly::aarch64::OPCODE::LD1Fourv4s)
.value("LD1Fourv4s_POST", LIEF::assembly::aarch64::OPCODE::LD1Fourv4s_POST)
.value("LD1Fourv8b", LIEF::assembly::aarch64::OPCODE::LD1Fourv8b)
@@ -4505,8 +4567,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LD1RQ_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_H_IMM)
.value("LD1RQ_W", LIEF::assembly::aarch64::OPCODE::LD1RQ_W)
.value("LD1RQ_W_IMM", LIEF::assembly::aarch64::OPCODE::LD1RQ_W_IMM)
.value("LD1RSB_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_D_IMM);
opcodes.value("LD1RSB_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_H_IMM)
.value("LD1RSB_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_D_IMM)
.value("LD1RSB_H_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_H_IMM)
.value("LD1RSB_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSB_S_IMM)
.value("LD1RSH_D_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSH_D_IMM)
.value("LD1RSH_S_IMM", LIEF::assembly::aarch64::OPCODE::LD1RSH_S_IMM)
@@ -4743,8 +4805,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LD4W_IMM", LIEF::assembly::aarch64::OPCODE::LD4W_IMM)
.value("LD4i16", LIEF::assembly::aarch64::OPCODE::LD4i16)
.value("LD4i16_POST", LIEF::assembly::aarch64::OPCODE::LD4i16_POST)
.value("LD4i32", LIEF::assembly::aarch64::OPCODE::LD4i32)
.value("LD4i32_POST", LIEF::assembly::aarch64::OPCODE::LD4i32_POST)
.value("LD4i32", LIEF::assembly::aarch64::OPCODE::LD4i32);
opcodes.value("LD4i32_POST", LIEF::assembly::aarch64::OPCODE::LD4i32_POST)
.value("LD4i64", LIEF::assembly::aarch64::OPCODE::LD4i64)
.value("LD4i64_POST", LIEF::assembly::aarch64::OPCODE::LD4i64_POST)
.value("LD4i8", LIEF::assembly::aarch64::OPCODE::LD4i8)
@@ -4805,8 +4867,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LDBFADDA", LIEF::assembly::aarch64::OPCODE::LDBFADDA)
.value("LDBFADDAL", LIEF::assembly::aarch64::OPCODE::LDBFADDAL)
.value("LDBFADDL", LIEF::assembly::aarch64::OPCODE::LDBFADDL)
.value("LDBFMAX", LIEF::assembly::aarch64::OPCODE::LDBFMAX);
opcodes.value("LDBFMAXA", LIEF::assembly::aarch64::OPCODE::LDBFMAXA)
.value("LDBFMAX", LIEF::assembly::aarch64::OPCODE::LDBFMAX)
.value("LDBFMAXA", LIEF::assembly::aarch64::OPCODE::LDBFMAXA)
.value("LDBFMAXAL", LIEF::assembly::aarch64::OPCODE::LDBFMAXAL)
.value("LDBFMAXL", LIEF::assembly::aarch64::OPCODE::LDBFMAXL)
.value("LDBFMAXNM", LIEF::assembly::aarch64::OPCODE::LDBFMAXNM)
@@ -5043,8 +5105,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LDRBBroW", LIEF::assembly::aarch64::OPCODE::LDRBBroW)
.value("LDRBBroX", LIEF::assembly::aarch64::OPCODE::LDRBBroX)
.value("LDRBBui", LIEF::assembly::aarch64::OPCODE::LDRBBui)
.value("LDRBpost", LIEF::assembly::aarch64::OPCODE::LDRBpost)
.value("LDRBpre", LIEF::assembly::aarch64::OPCODE::LDRBpre)
.value("LDRBpost", LIEF::assembly::aarch64::OPCODE::LDRBpost);
opcodes.value("LDRBpre", LIEF::assembly::aarch64::OPCODE::LDRBpre)
.value("LDRBroW", LIEF::assembly::aarch64::OPCODE::LDRBroW)
.value("LDRBroX", LIEF::assembly::aarch64::OPCODE::LDRBroX)
.value("LDRBui", LIEF::assembly::aarch64::OPCODE::LDRBui)
@@ -5105,8 +5167,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LDRWl", LIEF::assembly::aarch64::OPCODE::LDRWl)
.value("LDRWpost", LIEF::assembly::aarch64::OPCODE::LDRWpost)
.value("LDRWpre", LIEF::assembly::aarch64::OPCODE::LDRWpre)
.value("LDRWroW", LIEF::assembly::aarch64::OPCODE::LDRWroW);
opcodes.value("LDRWroX", LIEF::assembly::aarch64::OPCODE::LDRWroX)
.value("LDRWroW", LIEF::assembly::aarch64::OPCODE::LDRWroW)
.value("LDRWroX", LIEF::assembly::aarch64::OPCODE::LDRWroX)
.value("LDRWui", LIEF::assembly::aarch64::OPCODE::LDRWui)
.value("LDRXl", LIEF::assembly::aarch64::OPCODE::LDRXl)
.value("LDRXpost", LIEF::assembly::aarch64::OPCODE::LDRXpost)
@@ -5343,8 +5405,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("LUTI4_S_4ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_S_4ZTZI_H)
.value("LUTI4_S_4ZZT2Z", LIEF::assembly::aarch64::OPCODE::LUTI4_S_4ZZT2Z)
.value("LUTI4_Z2ZZI", LIEF::assembly::aarch64::OPCODE::LUTI4_Z2ZZI)
.value("LUTI4_ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_B)
.value("LUTI4_ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_H)
.value("LUTI4_ZTZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_B);
opcodes.value("LUTI4_ZTZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_H)
.value("LUTI4_ZTZI_S", LIEF::assembly::aarch64::OPCODE::LUTI4_ZTZI_S)
.value("LUTI4_ZZZI_B", LIEF::assembly::aarch64::OPCODE::LUTI4_ZZZI_B)
.value("LUTI4_ZZZI_H", LIEF::assembly::aarch64::OPCODE::LUTI4_ZZZI_H)
@@ -5405,8 +5467,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("MOPSSETGET", LIEF::assembly::aarch64::OPCODE::MOPSSETGET)
.value("MOPSSETGETN", LIEF::assembly::aarch64::OPCODE::MOPSSETGETN)
.value("MOVAZ_2ZMI_H_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_B)
.value("MOVAZ_2ZMI_H_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_D);
opcodes.value("MOVAZ_2ZMI_H_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_H)
.value("MOVAZ_2ZMI_H_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_D)
.value("MOVAZ_2ZMI_H_H", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_H)
.value("MOVAZ_2ZMI_H_S", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_H_S)
.value("MOVAZ_2ZMI_V_B", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_B)
.value("MOVAZ_2ZMI_V_D", LIEF::assembly::aarch64::OPCODE::MOVAZ_2ZMI_V_D)
@@ -5643,8 +5705,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("PMOV_PZI_B", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_B)
.value("PMOV_PZI_D", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_D)
.value("PMOV_PZI_H", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_H)
.value("PMOV_PZI_S", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_S)
.value("PMOV_ZIP_B", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_B)
.value("PMOV_PZI_S", LIEF::assembly::aarch64::OPCODE::PMOV_PZI_S);
opcodes.value("PMOV_ZIP_B", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_B)
.value("PMOV_ZIP_D", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_D)
.value("PMOV_ZIP_H", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_H)
.value("PMOV_ZIP_S", LIEF::assembly::aarch64::OPCODE::PMOV_ZIP_S)
@@ -5705,8 +5767,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("PRFW_PRI", LIEF::assembly::aarch64::OPCODE::PRFW_PRI)
.value("PRFW_PRR", LIEF::assembly::aarch64::OPCODE::PRFW_PRR)
.value("PRFW_S_PZI", LIEF::assembly::aarch64::OPCODE::PRFW_S_PZI)
.value("PRFW_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_SXTW_SCALED);
opcodes.value("PRFW_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_UXTW_SCALED)
.value("PRFW_S_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_SXTW_SCALED)
.value("PRFW_S_UXTW_SCALED", LIEF::assembly::aarch64::OPCODE::PRFW_S_UXTW_SCALED)
.value("PSEL_PPPRI_B", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_B)
.value("PSEL_PPPRI_D", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_D)
.value("PSEL_PPPRI_H", LIEF::assembly::aarch64::OPCODE::PSEL_PPPRI_H)
@@ -5943,8 +6005,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SABDv8i16", LIEF::assembly::aarch64::OPCODE::SABDv8i16)
.value("SABDv8i8", LIEF::assembly::aarch64::OPCODE::SABDv8i8)
.value("SADALP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_D)
.value("SADALP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_H)
.value("SADALP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_S)
.value("SADALP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_H);
opcodes.value("SADALP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SADALP_ZPmZ_S)
.value("SADALPv16i8_v8i16", LIEF::assembly::aarch64::OPCODE::SADALPv16i8_v8i16)
.value("SADALPv2i32_v1i64", LIEF::assembly::aarch64::OPCODE::SADALPv2i32_v1i64)
.value("SADALPv4i16_v2i32", LIEF::assembly::aarch64::OPCODE::SADALPv4i16_v2i32)
@@ -6005,8 +6067,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SBFMXri", LIEF::assembly::aarch64::OPCODE::SBFMXri)
.value("SCLAMP_VG2_2Z2Z_B", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_B)
.value("SCLAMP_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_D)
.value("SCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_H);
opcodes.value("SCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_S)
.value("SCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_H)
.value("SCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG2_2Z2Z_S)
.value("SCLAMP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_B)
.value("SCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_D)
.value("SCLAMP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::SCLAMP_VG4_4Z4Z_H)
@@ -6217,7 +6279,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SHSUBv4i32", LIEF::assembly::aarch64::OPCODE::SHSUBv4i32)
.value("SHSUBv8i16", LIEF::assembly::aarch64::OPCODE::SHSUBv8i16)
.value("SHSUBv8i8", LIEF::assembly::aarch64::OPCODE::SHSUBv8i8)
.value("SHUH", LIEF::assembly::aarch64::OPCODE::SHUH)
.value("SLI_ZZI_B", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_B)
.value("SLI_ZZI_D", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_D)
.value("SLI_ZZI_H", LIEF::assembly::aarch64::OPCODE::SLI_ZZI_H)
@@ -6244,8 +6305,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SMADDLrrr", LIEF::assembly::aarch64::OPCODE::SMADDLrrr)
.value("SMAXP_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_B)
.value("SMAXP_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_D)
.value("SMAXP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_H)
.value("SMAXP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_S)
.value("SMAXP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_H);
opcodes.value("SMAXP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMAXP_ZPmZ_S)
.value("SMAXPv16i8", LIEF::assembly::aarch64::OPCODE::SMAXPv16i8)
.value("SMAXPv2i32", LIEF::assembly::aarch64::OPCODE::SMAXPv2i32)
.value("SMAXPv4i16", LIEF::assembly::aarch64::OPCODE::SMAXPv4i16)
@@ -6305,8 +6366,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SMINP_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_H)
.value("SMINP_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SMINP_ZPmZ_S)
.value("SMINPv16i8", LIEF::assembly::aarch64::OPCODE::SMINPv16i8)
.value("SMINPv2i32", LIEF::assembly::aarch64::OPCODE::SMINPv2i32);
opcodes.value("SMINPv4i16", LIEF::assembly::aarch64::OPCODE::SMINPv4i16)
.value("SMINPv2i32", LIEF::assembly::aarch64::OPCODE::SMINPv2i32)
.value("SMINPv4i16", LIEF::assembly::aarch64::OPCODE::SMINPv4i16)
.value("SMINPv4i32", LIEF::assembly::aarch64::OPCODE::SMINPv4i32)
.value("SMINPv8i16", LIEF::assembly::aarch64::OPCODE::SMINPv8i16)
.value("SMINPv8i8", LIEF::assembly::aarch64::OPCODE::SMINPv8i8)
@@ -6544,8 +6605,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQABSv4i32", LIEF::assembly::aarch64::OPCODE::SQABSv4i32)
.value("SQABSv8i16", LIEF::assembly::aarch64::OPCODE::SQABSv8i16)
.value("SQABSv8i8", LIEF::assembly::aarch64::OPCODE::SQABSv8i8)
.value("SQADD_ZI_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_B)
.value("SQADD_ZI_D", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_D)
.value("SQADD_ZI_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_B);
opcodes.value("SQADD_ZI_D", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_D)
.value("SQADD_ZI_H", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_H)
.value("SQADD_ZI_S", LIEF::assembly::aarch64::OPCODE::SQADD_ZI_S)
.value("SQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQADD_ZPmZ_B)
@@ -6605,8 +6666,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQDECW_XPiI", LIEF::assembly::aarch64::OPCODE::SQDECW_XPiI)
.value("SQDECW_XPiWdI", LIEF::assembly::aarch64::OPCODE::SQDECW_XPiWdI)
.value("SQDECW_ZPiI", LIEF::assembly::aarch64::OPCODE::SQDECW_ZPiI)
.value("SQDMLALBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_D);
opcodes.value("SQDMLALBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_H)
.value("SQDMLALBT_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_D)
.value("SQDMLALBT_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_H)
.value("SQDMLALBT_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SQDMLALBT_ZZZ_S)
.value("SQDMLALB_ZZZI_D", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZI_D)
.value("SQDMLALB_ZZZI_S", LIEF::assembly::aarch64::OPCODE::SQDMLALB_ZZZI_S)
@@ -6844,8 +6905,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQRSHRN_VG4_Z4ZI_B", LIEF::assembly::aarch64::OPCODE::SQRSHRN_VG4_Z4ZI_B)
.value("SQRSHRN_VG4_Z4ZI_H", LIEF::assembly::aarch64::OPCODE::SQRSHRN_VG4_Z4ZI_H)
.value("SQRSHRN_Z2ZI_HtoB", LIEF::assembly::aarch64::OPCODE::SQRSHRN_Z2ZI_HtoB)
.value("SQRSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQRSHRN_Z2ZI_StoH)
.value("SQRSHRNb", LIEF::assembly::aarch64::OPCODE::SQRSHRNb)
.value("SQRSHRN_Z2ZI_StoH", LIEF::assembly::aarch64::OPCODE::SQRSHRN_Z2ZI_StoH);
opcodes.value("SQRSHRNb", LIEF::assembly::aarch64::OPCODE::SQRSHRNb)
.value("SQRSHRNh", LIEF::assembly::aarch64::OPCODE::SQRSHRNh)
.value("SQRSHRNs", LIEF::assembly::aarch64::OPCODE::SQRSHRNs)
.value("SQRSHRNv16i8_shift", LIEF::assembly::aarch64::OPCODE::SQRSHRNv16i8_shift)
@@ -6905,8 +6966,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SQSHL_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_B)
.value("SQSHL_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_D)
.value("SQSHL_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_H)
.value("SQSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_S);
opcodes.value("SQSHLb", LIEF::assembly::aarch64::OPCODE::SQSHLb)
.value("SQSHL_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SQSHL_ZPmZ_S)
.value("SQSHLb", LIEF::assembly::aarch64::OPCODE::SQSHLb)
.value("SQSHLd", LIEF::assembly::aarch64::OPCODE::SQSHLd)
.value("SQSHLh", LIEF::assembly::aarch64::OPCODE::SQSHLh)
.value("SQSHLs", LIEF::assembly::aarch64::OPCODE::SQSHLs)
@@ -7144,8 +7205,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SST1B_S_IMM", LIEF::assembly::aarch64::OPCODE::SST1B_S_IMM)
.value("SST1B_S_SXTW", LIEF::assembly::aarch64::OPCODE::SST1B_S_SXTW)
.value("SST1B_S_UXTW", LIEF::assembly::aarch64::OPCODE::SST1B_S_UXTW)
.value("SST1D", LIEF::assembly::aarch64::OPCODE::SST1D)
.value("SST1D_IMM", LIEF::assembly::aarch64::OPCODE::SST1D_IMM)
.value("SST1D", LIEF::assembly::aarch64::OPCODE::SST1D);
opcodes.value("SST1D_IMM", LIEF::assembly::aarch64::OPCODE::SST1D_IMM)
.value("SST1D_SCALED", LIEF::assembly::aarch64::OPCODE::SST1D_SCALED)
.value("SST1D_SXTW", LIEF::assembly::aarch64::OPCODE::SST1D_SXTW)
.value("SST1D_SXTW_SCALED", LIEF::assembly::aarch64::OPCODE::SST1D_SXTW_SCALED)
@@ -7205,8 +7266,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SSUBWv4i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBWv4i16_v4i32)
.value("SSUBWv4i32_v2i64", LIEF::assembly::aarch64::OPCODE::SSUBWv4i32_v2i64)
.value("SSUBWv8i16_v4i32", LIEF::assembly::aarch64::OPCODE::SSUBWv8i16_v4i32)
.value("SSUBWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBWv8i8_v8i16);
opcodes.value("ST1B", LIEF::assembly::aarch64::OPCODE::ST1B)
.value("SSUBWv8i8_v8i16", LIEF::assembly::aarch64::OPCODE::SSUBWv8i8_v8i16)
.value("ST1B", LIEF::assembly::aarch64::OPCODE::ST1B)
.value("ST1B_2Z", LIEF::assembly::aarch64::OPCODE::ST1B_2Z)
.value("ST1B_2Z_IMM", LIEF::assembly::aarch64::OPCODE::ST1B_2Z_IMM)
.value("ST1B_2Z_STRIDED", LIEF::assembly::aarch64::OPCODE::ST1B_2Z_STRIDED)
@@ -7444,8 +7505,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("ST4i8", LIEF::assembly::aarch64::OPCODE::ST4i8)
.value("ST4i8_POST", LIEF::assembly::aarch64::OPCODE::ST4i8_POST)
.value("ST64B", LIEF::assembly::aarch64::OPCODE::ST64B)
.value("ST64BV", LIEF::assembly::aarch64::OPCODE::ST64BV)
.value("ST64BV0", LIEF::assembly::aarch64::OPCODE::ST64BV0)
.value("ST64BV", LIEF::assembly::aarch64::OPCODE::ST64BV);
opcodes.value("ST64BV0", LIEF::assembly::aarch64::OPCODE::ST64BV0)
.value("STBFADD", LIEF::assembly::aarch64::OPCODE::STBFADD)
.value("STBFADDL", LIEF::assembly::aarch64::OPCODE::STBFADDL)
.value("STBFMAX", LIEF::assembly::aarch64::OPCODE::STBFMAX)
@@ -7456,7 +7517,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("STBFMINL", LIEF::assembly::aarch64::OPCODE::STBFMINL)
.value("STBFMINNM", LIEF::assembly::aarch64::OPCODE::STBFMINNM)
.value("STBFMINNML", LIEF::assembly::aarch64::OPCODE::STBFMINNML)
.value("STCPH", LIEF::assembly::aarch64::OPCODE::STCPH)
.value("STFADDD", LIEF::assembly::aarch64::OPCODE::STFADDD)
.value("STFADDH", LIEF::assembly::aarch64::OPCODE::STFADDH)
.value("STFADDLD", LIEF::assembly::aarch64::OPCODE::STFADDLD)
@@ -7505,8 +7565,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("STLLRX", LIEF::assembly::aarch64::OPCODE::STLLRX)
.value("STLPi", LIEF::assembly::aarch64::OPCODE::STLPi)
.value("STLRB", LIEF::assembly::aarch64::OPCODE::STLRB)
.value("STLRH", LIEF::assembly::aarch64::OPCODE::STLRH);
opcodes.value("STLRW", LIEF::assembly::aarch64::OPCODE::STLRW)
.value("STLRH", LIEF::assembly::aarch64::OPCODE::STLRH)
.value("STLRW", LIEF::assembly::aarch64::OPCODE::STLRW)
.value("STLRWpre", LIEF::assembly::aarch64::OPCODE::STLRWpre)
.value("STLRX", LIEF::assembly::aarch64::OPCODE::STLRX)
.value("STLRXpre", LIEF::assembly::aarch64::OPCODE::STLRXpre)
@@ -7645,7 +7705,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("STR_TX", LIEF::assembly::aarch64::OPCODE::STR_TX)
.value("STR_ZA", LIEF::assembly::aarch64::OPCODE::STR_ZA)
.value("STR_ZXI", LIEF::assembly::aarch64::OPCODE::STR_ZXI)
.value("STSHH", LIEF::assembly::aarch64::OPCODE::STSHH)
.value("STTNPQi", LIEF::assembly::aarch64::OPCODE::STTNPQi)
.value("STTNPXi", LIEF::assembly::aarch64::OPCODE::STTNPXi)
.value("STTPQi", LIEF::assembly::aarch64::OPCODE::STTPQi)
@@ -7746,8 +7805,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SUB_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_H)
.value("SUB_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUB_ZPmZ_S)
.value("SUB_ZZZ_B", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_B)
.value("SUB_ZZZ_CPA", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_CPA)
.value("SUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_D)
.value("SUB_ZZZ_CPA", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_CPA);
opcodes.value("SUB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_D)
.value("SUB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_H)
.value("SUB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::SUB_ZZZ_S)
.value("SUBv16i8", LIEF::assembly::aarch64::OPCODE::SUBv16i8)
@@ -7805,8 +7864,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("SUQADD_ZPmZ_B", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_B)
.value("SUQADD_ZPmZ_D", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_D)
.value("SUQADD_ZPmZ_H", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_H)
.value("SUQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_S);
opcodes.value("SUQADDv16i8", LIEF::assembly::aarch64::OPCODE::SUQADDv16i8)
.value("SUQADD_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::SUQADD_ZPmZ_S)
.value("SUQADDv16i8", LIEF::assembly::aarch64::OPCODE::SUQADDv16i8)
.value("SUQADDv1i16", LIEF::assembly::aarch64::OPCODE::SUQADDv1i16)
.value("SUQADDv1i32", LIEF::assembly::aarch64::OPCODE::SUQADDv1i32)
.value("SUQADDv1i64", LIEF::assembly::aarch64::OPCODE::SUQADDv1i64)
@@ -7913,7 +7972,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("TCHANGEFrr", LIEF::assembly::aarch64::OPCODE::TCHANGEFrr)
.value("TENTER", LIEF::assembly::aarch64::OPCODE::TENTER)
.value("TEXIT", LIEF::assembly::aarch64::OPCODE::TEXIT)
.value("TRCIT", LIEF::assembly::aarch64::OPCODE::TRCIT)
.value("TRN1_PPP_B", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_B)
.value("TRN1_PPP_D", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_D)
.value("TRN1_PPP_H", LIEF::assembly::aarch64::OPCODE::TRN1_PPP_H)
@@ -7946,7 +8004,6 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("TRN2v4i32", LIEF::assembly::aarch64::OPCODE::TRN2v4i32)
.value("TRN2v8i16", LIEF::assembly::aarch64::OPCODE::TRN2v8i16)
.value("TRN2v8i8", LIEF::assembly::aarch64::OPCODE::TRN2v8i8)
.value("TSB", LIEF::assembly::aarch64::OPCODE::TSB)
.value("UABALB_ZZZ_D", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_D)
.value("UABALB_ZZZ_H", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_H)
.value("UABALB_ZZZ_S", LIEF::assembly::aarch64::OPCODE::UABALB_ZZZ_S)
@@ -8048,8 +8105,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UCLAMP_VG2_2Z2Z_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_D)
.value("UCLAMP_VG2_2Z2Z_H", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_H)
.value("UCLAMP_VG2_2Z2Z_S", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG2_2Z2Z_S)
.value("UCLAMP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_B)
.value("UCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_D)
.value("UCLAMP_VG4_4Z4Z_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_B);
opcodes.value("UCLAMP_VG4_4Z4Z_D", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_D)
.value("UCLAMP_VG4_4Z4Z_H", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_H)
.value("UCLAMP_VG4_4Z4Z_S", LIEF::assembly::aarch64::OPCODE::UCLAMP_VG4_4Z4Z_S)
.value("UCLAMP_ZZZ_B", LIEF::assembly::aarch64::OPCODE::UCLAMP_ZZZ_B)
@@ -8105,8 +8162,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UCVTFv2i32_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv2i32_shift)
.value("UCVTFv2i64_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv2i64_shift)
.value("UCVTFv4f16", LIEF::assembly::aarch64::OPCODE::UCVTFv4f16)
.value("UCVTFv4f32", LIEF::assembly::aarch64::OPCODE::UCVTFv4f32);
opcodes.value("UCVTFv4i16_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv4i16_shift)
.value("UCVTFv4f32", LIEF::assembly::aarch64::OPCODE::UCVTFv4f32)
.value("UCVTFv4i16_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv4i16_shift)
.value("UCVTFv4i32_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv4i32_shift)
.value("UCVTFv8f16", LIEF::assembly::aarch64::OPCODE::UCVTFv8f16)
.value("UCVTFv8i16_shift", LIEF::assembly::aarch64::OPCODE::UCVTFv8i16_shift)
@@ -8348,8 +8405,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UMLSLL_VG4_M4Z4Z_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_BtoS)
.value("UMLSLL_VG4_M4Z4Z_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4Z4Z_HtoD)
.value("UMLSLL_VG4_M4ZZI_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_BtoS)
.value("UMLSLL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_HtoD)
.value("UMLSLL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_BtoS)
.value("UMLSLL_VG4_M4ZZI_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZI_HtoD);
opcodes.value("UMLSLL_VG4_M4ZZ_BtoS", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_BtoS)
.value("UMLSLL_VG4_M4ZZ_HtoD", LIEF::assembly::aarch64::OPCODE::UMLSLL_VG4_M4ZZ_HtoD)
.value("UMLSLT_ZZZI_D", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZI_D)
.value("UMLSLT_ZZZI_S", LIEF::assembly::aarch64::OPCODE::UMLSLT_ZZZI_S)
@@ -8405,8 +8462,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UMOPA_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::UMOPA_MPPZZ_S)
.value("UMOPS_MPPZZ_D", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_D)
.value("UMOPS_MPPZZ_HtoS", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_HtoS)
.value("UMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_S);
opcodes.value("UMOVvi16", LIEF::assembly::aarch64::OPCODE::UMOVvi16)
.value("UMOPS_MPPZZ_S", LIEF::assembly::aarch64::OPCODE::UMOPS_MPPZZ_S)
.value("UMOVvi16", LIEF::assembly::aarch64::OPCODE::UMOVvi16)
.value("UMOVvi16_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi16_idx0)
.value("UMOVvi32", LIEF::assembly::aarch64::OPCODE::UMOVvi32)
.value("UMOVvi32_idx0", LIEF::assembly::aarch64::OPCODE::UMOVvi32_idx0)
@@ -8648,8 +8705,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("UQXTNv1i8", LIEF::assembly::aarch64::OPCODE::UQXTNv1i8)
.value("UQXTNv2i32", LIEF::assembly::aarch64::OPCODE::UQXTNv2i32)
.value("UQXTNv4i16", LIEF::assembly::aarch64::OPCODE::UQXTNv4i16)
.value("UQXTNv4i32", LIEF::assembly::aarch64::OPCODE::UQXTNv4i32)
.value("UQXTNv8i16", LIEF::assembly::aarch64::OPCODE::UQXTNv8i16)
.value("UQXTNv4i32", LIEF::assembly::aarch64::OPCODE::UQXTNv4i32);
opcodes.value("UQXTNv8i16", LIEF::assembly::aarch64::OPCODE::UQXTNv8i16)
.value("UQXTNv8i8", LIEF::assembly::aarch64::OPCODE::UQXTNv8i8)
.value("URECPE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URECPE_ZPmZ_S)
.value("URECPE_ZPzZ_S", LIEF::assembly::aarch64::OPCODE::URECPE_ZPzZ_S)
@@ -8705,8 +8762,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("URSHRv16i8_shift", LIEF::assembly::aarch64::OPCODE::URSHRv16i8_shift)
.value("URSHRv2i32_shift", LIEF::assembly::aarch64::OPCODE::URSHRv2i32_shift)
.value("URSHRv2i64_shift", LIEF::assembly::aarch64::OPCODE::URSHRv2i64_shift)
.value("URSHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i16_shift);
opcodes.value("URSHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i32_shift)
.value("URSHRv4i16_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i16_shift)
.value("URSHRv4i32_shift", LIEF::assembly::aarch64::OPCODE::URSHRv4i32_shift)
.value("URSHRv8i16_shift", LIEF::assembly::aarch64::OPCODE::URSHRv8i16_shift)
.value("URSHRv8i8_shift", LIEF::assembly::aarch64::OPCODE::URSHRv8i8_shift)
.value("URSQRTE_ZPmZ_S", LIEF::assembly::aarch64::OPCODE::URSQRTE_ZPmZ_S)
@@ -8948,8 +9005,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("WHILEGT_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_B)
.value("WHILEGT_2PXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_D)
.value("WHILEGT_2PXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_H)
.value("WHILEGT_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_S)
.value("WHILEGT_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_B)
.value("WHILEGT_2PXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_2PXX_S);
opcodes.value("WHILEGT_CXX_B", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_B)
.value("WHILEGT_CXX_D", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_D)
.value("WHILEGT_CXX_H", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_H)
.value("WHILEGT_CXX_S", LIEF::assembly::aarch64::OPCODE::WHILEGT_CXX_S)
@@ -9005,8 +9062,8 @@ void create<LIEF::assembly::aarch64::OPCODE>(nb::module_& m) {
.value("WHILELE_PWW_D", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_D)
.value("WHILELE_PWW_H", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_H)
.value("WHILELE_PWW_S", LIEF::assembly::aarch64::OPCODE::WHILELE_PWW_S)
.value("WHILELE_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_B);
opcodes.value("WHILELE_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_D)
.value("WHILELE_PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_B)
.value("WHILELE_PXX_D", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_D)
.value("WHILELE_PXX_H", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_H)
.value("WHILELE_PXX_S", LIEF::assembly::aarch64::OPCODE::WHILELE_PXX_S)
.value("WHILELO_2PXX_B", LIEF::assembly::aarch64::OPCODE::WHILELO_2PXX_B)
api/python/src/asm/aarch64/pyRegister.cpp
+23 -31
View File
@@ -1513,10 +1513,8 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("APDAKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APDAKeyHi_EL1)
.value("APDBKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APDBKeyLo_EL1)
.value("APDBKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APDBKeyHi_EL1)
.value("TPMIN0_EL1", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL1)
.value("TPMAX0_EL1", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL1)
.value("TPMIN1_EL1", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL1)
.value("TPMAX1_EL1", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL1)
.value("TPCR0_EL1", LIEF::assembly::aarch64::SYSREG::TPCR0_EL1)
.value("TPCR1_EL1", LIEF::assembly::aarch64::SYSREG::TPCR1_EL1)
.value("APGAKeyLo_EL1", LIEF::assembly::aarch64::SYSREG::APGAKeyLo_EL1)
.value("APGAKeyHi_EL1", LIEF::assembly::aarch64::SYSREG::APGAKeyHi_EL1)
.value("GCSCR_EL1", LIEF::assembly::aarch64::SYSREG::GCSCR_EL1)
@@ -1796,10 +1794,8 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("CSSELR_EL1", LIEF::assembly::aarch64::SYSREG::CSSELR_EL1)
.value("CTR_EL0", LIEF::assembly::aarch64::SYSREG::CTR_EL0)
.value("DCZID_EL0", LIEF::assembly::aarch64::SYSREG::DCZID_EL0)
.value("TPMIN0_EL0", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL0)
.value("TPMAX0_EL0", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL0)
.value("TPMIN1_EL0", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL0)
.value("TPMAX1_EL0", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL0)
.value("TPCR0_EL0", LIEF::assembly::aarch64::SYSREG::TPCR0_EL0)
.value("TPCR1_EL0", LIEF::assembly::aarch64::SYSREG::TPCR1_EL0)
.value("RNDR", LIEF::assembly::aarch64::SYSREG::RNDR)
.value("RNDRRS", LIEF::assembly::aarch64::SYSREG::RNDRRS)
.value("GCSPR_EL0", LIEF::assembly::aarch64::SYSREG::GCSPR_EL0)
@@ -1807,12 +1803,12 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("NZCV", LIEF::assembly::aarch64::SYSREG::NZCV)
.value("DAIF", LIEF::assembly::aarch64::SYSREG::DAIF)
.value("SVCR", LIEF::assembly::aarch64::SYSREG::SVCR)
.value("DIT", LIEF::assembly::aarch64::SYSREG::DIT);
reg.value("SSBS", LIEF::assembly::aarch64::SYSREG::SSBS)
.value("DIT", LIEF::assembly::aarch64::SYSREG::DIT)
.value("SSBS", LIEF::assembly::aarch64::SYSREG::SSBS)
.value("TCO", LIEF::assembly::aarch64::SYSREG::TCO)
.value("FPCR", LIEF::assembly::aarch64::SYSREG::FPCR)
.value("FPSR", LIEF::assembly::aarch64::SYSREG::FPSR)
.value("FPMR", LIEF::assembly::aarch64::SYSREG::FPMR)
.value("FPSR", LIEF::assembly::aarch64::SYSREG::FPSR);
reg.value("FPMR", LIEF::assembly::aarch64::SYSREG::FPMR)
.value("DSPSR_EL0", LIEF::assembly::aarch64::SYSREG::DSPSR_EL0)
.value("DLR_EL0", LIEF::assembly::aarch64::SYSREG::DLR_EL0)
.value("DPOCR_EL0", LIEF::assembly::aarch64::SYSREG::DPOCR_EL0)
@@ -2005,10 +2001,8 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("LDSTT_EL2", LIEF::assembly::aarch64::SYSREG::LDSTT_EL2)
.value("VNCR_EL2", LIEF::assembly::aarch64::SYSREG::VNCR_EL2)
.value("VNCCR_EL2", LIEF::assembly::aarch64::SYSREG::VNCCR_EL2)
.value("TPMIN0_EL2", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL2)
.value("TPMAX0_EL2", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL2)
.value("TPMIN1_EL2", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL2)
.value("TPMAX1_EL2", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL2)
.value("TPCR0_EL2", LIEF::assembly::aarch64::SYSREG::TPCR0_EL2)
.value("TPCR1_EL2", LIEF::assembly::aarch64::SYSREG::TPCR1_EL2)
.value("HDBSSBR_EL2", LIEF::assembly::aarch64::SYSREG::HDBSSBR_EL2)
.value("HDBSSPROD_EL2", LIEF::assembly::aarch64::SYSREG::HDBSSPROD_EL2)
.value("HACDBSBR_EL2", LIEF::assembly::aarch64::SYSREG::HACDBSBR_EL2)
@@ -2107,14 +2101,14 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("SP_EL1", LIEF::assembly::aarch64::SYSREG::SP_EL1)
.value("SPSR_irq", LIEF::assembly::aarch64::SYSREG::SPSR_irq)
.value("SPSR_abt", LIEF::assembly::aarch64::SYSREG::SPSR_abt)
.value("SPSR_und", LIEF::assembly::aarch64::SYSREG::SPSR_und);
reg.value("SPSR_fiq", LIEF::assembly::aarch64::SYSREG::SPSR_fiq)
.value("SPSR_und", LIEF::assembly::aarch64::SYSREG::SPSR_und)
.value("SPSR_fiq", LIEF::assembly::aarch64::SYSREG::SPSR_fiq)
.value("IFSR32_EL2", LIEF::assembly::aarch64::SYSREG::IFSR32_EL2)
.value("AFSR0_EL2", LIEF::assembly::aarch64::SYSREG::AFSR0_EL2)
.value("AFSR1_EL2", LIEF::assembly::aarch64::SYSREG::AFSR1_EL2)
.value("ESR_EL2", LIEF::assembly::aarch64::SYSREG::ESR_EL2)
.value("VSESR_EL2", LIEF::assembly::aarch64::SYSREG::VSESR_EL2)
.value("FPEXC32_EL2", LIEF::assembly::aarch64::SYSREG::FPEXC32_EL2)
.value("VSESR_EL2", LIEF::assembly::aarch64::SYSREG::VSESR_EL2);
reg.value("FPEXC32_EL2", LIEF::assembly::aarch64::SYSREG::FPEXC32_EL2)
.value("TFSR_EL2", LIEF::assembly::aarch64::SYSREG::TFSR_EL2)
.value("FAR_EL2", LIEF::assembly::aarch64::SYSREG::FAR_EL2)
.value("HPFAR_EL2", LIEF::assembly::aarch64::SYSREG::HPFAR_EL2)
@@ -2180,8 +2174,6 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("MPAMVPM5_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM5_EL2)
.value("MPAMVPM6_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM6_EL2)
.value("MPAMVPM7_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVPM7_EL2)
.value("MPAMVIDCR_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVIDCR_EL2)
.value("MPAMVIDSR_EL2", LIEF::assembly::aarch64::SYSREG::MPAMVIDSR_EL2)
.value("MECID_P0_EL2", LIEF::assembly::aarch64::SYSREG::MECID_P0_EL2)
.value("MECID_A0_EL2", LIEF::assembly::aarch64::SYSREG::MECID_A0_EL2)
.value("MECID_P1_EL2", LIEF::assembly::aarch64::SYSREG::MECID_P1_EL2)
@@ -2193,6 +2185,8 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("RVBAR_EL2", LIEF::assembly::aarch64::SYSREG::RVBAR_EL2)
.value("RMR_EL2", LIEF::assembly::aarch64::SYSREG::RMR_EL2)
.value("VDISR_EL2", LIEF::assembly::aarch64::SYSREG::VDISR_EL2)
.value("ICH_PPI_HVIR0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_HVIR0_EL2)
.value("ICH_PPI_HVIR1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_PPI_HVIR1_EL2)
.value("ICH_AP0R0_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R0_EL2)
.value("ICH_AP0R1_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R1_EL2)
.value("ICH_AP0R2_EL2", LIEF::assembly::aarch64::SYSREG::ICH_AP0R2_EL2)
@@ -2330,10 +2324,8 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("DPOTBR0_EL12", LIEF::assembly::aarch64::SYSREG::DPOTBR0_EL12)
.value("DPOTBR1_EL12", LIEF::assembly::aarch64::SYSREG::DPOTBR1_EL12)
.value("LDSTT_EL12", LIEF::assembly::aarch64::SYSREG::LDSTT_EL12)
.value("TPMIN0_EL12", LIEF::assembly::aarch64::SYSREG::TPMIN0_EL12)
.value("TPMAX0_EL12", LIEF::assembly::aarch64::SYSREG::TPMAX0_EL12)
.value("TPMIN1_EL12", LIEF::assembly::aarch64::SYSREG::TPMIN1_EL12)
.value("TPMAX1_EL12", LIEF::assembly::aarch64::SYSREG::TPMAX1_EL12)
.value("TPCR0_EL12", LIEF::assembly::aarch64::SYSREG::TPCR0_EL12)
.value("TPCR1_EL12", LIEF::assembly::aarch64::SYSREG::TPCR1_EL12)
.value("GCSCR_EL12", LIEF::assembly::aarch64::SYSREG::GCSCR_EL12)
.value("GCSPR_EL12", LIEF::assembly::aarch64::SYSREG::GCSPR_EL12)
.value("TCRMASK_EL12", LIEF::assembly::aarch64::SYSREG::TCRMASK_EL12)
@@ -2407,16 +2399,16 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("STINDEX_EL12", LIEF::assembly::aarch64::SYSREG::STINDEX_EL12)
.value("TINDEX_EL12", LIEF::assembly::aarch64::SYSREG::TINDEX_EL12)
.value("AFSR0_EL12", LIEF::assembly::aarch64::SYSREG::AFSR0_EL12)
.value("AFSR1_EL12", LIEF::assembly::aarch64::SYSREG::AFSR1_EL12);
reg.value("ESR_EL12", LIEF::assembly::aarch64::SYSREG::ESR_EL12)
.value("AFSR1_EL12", LIEF::assembly::aarch64::SYSREG::AFSR1_EL12)
.value("ESR_EL12", LIEF::assembly::aarch64::SYSREG::ESR_EL12)
.value("TFSR_EL12", LIEF::assembly::aarch64::SYSREG::TFSR_EL12)
.value("FAR_EL12", LIEF::assembly::aarch64::SYSREG::FAR_EL12)
.value("PFAR_EL12", LIEF::assembly::aarch64::SYSREG::PFAR_EL12)
.value("PMSCR_EL12", LIEF::assembly::aarch64::SYSREG::PMSCR_EL12)
.value("PMBSR_EL12", LIEF::assembly::aarch64::SYSREG::PMBSR_EL12)
.value("TRBSR_EL12", LIEF::assembly::aarch64::SYSREG::TRBSR_EL12)
.value("MAIR_EL12", LIEF::assembly::aarch64::SYSREG::MAIR_EL12)
.value("MAIR2_EL12", LIEF::assembly::aarch64::SYSREG::MAIR2_EL12)
.value("MAIR_EL12", LIEF::assembly::aarch64::SYSREG::MAIR_EL12);
reg.value("MAIR2_EL12", LIEF::assembly::aarch64::SYSREG::MAIR2_EL12)
.value("PIRE0_EL12", LIEF::assembly::aarch64::SYSREG::PIRE0_EL12)
.value("PIR_EL12", LIEF::assembly::aarch64::SYSREG::PIR_EL12)
.value("POR_EL12", LIEF::assembly::aarch64::SYSREG::POR_EL12)
@@ -2446,6 +2438,7 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("CPTR_EL3", LIEF::assembly::aarch64::SYSREG::CPTR_EL3)
.value("FGWTE3_EL3", LIEF::assembly::aarch64::SYSREG::FGWTE3_EL3)
.value("ZCR_EL3", LIEF::assembly::aarch64::SYSREG::ZCR_EL3)
.value("SCR2_EL3", LIEF::assembly::aarch64::SYSREG::SCR2_EL3)
.value("SMCR_EL3", LIEF::assembly::aarch64::SYSREG::SMCR_EL3)
.value("MDCR_EL3", LIEF::assembly::aarch64::SYSREG::MDCR_EL3)
.value("TTBR0_EL3", LIEF::assembly::aarch64::SYSREG::TTBR0_EL3)
@@ -2513,7 +2506,6 @@ void create<LIEF::assembly::aarch64::SYSREG>(nb::module_& m) {
.value("MPAM3_EL3", LIEF::assembly::aarch64::SYSREG::MPAM3_EL3)
.value("MPAMCTL_EL3", LIEF::assembly::aarch64::SYSREG::MPAMCTL_EL3)
.value("MPAMBW3_EL3", LIEF::assembly::aarch64::SYSREG::MPAMBW3_EL3)
.value("MPAMVIDSR_EL3", LIEF::assembly::aarch64::SYSREG::MPAMVIDSR_EL3)
.value("MECID_RL_A_EL3", LIEF::assembly::aarch64::SYSREG::MECID_RL_A_EL3)
.value("VBAR_EL3", LIEF::assembly::aarch64::SYSREG::VBAR_EL3)
.value("RVBAR_EL3", LIEF::assembly::aarch64::SYSREG::RVBAR_EL3)
api/python/src/asm/arm/pyOpcode.cpp
+78 -66
View File
@@ -108,10 +108,12 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("G_LOAD", LIEF::assembly::arm::OPCODE::G_LOAD)
.value("G_SEXTLOAD", LIEF::assembly::arm::OPCODE::G_SEXTLOAD)
.value("G_ZEXTLOAD", LIEF::assembly::arm::OPCODE::G_ZEXTLOAD)
.value("G_FPEXTLOAD", LIEF::assembly::arm::OPCODE::G_FPEXTLOAD)
.value("G_INDEXED_LOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_LOAD)
.value("G_INDEXED_SEXTLOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_SEXTLOAD)
.value("G_INDEXED_ZEXTLOAD", LIEF::assembly::arm::OPCODE::G_INDEXED_ZEXTLOAD)
.value("G_STORE", LIEF::assembly::arm::OPCODE::G_STORE)
.value("G_FPTRUNCSTORE", LIEF::assembly::arm::OPCODE::G_FPTRUNCSTORE)
.value("G_INDEXED_STORE", LIEF::assembly::arm::OPCODE::G_INDEXED_STORE)
.value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::arm::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
.value("G_ATOMIC_CMPXCHG", LIEF::assembly::arm::OPCODE::G_ATOMIC_CMPXCHG)
@@ -132,6 +134,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("G_ATOMICRMW_FMIN", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMIN)
.value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMAXIMUM)
.value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMINIMUM)
.value("G_ATOMICRMW_FMAXIMUMNUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMAXIMUMNUM)
.value("G_ATOMICRMW_FMINIMUMNUM", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_FMINIMUMNUM)
.value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UINC_WRAP)
.value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_UDEC_WRAP)
.value("G_ATOMICRMW_USUB_COND", LIEF::assembly::arm::OPCODE::G_ATOMICRMW_USUB_COND)
@@ -263,12 +267,14 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("G_STEP_VECTOR", LIEF::assembly::arm::OPCODE::G_STEP_VECTOR)
.value("G_VECTOR_COMPRESS", LIEF::assembly::arm::OPCODE::G_VECTOR_COMPRESS)
.value("G_CTTZ", LIEF::assembly::arm::OPCODE::G_CTTZ)
.value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::arm::OPCODE::G_CTTZ_ZERO_UNDEF)
.value("G_CTTZ_ZERO_POISON", LIEF::assembly::arm::OPCODE::G_CTTZ_ZERO_POISON)
.value("G_CTLZ", LIEF::assembly::arm::OPCODE::G_CTLZ)
.value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::arm::OPCODE::G_CTLZ_ZERO_UNDEF)
.value("G_CTLZ_ZERO_POISON", LIEF::assembly::arm::OPCODE::G_CTLZ_ZERO_POISON)
.value("G_CTLS", LIEF::assembly::arm::OPCODE::G_CTLS)
.value("G_CTPOP", LIEF::assembly::arm::OPCODE::G_CTPOP)
.value("G_BSWAP", LIEF::assembly::arm::OPCODE::G_BSWAP)
.value("G_BITREVERSE", LIEF::assembly::arm::OPCODE::G_BITREVERSE)
.value("G_CLMUL", LIEF::assembly::arm::OPCODE::G_CLMUL)
.value("G_FCEIL", LIEF::assembly::arm::OPCODE::G_FCEIL)
.value("G_FCOS", LIEF::assembly::arm::OPCODE::G_FCOS)
.value("G_FSIN", LIEF::assembly::arm::OPCODE::G_FSIN)
@@ -299,14 +305,17 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("G_STRICT_FMA", LIEF::assembly::arm::OPCODE::G_STRICT_FMA)
.value("G_STRICT_FSQRT", LIEF::assembly::arm::OPCODE::G_STRICT_FSQRT)
.value("G_STRICT_FLDEXP", LIEF::assembly::arm::OPCODE::G_STRICT_FLDEXP)
.value("G_STRICT_FCMP", LIEF::assembly::arm::OPCODE::G_STRICT_FCMP);
opcodes.value("G_STRICT_FCMPS", LIEF::assembly::arm::OPCODE::G_STRICT_FCMPS)
.value("G_READ_REGISTER", LIEF::assembly::arm::OPCODE::G_READ_REGISTER)
.value("G_WRITE_REGISTER", LIEF::assembly::arm::OPCODE::G_WRITE_REGISTER)
.value("G_MEMCPY", LIEF::assembly::arm::OPCODE::G_MEMCPY)
.value("G_MEMCPY_INLINE", LIEF::assembly::arm::OPCODE::G_MEMCPY_INLINE)
.value("G_MEMMOVE", LIEF::assembly::arm::OPCODE::G_MEMMOVE)
.value("G_MEMSET", LIEF::assembly::arm::OPCODE::G_MEMSET)
.value("G_BZERO", LIEF::assembly::arm::OPCODE::G_BZERO);
opcodes.value("G_TRAP", LIEF::assembly::arm::OPCODE::G_TRAP)
.value("G_BZERO", LIEF::assembly::arm::OPCODE::G_BZERO)
.value("G_MEMSET_INLINE", LIEF::assembly::arm::OPCODE::G_MEMSET_INLINE)
.value("G_TRAP", LIEF::assembly::arm::OPCODE::G_TRAP)
.value("G_DEBUGTRAP", LIEF::assembly::arm::OPCODE::G_DEBUGTRAP)
.value("G_UBSANTRAP", LIEF::assembly::arm::OPCODE::G_UBSANTRAP)
.value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::arm::OPCODE::G_VECREDUCE_SEQ_FADD)
@@ -350,6 +359,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("BR_JTm_rs", LIEF::assembly::arm::OPCODE::BR_JTm_rs)
.value("BR_JTr", LIEF::assembly::arm::OPCODE::BR_JTr)
.value("BX_CALL", LIEF::assembly::arm::OPCODE::BX_CALL)
.value("CATCHRET", LIEF::assembly::arm::OPCODE::CATCHRET)
.value("CLEANUPRET", LIEF::assembly::arm::OPCODE::CLEANUPRET)
.value("CMP_SWAP_16", LIEF::assembly::arm::OPCODE::CMP_SWAP_16)
.value("CMP_SWAP_32", LIEF::assembly::arm::OPCODE::CMP_SWAP_32)
.value("CMP_SWAP_64", LIEF::assembly::arm::OPCODE::CMP_SWAP_64)
@@ -594,8 +605,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VMOVDcc", LIEF::assembly::arm::OPCODE::VMOVDcc)
.value("VMOVHcc", LIEF::assembly::arm::OPCODE::VMOVHcc)
.value("VMOVQ0", LIEF::assembly::arm::OPCODE::VMOVQ0)
.value("VMOVScc", LIEF::assembly::arm::OPCODE::VMOVScc)
.value("VST1LNdAsm_16", LIEF::assembly::arm::OPCODE::VST1LNdAsm_16)
.value("VMOVScc", LIEF::assembly::arm::OPCODE::VMOVScc);
opcodes.value("VST1LNdAsm_16", LIEF::assembly::arm::OPCODE::VST1LNdAsm_16)
.value("VST1LNdAsm_32", LIEF::assembly::arm::OPCODE::VST1LNdAsm_32)
.value("VST1LNdAsm_8", LIEF::assembly::arm::OPCODE::VST1LNdAsm_8)
.value("VST1LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST1LNdWB_fixed_Asm_16)
@@ -605,8 +616,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VST1LNdWB_register_Asm_32", LIEF::assembly::arm::OPCODE::VST1LNdWB_register_Asm_32)
.value("VST1LNdWB_register_Asm_8", LIEF::assembly::arm::OPCODE::VST1LNdWB_register_Asm_8)
.value("VST2LNdAsm_16", LIEF::assembly::arm::OPCODE::VST2LNdAsm_16)
.value("VST2LNdAsm_32", LIEF::assembly::arm::OPCODE::VST2LNdAsm_32);
opcodes.value("VST2LNdAsm_8", LIEF::assembly::arm::OPCODE::VST2LNdAsm_8)
.value("VST2LNdAsm_32", LIEF::assembly::arm::OPCODE::VST2LNdAsm_32)
.value("VST2LNdAsm_8", LIEF::assembly::arm::OPCODE::VST2LNdAsm_8)
.value("VST2LNdWB_fixed_Asm_16", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_16)
.value("VST2LNdWB_fixed_Asm_32", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_32)
.value("VST2LNdWB_fixed_Asm_8", LIEF::assembly::arm::OPCODE::VST2LNdWB_fixed_Asm_8)
@@ -692,6 +703,7 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("t2ADDSrs", LIEF::assembly::arm::OPCODE::t2ADDSrs)
.value("t2BF_LabelPseudo", LIEF::assembly::arm::OPCODE::t2BF_LabelPseudo)
.value("t2BR_JT", LIEF::assembly::arm::OPCODE::t2BR_JT)
.value("t2BXAUT_RET", LIEF::assembly::arm::OPCODE::t2BXAUT_RET)
.value("t2CALL_BTI", LIEF::assembly::arm::OPCODE::t2CALL_BTI)
.value("t2DoLoopStart", LIEF::assembly::arm::OPCODE::t2DoLoopStart)
.value("t2DoLoopStartTP", LIEF::assembly::arm::OPCODE::t2DoLoopStartTP)
@@ -883,9 +895,9 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("CLREX", LIEF::assembly::arm::OPCODE::CLREX)
.value("CLZ", LIEF::assembly::arm::OPCODE::CLZ)
.value("CMNri", LIEF::assembly::arm::OPCODE::CMNri)
.value("CMNzrr", LIEF::assembly::arm::OPCODE::CMNzrr)
.value("CMNzrsi", LIEF::assembly::arm::OPCODE::CMNzrsi)
.value("CMNzrsr", LIEF::assembly::arm::OPCODE::CMNzrsr)
.value("CMNrr", LIEF::assembly::arm::OPCODE::CMNrr)
.value("CMNrsi", LIEF::assembly::arm::OPCODE::CMNrsi)
.value("CMNrsr", LIEF::assembly::arm::OPCODE::CMNrsr)
.value("CMPri", LIEF::assembly::arm::OPCODE::CMPri)
.value("CMPrr", LIEF::assembly::arm::OPCODE::CMPrr)
.value("CMPrsi", LIEF::assembly::arm::OPCODE::CMPrsi)
@@ -893,8 +905,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("CPS1p", LIEF::assembly::arm::OPCODE::CPS1p)
.value("CPS2p", LIEF::assembly::arm::OPCODE::CPS2p)
.value("CPS3p", LIEF::assembly::arm::OPCODE::CPS3p)
.value("CRC32B", LIEF::assembly::arm::OPCODE::CRC32B)
.value("CRC32CB", LIEF::assembly::arm::OPCODE::CRC32CB)
.value("CRC32B", LIEF::assembly::arm::OPCODE::CRC32B);
opcodes.value("CRC32CB", LIEF::assembly::arm::OPCODE::CRC32CB)
.value("CRC32CH", LIEF::assembly::arm::OPCODE::CRC32CH)
.value("CRC32CW", LIEF::assembly::arm::OPCODE::CRC32CW)
.value("CRC32H", LIEF::assembly::arm::OPCODE::CRC32H)
@@ -905,8 +917,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("EORri", LIEF::assembly::arm::OPCODE::EORri)
.value("EORrr", LIEF::assembly::arm::OPCODE::EORrr)
.value("EORrsi", LIEF::assembly::arm::OPCODE::EORrsi)
.value("EORrsr", LIEF::assembly::arm::OPCODE::EORrsr);
opcodes.value("ERET", LIEF::assembly::arm::OPCODE::ERET)
.value("EORrsr", LIEF::assembly::arm::OPCODE::EORrsr)
.value("ERET", LIEF::assembly::arm::OPCODE::ERET)
.value("FCONSTD", LIEF::assembly::arm::OPCODE::FCONSTD)
.value("FCONSTH", LIEF::assembly::arm::OPCODE::FCONSTH)
.value("FCONSTS", LIEF::assembly::arm::OPCODE::FCONSTS)
@@ -1193,8 +1205,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VHADD_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_s8)
.value("MVE_VHADD_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u16)
.value("MVE_VHADD_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u32)
.value("MVE_VHADD_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u8)
.value("MVE_VHADDs16", LIEF::assembly::arm::OPCODE::MVE_VHADDs16)
.value("MVE_VHADD_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VHADD_qr_u8);
opcodes.value("MVE_VHADDs16", LIEF::assembly::arm::OPCODE::MVE_VHADDs16)
.value("MVE_VHADDs32", LIEF::assembly::arm::OPCODE::MVE_VHADDs32)
.value("MVE_VHADDs8", LIEF::assembly::arm::OPCODE::MVE_VHADDs8)
.value("MVE_VHADDu16", LIEF::assembly::arm::OPCODE::MVE_VHADDu16)
@@ -1205,8 +1217,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VHCADDs8", LIEF::assembly::arm::OPCODE::MVE_VHCADDs8)
.value("MVE_VHSUB_qr_s16", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s16)
.value("MVE_VHSUB_qr_s32", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s32)
.value("MVE_VHSUB_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s8);
opcodes.value("MVE_VHSUB_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u16)
.value("MVE_VHSUB_qr_s8", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_s8)
.value("MVE_VHSUB_qr_u16", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u16)
.value("MVE_VHSUB_qr_u32", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u32)
.value("MVE_VHSUB_qr_u8", LIEF::assembly::arm::OPCODE::MVE_VHSUB_qr_u8)
.value("MVE_VHSUBs16", LIEF::assembly::arm::OPCODE::MVE_VHSUBs16)
@@ -1493,8 +1505,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VPTv16u8r", LIEF::assembly::arm::OPCODE::MVE_VPTv16u8r)
.value("MVE_VPTv4f32", LIEF::assembly::arm::OPCODE::MVE_VPTv4f32)
.value("MVE_VPTv4f32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4f32r)
.value("MVE_VPTv4i32", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32)
.value("MVE_VPTv4i32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32r)
.value("MVE_VPTv4i32", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32);
opcodes.value("MVE_VPTv4i32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4i32r)
.value("MVE_VPTv4s32", LIEF::assembly::arm::OPCODE::MVE_VPTv4s32)
.value("MVE_VPTv4s32r", LIEF::assembly::arm::OPCODE::MVE_VPTv4s32r)
.value("MVE_VPTv4u32", LIEF::assembly::arm::OPCODE::MVE_VPTv4u32)
@@ -1505,8 +1517,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VPTv8i16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8i16r)
.value("MVE_VPTv8s16", LIEF::assembly::arm::OPCODE::MVE_VPTv8s16)
.value("MVE_VPTv8s16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8s16r)
.value("MVE_VPTv8u16", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16);
opcodes.value("MVE_VPTv8u16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16r)
.value("MVE_VPTv8u16", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16)
.value("MVE_VPTv8u16r", LIEF::assembly::arm::OPCODE::MVE_VPTv8u16r)
.value("MVE_VQABSs16", LIEF::assembly::arm::OPCODE::MVE_VQABSs16)
.value("MVE_VQABSs32", LIEF::assembly::arm::OPCODE::MVE_VQABSs32)
.value("MVE_VQABSs8", LIEF::assembly::arm::OPCODE::MVE_VQABSs8)
@@ -1793,8 +1805,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VST40_8", LIEF::assembly::arm::OPCODE::MVE_VST40_8)
.value("MVE_VST40_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST40_8_wb)
.value("MVE_VST41_16", LIEF::assembly::arm::OPCODE::MVE_VST41_16)
.value("MVE_VST41_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_16_wb)
.value("MVE_VST41_32", LIEF::assembly::arm::OPCODE::MVE_VST41_32)
.value("MVE_VST41_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_16_wb);
opcodes.value("MVE_VST41_32", LIEF::assembly::arm::OPCODE::MVE_VST41_32)
.value("MVE_VST41_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_32_wb)
.value("MVE_VST41_8", LIEF::assembly::arm::OPCODE::MVE_VST41_8)
.value("MVE_VST41_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST41_8_wb)
@@ -1805,8 +1817,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("MVE_VST42_8", LIEF::assembly::arm::OPCODE::MVE_VST42_8)
.value("MVE_VST42_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST42_8_wb)
.value("MVE_VST43_16", LIEF::assembly::arm::OPCODE::MVE_VST43_16)
.value("MVE_VST43_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_16_wb);
opcodes.value("MVE_VST43_32", LIEF::assembly::arm::OPCODE::MVE_VST43_32)
.value("MVE_VST43_16_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_16_wb)
.value("MVE_VST43_32", LIEF::assembly::arm::OPCODE::MVE_VST43_32)
.value("MVE_VST43_32_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_32_wb)
.value("MVE_VST43_8", LIEF::assembly::arm::OPCODE::MVE_VST43_8)
.value("MVE_VST43_8_wb", LIEF::assembly::arm::OPCODE::MVE_VST43_8_wb)
@@ -2093,8 +2105,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("UQSAX", LIEF::assembly::arm::OPCODE::UQSAX)
.value("UQSUB16", LIEF::assembly::arm::OPCODE::UQSUB16)
.value("UQSUB8", LIEF::assembly::arm::OPCODE::UQSUB8)
.value("USAD8", LIEF::assembly::arm::OPCODE::USAD8)
.value("USADA8", LIEF::assembly::arm::OPCODE::USADA8)
.value("USAD8", LIEF::assembly::arm::OPCODE::USAD8);
opcodes.value("USADA8", LIEF::assembly::arm::OPCODE::USADA8)
.value("USAT", LIEF::assembly::arm::OPCODE::USAT)
.value("USAT16", LIEF::assembly::arm::OPCODE::USAT16)
.value("USAX", LIEF::assembly::arm::OPCODE::USAX)
@@ -2105,8 +2117,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("UXTAH", LIEF::assembly::arm::OPCODE::UXTAH)
.value("UXTB", LIEF::assembly::arm::OPCODE::UXTB)
.value("UXTB16", LIEF::assembly::arm::OPCODE::UXTB16)
.value("UXTH", LIEF::assembly::arm::OPCODE::UXTH);
opcodes.value("VABALsv2i64", LIEF::assembly::arm::OPCODE::VABALsv2i64)
.value("UXTH", LIEF::assembly::arm::OPCODE::UXTH)
.value("VABALsv2i64", LIEF::assembly::arm::OPCODE::VABALsv2i64)
.value("VABALsv4i32", LIEF::assembly::arm::OPCODE::VABALsv4i32)
.value("VABALsv8i16", LIEF::assembly::arm::OPCODE::VABALsv8i16)
.value("VABALuv2i64", LIEF::assembly::arm::OPCODE::VABALuv2i64)
@@ -2393,8 +2405,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VCVTNSS", LIEF::assembly::arm::OPCODE::VCVTNSS)
.value("VCVTNUD", LIEF::assembly::arm::OPCODE::VCVTNUD)
.value("VCVTNUH", LIEF::assembly::arm::OPCODE::VCVTNUH)
.value("VCVTNUS", LIEF::assembly::arm::OPCODE::VCVTNUS)
.value("VCVTPNSDf", LIEF::assembly::arm::OPCODE::VCVTPNSDf)
.value("VCVTNUS", LIEF::assembly::arm::OPCODE::VCVTNUS);
opcodes.value("VCVTPNSDf", LIEF::assembly::arm::OPCODE::VCVTPNSDf)
.value("VCVTPNSDh", LIEF::assembly::arm::OPCODE::VCVTPNSDh)
.value("VCVTPNSQf", LIEF::assembly::arm::OPCODE::VCVTPNSQf)
.value("VCVTPNSQh", LIEF::assembly::arm::OPCODE::VCVTPNSQh)
@@ -2405,8 +2417,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VCVTPSD", LIEF::assembly::arm::OPCODE::VCVTPSD)
.value("VCVTPSH", LIEF::assembly::arm::OPCODE::VCVTPSH)
.value("VCVTPSS", LIEF::assembly::arm::OPCODE::VCVTPSS)
.value("VCVTPUD", LIEF::assembly::arm::OPCODE::VCVTPUD);
opcodes.value("VCVTPUH", LIEF::assembly::arm::OPCODE::VCVTPUH)
.value("VCVTPUD", LIEF::assembly::arm::OPCODE::VCVTPUD)
.value("VCVTPUH", LIEF::assembly::arm::OPCODE::VCVTPUH)
.value("VCVTPUS", LIEF::assembly::arm::OPCODE::VCVTPUS)
.value("VCVTSD", LIEF::assembly::arm::OPCODE::VCVTSD)
.value("VCVTTDH", LIEF::assembly::arm::OPCODE::VCVTTDH)
@@ -2693,8 +2705,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VLD2DUPq8OddPseudoWB_fixed", LIEF::assembly::arm::OPCODE::VLD2DUPq8OddPseudoWB_fixed)
.value("VLD2DUPq8OddPseudoWB_register", LIEF::assembly::arm::OPCODE::VLD2DUPq8OddPseudoWB_register)
.value("VLD2LNd16", LIEF::assembly::arm::OPCODE::VLD2LNd16)
.value("VLD2LNd16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo)
.value("VLD2LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo_UPD)
.value("VLD2LNd16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo);
opcodes.value("VLD2LNd16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd16Pseudo_UPD)
.value("VLD2LNd16_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd16_UPD)
.value("VLD2LNd32", LIEF::assembly::arm::OPCODE::VLD2LNd32)
.value("VLD2LNd32Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNd32Pseudo)
@@ -2705,8 +2717,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VLD2LNd8Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd8Pseudo_UPD)
.value("VLD2LNd8_UPD", LIEF::assembly::arm::OPCODE::VLD2LNd8_UPD)
.value("VLD2LNq16", LIEF::assembly::arm::OPCODE::VLD2LNq16)
.value("VLD2LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo);
opcodes.value("VLD2LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo_UPD)
.value("VLD2LNq16Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo)
.value("VLD2LNq16Pseudo_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq16Pseudo_UPD)
.value("VLD2LNq16_UPD", LIEF::assembly::arm::OPCODE::VLD2LNq16_UPD)
.value("VLD2LNq32", LIEF::assembly::arm::OPCODE::VLD2LNq32)
.value("VLD2LNq32Pseudo", LIEF::assembly::arm::OPCODE::VLD2LNq32Pseudo)
@@ -2993,8 +3005,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VMLAv8i8", LIEF::assembly::arm::OPCODE::VMLAv8i8)
.value("VMLSD", LIEF::assembly::arm::OPCODE::VMLSD)
.value("VMLSH", LIEF::assembly::arm::OPCODE::VMLSH)
.value("VMLSLslsv2i32", LIEF::assembly::arm::OPCODE::VMLSLslsv2i32)
.value("VMLSLslsv4i16", LIEF::assembly::arm::OPCODE::VMLSLslsv4i16)
.value("VMLSLslsv2i32", LIEF::assembly::arm::OPCODE::VMLSLslsv2i32);
opcodes.value("VMLSLslsv4i16", LIEF::assembly::arm::OPCODE::VMLSLslsv4i16)
.value("VMLSLsluv2i32", LIEF::assembly::arm::OPCODE::VMLSLsluv2i32)
.value("VMLSLsluv4i16", LIEF::assembly::arm::OPCODE::VMLSLsluv4i16)
.value("VMLSLsv2i64", LIEF::assembly::arm::OPCODE::VMLSLsv2i64)
@@ -3005,8 +3017,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VMLSLuv8i16", LIEF::assembly::arm::OPCODE::VMLSLuv8i16)
.value("VMLSS", LIEF::assembly::arm::OPCODE::VMLSS)
.value("VMLSfd", LIEF::assembly::arm::OPCODE::VMLSfd)
.value("VMLSfq", LIEF::assembly::arm::OPCODE::VMLSfq);
opcodes.value("VMLShd", LIEF::assembly::arm::OPCODE::VMLShd)
.value("VMLSfq", LIEF::assembly::arm::OPCODE::VMLSfq)
.value("VMLShd", LIEF::assembly::arm::OPCODE::VMLShd)
.value("VMLShq", LIEF::assembly::arm::OPCODE::VMLShq)
.value("VMLSslfd", LIEF::assembly::arm::OPCODE::VMLSslfd)
.value("VMLSslfq", LIEF::assembly::arm::OPCODE::VMLSslfq)
@@ -3293,8 +3305,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VQRSHRNsv4i16", LIEF::assembly::arm::OPCODE::VQRSHRNsv4i16)
.value("VQRSHRNsv8i8", LIEF::assembly::arm::OPCODE::VQRSHRNsv8i8)
.value("VQRSHRNuv2i32", LIEF::assembly::arm::OPCODE::VQRSHRNuv2i32)
.value("VQRSHRNuv4i16", LIEF::assembly::arm::OPCODE::VQRSHRNuv4i16)
.value("VQRSHRNuv8i8", LIEF::assembly::arm::OPCODE::VQRSHRNuv8i8)
.value("VQRSHRNuv4i16", LIEF::assembly::arm::OPCODE::VQRSHRNuv4i16);
opcodes.value("VQRSHRNuv8i8", LIEF::assembly::arm::OPCODE::VQRSHRNuv8i8)
.value("VQRSHRUNv2i32", LIEF::assembly::arm::OPCODE::VQRSHRUNv2i32)
.value("VQRSHRUNv4i16", LIEF::assembly::arm::OPCODE::VQRSHRUNv4i16)
.value("VQRSHRUNv8i8", LIEF::assembly::arm::OPCODE::VQRSHRUNv8i8)
@@ -3305,8 +3317,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VQSHLsiv4i16", LIEF::assembly::arm::OPCODE::VQSHLsiv4i16)
.value("VQSHLsiv4i32", LIEF::assembly::arm::OPCODE::VQSHLsiv4i32)
.value("VQSHLsiv8i16", LIEF::assembly::arm::OPCODE::VQSHLsiv8i16)
.value("VQSHLsiv8i8", LIEF::assembly::arm::OPCODE::VQSHLsiv8i8);
opcodes.value("VQSHLsuv16i8", LIEF::assembly::arm::OPCODE::VQSHLsuv16i8)
.value("VQSHLsiv8i8", LIEF::assembly::arm::OPCODE::VQSHLsiv8i8)
.value("VQSHLsuv16i8", LIEF::assembly::arm::OPCODE::VQSHLsuv16i8)
.value("VQSHLsuv1i64", LIEF::assembly::arm::OPCODE::VQSHLsuv1i64)
.value("VQSHLsuv2i32", LIEF::assembly::arm::OPCODE::VQSHLsuv2i32)
.value("VQSHLsuv2i64", LIEF::assembly::arm::OPCODE::VQSHLsuv2i64)
@@ -3593,8 +3605,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VSLIv2i32", LIEF::assembly::arm::OPCODE::VSLIv2i32)
.value("VSLIv2i64", LIEF::assembly::arm::OPCODE::VSLIv2i64)
.value("VSLIv4i16", LIEF::assembly::arm::OPCODE::VSLIv4i16)
.value("VSLIv4i32", LIEF::assembly::arm::OPCODE::VSLIv4i32)
.value("VSLIv8i16", LIEF::assembly::arm::OPCODE::VSLIv8i16)
.value("VSLIv4i32", LIEF::assembly::arm::OPCODE::VSLIv4i32);
opcodes.value("VSLIv8i16", LIEF::assembly::arm::OPCODE::VSLIv8i16)
.value("VSLIv8i8", LIEF::assembly::arm::OPCODE::VSLIv8i8)
.value("VSLTOD", LIEF::assembly::arm::OPCODE::VSLTOD)
.value("VSLTOH", LIEF::assembly::arm::OPCODE::VSLTOH)
@@ -3605,8 +3617,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VSQRTS", LIEF::assembly::arm::OPCODE::VSQRTS)
.value("VSRAsv16i8", LIEF::assembly::arm::OPCODE::VSRAsv16i8)
.value("VSRAsv1i64", LIEF::assembly::arm::OPCODE::VSRAsv1i64)
.value("VSRAsv2i32", LIEF::assembly::arm::OPCODE::VSRAsv2i32);
opcodes.value("VSRAsv2i64", LIEF::assembly::arm::OPCODE::VSRAsv2i64)
.value("VSRAsv2i32", LIEF::assembly::arm::OPCODE::VSRAsv2i32)
.value("VSRAsv2i64", LIEF::assembly::arm::OPCODE::VSRAsv2i64)
.value("VSRAsv4i16", LIEF::assembly::arm::OPCODE::VSRAsv4i16)
.value("VSRAsv4i32", LIEF::assembly::arm::OPCODE::VSRAsv4i32)
.value("VSRAsv8i16", LIEF::assembly::arm::OPCODE::VSRAsv8i16)
@@ -3893,8 +3905,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VSTMSIA", LIEF::assembly::arm::OPCODE::VSTMSIA)
.value("VSTMSIA_UPD", LIEF::assembly::arm::OPCODE::VSTMSIA_UPD)
.value("VSTRD", LIEF::assembly::arm::OPCODE::VSTRD)
.value("VSTRH", LIEF::assembly::arm::OPCODE::VSTRH)
.value("VSTRS", LIEF::assembly::arm::OPCODE::VSTRS)
.value("VSTRH", LIEF::assembly::arm::OPCODE::VSTRH);
opcodes.value("VSTRS", LIEF::assembly::arm::OPCODE::VSTRS)
.value("VSTR_FPCXTNS_off", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_off)
.value("VSTR_FPCXTNS_post", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_post)
.value("VSTR_FPCXTNS_pre", LIEF::assembly::arm::OPCODE::VSTR_FPCXTNS_pre)
@@ -3905,8 +3917,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("VSTR_FPSCR_NZCVQC_post", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_NZCVQC_post)
.value("VSTR_FPSCR_NZCVQC_pre", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_NZCVQC_pre)
.value("VSTR_FPSCR_off", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_off)
.value("VSTR_FPSCR_post", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_post);
opcodes.value("VSTR_FPSCR_pre", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_pre)
.value("VSTR_FPSCR_post", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_post)
.value("VSTR_FPSCR_pre", LIEF::assembly::arm::OPCODE::VSTR_FPSCR_pre)
.value("VSTR_P0_off", LIEF::assembly::arm::OPCODE::VSTR_P0_off)
.value("VSTR_P0_post", LIEF::assembly::arm::OPCODE::VSTR_P0_post)
.value("VSTR_P0_pre", LIEF::assembly::arm::OPCODE::VSTR_P0_pre)
@@ -4079,8 +4091,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("t2CLRM", LIEF::assembly::arm::OPCODE::t2CLRM)
.value("t2CLZ", LIEF::assembly::arm::OPCODE::t2CLZ)
.value("t2CMNri", LIEF::assembly::arm::OPCODE::t2CMNri)
.value("t2CMNzrr", LIEF::assembly::arm::OPCODE::t2CMNzrr)
.value("t2CMNzrs", LIEF::assembly::arm::OPCODE::t2CMNzrs)
.value("t2CMNrr", LIEF::assembly::arm::OPCODE::t2CMNrr)
.value("t2CMNrs", LIEF::assembly::arm::OPCODE::t2CMNrs)
.value("t2CMPri", LIEF::assembly::arm::OPCODE::t2CMPri)
.value("t2CMPrr", LIEF::assembly::arm::OPCODE::t2CMPrr)
.value("t2CMPrs", LIEF::assembly::arm::OPCODE::t2CMPrs)
@@ -4193,8 +4205,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("t2MCR2", LIEF::assembly::arm::OPCODE::t2MCR2)
.value("t2MCRR", LIEF::assembly::arm::OPCODE::t2MCRR)
.value("t2MCRR2", LIEF::assembly::arm::OPCODE::t2MCRR2)
.value("t2MLA", LIEF::assembly::arm::OPCODE::t2MLA)
.value("t2MLS", LIEF::assembly::arm::OPCODE::t2MLS)
.value("t2MLA", LIEF::assembly::arm::OPCODE::t2MLA);
opcodes.value("t2MLS", LIEF::assembly::arm::OPCODE::t2MLS)
.value("t2MOVTi16", LIEF::assembly::arm::OPCODE::t2MOVTi16)
.value("t2MOVi", LIEF::assembly::arm::OPCODE::t2MOVi)
.value("t2MOVi16", LIEF::assembly::arm::OPCODE::t2MOVi16)
@@ -4205,8 +4217,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("t2MRRC2", LIEF::assembly::arm::OPCODE::t2MRRC2)
.value("t2MRS_AR", LIEF::assembly::arm::OPCODE::t2MRS_AR)
.value("t2MRS_M", LIEF::assembly::arm::OPCODE::t2MRS_M)
.value("t2MRSbanked", LIEF::assembly::arm::OPCODE::t2MRSbanked);
opcodes.value("t2MRSsys_AR", LIEF::assembly::arm::OPCODE::t2MRSsys_AR)
.value("t2MRSbanked", LIEF::assembly::arm::OPCODE::t2MRSbanked)
.value("t2MRSsys_AR", LIEF::assembly::arm::OPCODE::t2MRSsys_AR)
.value("t2MSR_AR", LIEF::assembly::arm::OPCODE::t2MSR_AR)
.value("t2MSR_M", LIEF::assembly::arm::OPCODE::t2MSR_M)
.value("t2MSRbanked", LIEF::assembly::arm::OPCODE::t2MSRbanked)
@@ -4462,7 +4474,7 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("tBcc", LIEF::assembly::arm::OPCODE::tBcc)
.value("tCBNZ", LIEF::assembly::arm::OPCODE::tCBNZ)
.value("tCBZ", LIEF::assembly::arm::OPCODE::tCBZ)
.value("tCMNz", LIEF::assembly::arm::OPCODE::tCMNz)
.value("tCMN", LIEF::assembly::arm::OPCODE::tCMN)
.value("tCMPhir", LIEF::assembly::arm::OPCODE::tCMPhir)
.value("tCMPi8", LIEF::assembly::arm::OPCODE::tCMPi8)
.value("tCMPr", LIEF::assembly::arm::OPCODE::tCMPr)
@@ -4493,8 +4505,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("tMOVr", LIEF::assembly::arm::OPCODE::tMOVr)
.value("tMUL", LIEF::assembly::arm::OPCODE::tMUL)
.value("tMVN", LIEF::assembly::arm::OPCODE::tMVN)
.value("tORR", LIEF::assembly::arm::OPCODE::tORR)
.value("tPICADD", LIEF::assembly::arm::OPCODE::tPICADD)
.value("tORR", LIEF::assembly::arm::OPCODE::tORR);
opcodes.value("tPICADD", LIEF::assembly::arm::OPCODE::tPICADD)
.value("tPOP", LIEF::assembly::arm::OPCODE::tPOP)
.value("tPUSH", LIEF::assembly::arm::OPCODE::tPUSH)
.value("tREV", LIEF::assembly::arm::OPCODE::tREV)
@@ -4505,8 +4517,8 @@ void create<LIEF::assembly::arm::OPCODE>(nb::module_& m) {
.value("tSBC", LIEF::assembly::arm::OPCODE::tSBC)
.value("tSETEND", LIEF::assembly::arm::OPCODE::tSETEND)
.value("tSTMIA_UPD", LIEF::assembly::arm::OPCODE::tSTMIA_UPD)
.value("tSTRBi", LIEF::assembly::arm::OPCODE::tSTRBi);
opcodes.value("tSTRBr", LIEF::assembly::arm::OPCODE::tSTRBr)
.value("tSTRBi", LIEF::assembly::arm::OPCODE::tSTRBi)
.value("tSTRBr", LIEF::assembly::arm::OPCODE::tSTRBr)
.value("tSTRHi", LIEF::assembly::arm::OPCODE::tSTRHi)
.value("tSTRHr", LIEF::assembly::arm::OPCODE::tSTRHr)
.value("tSTRi", LIEF::assembly::arm::OPCODE::tSTRi)
api/python/src/asm/ebpf/pyOpcode.cpp
+16 -4
View File
@@ -108,10 +108,12 @@ void create<LIEF::assembly::ebpf::OPCODE>(nb::module_& m) {
.value("G_LOAD", LIEF::assembly::ebpf::OPCODE::G_LOAD)
.value("G_SEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_SEXTLOAD)
.value("G_ZEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_ZEXTLOAD)
.value("G_FPEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_FPEXTLOAD)
.value("G_INDEXED_LOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_LOAD)
.value("G_INDEXED_SEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_SEXTLOAD)
.value("G_INDEXED_ZEXTLOAD", LIEF::assembly::ebpf::OPCODE::G_INDEXED_ZEXTLOAD)
.value("G_STORE", LIEF::assembly::ebpf::OPCODE::G_STORE)
.value("G_FPTRUNCSTORE", LIEF::assembly::ebpf::OPCODE::G_FPTRUNCSTORE)
.value("G_INDEXED_STORE", LIEF::assembly::ebpf::OPCODE::G_INDEXED_STORE)
.value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::ebpf::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
.value("G_ATOMIC_CMPXCHG", LIEF::assembly::ebpf::OPCODE::G_ATOMIC_CMPXCHG)
@@ -132,6 +134,8 @@ void create<LIEF::assembly::ebpf::OPCODE>(nb::module_& m) {
.value("G_ATOMICRMW_FMIN", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMIN)
.value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMAXIMUM)
.value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMINIMUM)
.value("G_ATOMICRMW_FMAXIMUMNUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMAXIMUMNUM)
.value("G_ATOMICRMW_FMINIMUMNUM", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_FMINIMUMNUM)
.value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UINC_WRAP)
.value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_UDEC_WRAP)
.value("G_ATOMICRMW_USUB_COND", LIEF::assembly::ebpf::OPCODE::G_ATOMICRMW_USUB_COND)
@@ -263,12 +267,14 @@ void create<LIEF::assembly::ebpf::OPCODE>(nb::module_& m) {
.value("G_STEP_VECTOR", LIEF::assembly::ebpf::OPCODE::G_STEP_VECTOR)
.value("G_VECTOR_COMPRESS", LIEF::assembly::ebpf::OPCODE::G_VECTOR_COMPRESS)
.value("G_CTTZ", LIEF::assembly::ebpf::OPCODE::G_CTTZ)
.value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::ebpf::OPCODE::G_CTTZ_ZERO_UNDEF)
.value("G_CTTZ_ZERO_POISON", LIEF::assembly::ebpf::OPCODE::G_CTTZ_ZERO_POISON)
.value("G_CTLZ", LIEF::assembly::ebpf::OPCODE::G_CTLZ)
.value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::ebpf::OPCODE::G_CTLZ_ZERO_UNDEF)
.value("G_CTLZ_ZERO_POISON", LIEF::assembly::ebpf::OPCODE::G_CTLZ_ZERO_POISON)
.value("G_CTLS", LIEF::assembly::ebpf::OPCODE::G_CTLS)
.value("G_CTPOP", LIEF::assembly::ebpf::OPCODE::G_CTPOP)
.value("G_BSWAP", LIEF::assembly::ebpf::OPCODE::G_BSWAP)
.value("G_BITREVERSE", LIEF::assembly::ebpf::OPCODE::G_BITREVERSE)
.value("G_CLMUL", LIEF::assembly::ebpf::OPCODE::G_CLMUL)
.value("G_FCEIL", LIEF::assembly::ebpf::OPCODE::G_FCEIL)
.value("G_FCOS", LIEF::assembly::ebpf::OPCODE::G_FCOS)
.value("G_FSIN", LIEF::assembly::ebpf::OPCODE::G_FSIN)
@@ -299,14 +305,17 @@ void create<LIEF::assembly::ebpf::OPCODE>(nb::module_& m) {
.value("G_STRICT_FMA", LIEF::assembly::ebpf::OPCODE::G_STRICT_FMA)
.value("G_STRICT_FSQRT", LIEF::assembly::ebpf::OPCODE::G_STRICT_FSQRT)
.value("G_STRICT_FLDEXP", LIEF::assembly::ebpf::OPCODE::G_STRICT_FLDEXP)
.value("G_STRICT_FCMP", LIEF::assembly::ebpf::OPCODE::G_STRICT_FCMP);
opcodes.value("G_STRICT_FCMPS", LIEF::assembly::ebpf::OPCODE::G_STRICT_FCMPS)
.value("G_READ_REGISTER", LIEF::assembly::ebpf::OPCODE::G_READ_REGISTER)
.value("G_WRITE_REGISTER", LIEF::assembly::ebpf::OPCODE::G_WRITE_REGISTER)
.value("G_MEMCPY", LIEF::assembly::ebpf::OPCODE::G_MEMCPY)
.value("G_MEMCPY_INLINE", LIEF::assembly::ebpf::OPCODE::G_MEMCPY_INLINE)
.value("G_MEMMOVE", LIEF::assembly::ebpf::OPCODE::G_MEMMOVE)
.value("G_MEMSET", LIEF::assembly::ebpf::OPCODE::G_MEMSET)
.value("G_BZERO", LIEF::assembly::ebpf::OPCODE::G_BZERO);
opcodes.value("G_TRAP", LIEF::assembly::ebpf::OPCODE::G_TRAP)
.value("G_BZERO", LIEF::assembly::ebpf::OPCODE::G_BZERO)
.value("G_MEMSET_INLINE", LIEF::assembly::ebpf::OPCODE::G_MEMSET_INLINE)
.value("G_TRAP", LIEF::assembly::ebpf::OPCODE::G_TRAP)
.value("G_DEBUGTRAP", LIEF::assembly::ebpf::OPCODE::G_DEBUGTRAP)
.value("G_UBSANTRAP", LIEF::assembly::ebpf::OPCODE::G_UBSANTRAP)
.value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::ebpf::OPCODE::G_VECREDUCE_SEQ_FADD)
@@ -332,7 +341,10 @@ void create<LIEF::assembly::ebpf::OPCODE>(nb::module_& m) {
.value("ADJCALLSTACKUP", LIEF::assembly::ebpf::OPCODE::ADJCALLSTACKUP)
.value("FI_ri", LIEF::assembly::ebpf::OPCODE::FI_ri)
.value("LDIMM64", LIEF::assembly::ebpf::OPCODE::LDIMM64)
.value("LOAD_STACK_ARG_PSEUDO", LIEF::assembly::ebpf::OPCODE::LOAD_STACK_ARG_PSEUDO)
.value("MEMCPY", LIEF::assembly::ebpf::OPCODE::MEMCPY)
.value("STORE_STACK_ARG_IMM_PSEUDO", LIEF::assembly::ebpf::OPCODE::STORE_STACK_ARG_IMM_PSEUDO)
.value("STORE_STACK_ARG_PSEUDO", LIEF::assembly::ebpf::OPCODE::STORE_STACK_ARG_PSEUDO)
.value("Select", LIEF::assembly::ebpf::OPCODE::Select)
.value("Select_32", LIEF::assembly::ebpf::OPCODE::Select_32)
.value("Select_32_64", LIEF::assembly::ebpf::OPCODE::Select_32_64)
api/python/src/asm/mips/pyOpcode.cpp
+45 -42
View File
@@ -108,10 +108,12 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("G_LOAD", LIEF::assembly::mips::OPCODE::G_LOAD)
.value("G_SEXTLOAD", LIEF::assembly::mips::OPCODE::G_SEXTLOAD)
.value("G_ZEXTLOAD", LIEF::assembly::mips::OPCODE::G_ZEXTLOAD)
.value("G_FPEXTLOAD", LIEF::assembly::mips::OPCODE::G_FPEXTLOAD)
.value("G_INDEXED_LOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_LOAD)
.value("G_INDEXED_SEXTLOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_SEXTLOAD)
.value("G_INDEXED_ZEXTLOAD", LIEF::assembly::mips::OPCODE::G_INDEXED_ZEXTLOAD)
.value("G_STORE", LIEF::assembly::mips::OPCODE::G_STORE)
.value("G_FPTRUNCSTORE", LIEF::assembly::mips::OPCODE::G_FPTRUNCSTORE)
.value("G_INDEXED_STORE", LIEF::assembly::mips::OPCODE::G_INDEXED_STORE)
.value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::mips::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
.value("G_ATOMIC_CMPXCHG", LIEF::assembly::mips::OPCODE::G_ATOMIC_CMPXCHG)
@@ -132,6 +134,8 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("G_ATOMICRMW_FMIN", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMIN)
.value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMAXIMUM)
.value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMINIMUM)
.value("G_ATOMICRMW_FMAXIMUMNUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMAXIMUMNUM)
.value("G_ATOMICRMW_FMINIMUMNUM", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_FMINIMUMNUM)
.value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UINC_WRAP)
.value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_UDEC_WRAP)
.value("G_ATOMICRMW_USUB_COND", LIEF::assembly::mips::OPCODE::G_ATOMICRMW_USUB_COND)
@@ -263,12 +267,14 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("G_STEP_VECTOR", LIEF::assembly::mips::OPCODE::G_STEP_VECTOR)
.value("G_VECTOR_COMPRESS", LIEF::assembly::mips::OPCODE::G_VECTOR_COMPRESS)
.value("G_CTTZ", LIEF::assembly::mips::OPCODE::G_CTTZ)
.value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::mips::OPCODE::G_CTTZ_ZERO_UNDEF)
.value("G_CTTZ_ZERO_POISON", LIEF::assembly::mips::OPCODE::G_CTTZ_ZERO_POISON)
.value("G_CTLZ", LIEF::assembly::mips::OPCODE::G_CTLZ)
.value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::mips::OPCODE::G_CTLZ_ZERO_UNDEF)
.value("G_CTLZ_ZERO_POISON", LIEF::assembly::mips::OPCODE::G_CTLZ_ZERO_POISON)
.value("G_CTLS", LIEF::assembly::mips::OPCODE::G_CTLS)
.value("G_CTPOP", LIEF::assembly::mips::OPCODE::G_CTPOP)
.value("G_BSWAP", LIEF::assembly::mips::OPCODE::G_BSWAP)
.value("G_BITREVERSE", LIEF::assembly::mips::OPCODE::G_BITREVERSE)
.value("G_CLMUL", LIEF::assembly::mips::OPCODE::G_CLMUL)
.value("G_FCEIL", LIEF::assembly::mips::OPCODE::G_FCEIL)
.value("G_FCOS", LIEF::assembly::mips::OPCODE::G_FCOS)
.value("G_FSIN", LIEF::assembly::mips::OPCODE::G_FSIN)
@@ -299,14 +305,17 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("G_STRICT_FMA", LIEF::assembly::mips::OPCODE::G_STRICT_FMA)
.value("G_STRICT_FSQRT", LIEF::assembly::mips::OPCODE::G_STRICT_FSQRT)
.value("G_STRICT_FLDEXP", LIEF::assembly::mips::OPCODE::G_STRICT_FLDEXP)
.value("G_STRICT_FCMP", LIEF::assembly::mips::OPCODE::G_STRICT_FCMP);
opcodes.value("G_STRICT_FCMPS", LIEF::assembly::mips::OPCODE::G_STRICT_FCMPS)
.value("G_READ_REGISTER", LIEF::assembly::mips::OPCODE::G_READ_REGISTER)
.value("G_WRITE_REGISTER", LIEF::assembly::mips::OPCODE::G_WRITE_REGISTER)
.value("G_MEMCPY", LIEF::assembly::mips::OPCODE::G_MEMCPY)
.value("G_MEMCPY_INLINE", LIEF::assembly::mips::OPCODE::G_MEMCPY_INLINE)
.value("G_MEMMOVE", LIEF::assembly::mips::OPCODE::G_MEMMOVE)
.value("G_MEMSET", LIEF::assembly::mips::OPCODE::G_MEMSET)
.value("G_BZERO", LIEF::assembly::mips::OPCODE::G_BZERO);
opcodes.value("G_TRAP", LIEF::assembly::mips::OPCODE::G_TRAP)
.value("G_BZERO", LIEF::assembly::mips::OPCODE::G_BZERO)
.value("G_MEMSET_INLINE", LIEF::assembly::mips::OPCODE::G_MEMSET_INLINE)
.value("G_TRAP", LIEF::assembly::mips::OPCODE::G_TRAP)
.value("G_DEBUGTRAP", LIEF::assembly::mips::OPCODE::G_DEBUGTRAP)
.value("G_UBSANTRAP", LIEF::assembly::mips::OPCODE::G_UBSANTRAP)
.value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::mips::OPCODE::G_VECREDUCE_SEQ_FADD)
@@ -548,7 +557,6 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("LDMacro", LIEF::assembly::mips::OPCODE::LDMacro)
.value("LDR_D", LIEF::assembly::mips::OPCODE::LDR_D)
.value("LDR_W", LIEF::assembly::mips::OPCODE::LDR_W)
.value("LD_F16", LIEF::assembly::mips::OPCODE::LD_F16)
.value("LOAD_ACC128", LIEF::assembly::mips::OPCODE::LOAD_ACC128)
.value("LOAD_ACC64", LIEF::assembly::mips::OPCODE::LOAD_ACC64)
.value("LOAD_ACC64DSP", LIEF::assembly::mips::OPCODE::LOAD_ACC64DSP)
@@ -583,10 +591,6 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("MFTLO", LIEF::assembly::mips::OPCODE::MFTLO)
.value("MIPSeh_return32", LIEF::assembly::mips::OPCODE::MIPSeh_return32)
.value("MIPSeh_return64", LIEF::assembly::mips::OPCODE::MIPSeh_return64)
.value("MSA_FP_EXTEND_D_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_EXTEND_D_PSEUDO)
.value("MSA_FP_EXTEND_W_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_EXTEND_W_PSEUDO)
.value("MSA_FP_ROUND_D_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_ROUND_D_PSEUDO)
.value("MSA_FP_ROUND_W_PSEUDO", LIEF::assembly::mips::OPCODE::MSA_FP_ROUND_W_PSEUDO)
.value("MTTACX", LIEF::assembly::mips::OPCODE::MTTACX)
.value("MTTC0", LIEF::assembly::mips::OPCODE::MTTC0)
.value("MTTC1", LIEF::assembly::mips::OPCODE::MTTC1)
@@ -601,12 +605,12 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("MultRxRy16", LIEF::assembly::mips::OPCODE::MultRxRy16)
.value("MultRxRyRz16", LIEF::assembly::mips::OPCODE::MultRxRyRz16)
.value("MultuRxRy16", LIEF::assembly::mips::OPCODE::MultuRxRy16)
.value("MultuRxRyRz16", LIEF::assembly::mips::OPCODE::MultuRxRyRz16)
.value("NOP", LIEF::assembly::mips::OPCODE::NOP)
.value("MultuRxRyRz16", LIEF::assembly::mips::OPCODE::MultuRxRyRz16);
opcodes.value("NOP", LIEF::assembly::mips::OPCODE::NOP)
.value("NORImm", LIEF::assembly::mips::OPCODE::NORImm)
.value("NORImm64", LIEF::assembly::mips::OPCODE::NORImm64)
.value("NOR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_D_PSEUDO);
opcodes.value("NOR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_H_PSEUDO)
.value("NOR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_D_PSEUDO)
.value("NOR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_H_PSEUDO)
.value("NOR_V_W_PSEUDO", LIEF::assembly::mips::OPCODE::NOR_V_W_PSEUDO)
.value("OR_V_D_PSEUDO", LIEF::assembly::mips::OPCODE::OR_V_D_PSEUDO)
.value("OR_V_H_PSEUDO", LIEF::assembly::mips::OPCODE::OR_V_H_PSEUDO)
@@ -730,7 +734,6 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("STORE_CCOND_DSP", LIEF::assembly::mips::OPCODE::STORE_CCOND_DSP)
.value("STR_D", LIEF::assembly::mips::OPCODE::STR_D)
.value("STR_W", LIEF::assembly::mips::OPCODE::STR_W)
.value("ST_F16", LIEF::assembly::mips::OPCODE::ST_F16)
.value("SWM_MM", LIEF::assembly::mips::OPCODE::SWM_MM)
.value("SZ_B_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_B_PSEUDO)
.value("SZ_D_PSEUDO", LIEF::assembly::mips::OPCODE::SZ_D_PSEUDO)
@@ -902,11 +905,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("AVER_S_B", LIEF::assembly::mips::OPCODE::AVER_S_B)
.value("AVER_S_D", LIEF::assembly::mips::OPCODE::AVER_S_D)
.value("AVER_S_H", LIEF::assembly::mips::OPCODE::AVER_S_H)
.value("AVER_S_W", LIEF::assembly::mips::OPCODE::AVER_S_W)
.value("AVER_U_B", LIEF::assembly::mips::OPCODE::AVER_U_B)
.value("AVER_S_W", LIEF::assembly::mips::OPCODE::AVER_S_W);
opcodes.value("AVER_U_B", LIEF::assembly::mips::OPCODE::AVER_U_B)
.value("AVER_U_D", LIEF::assembly::mips::OPCODE::AVER_U_D)
.value("AVER_U_H", LIEF::assembly::mips::OPCODE::AVER_U_H);
opcodes.value("AVER_U_W", LIEF::assembly::mips::OPCODE::AVER_U_W)
.value("AVER_U_H", LIEF::assembly::mips::OPCODE::AVER_U_H)
.value("AVER_U_W", LIEF::assembly::mips::OPCODE::AVER_U_W)
.value("AVE_S_B", LIEF::assembly::mips::OPCODE::AVE_S_B)
.value("AVE_S_D", LIEF::assembly::mips::OPCODE::AVE_S_D)
.value("AVE_S_H", LIEF::assembly::mips::OPCODE::AVE_S_H)
@@ -1202,11 +1205,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("CMPGDU_EQ_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_EQ_QB_MMR2)
.value("CMPGDU_LE_QB", LIEF::assembly::mips::OPCODE::CMPGDU_LE_QB)
.value("CMPGDU_LE_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_LE_QB_MMR2)
.value("CMPGDU_LT_QB", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB)
.value("CMPGDU_LT_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB_MMR2)
.value("CMPGDU_LT_QB", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB);
opcodes.value("CMPGDU_LT_QB_MMR2", LIEF::assembly::mips::OPCODE::CMPGDU_LT_QB_MMR2)
.value("CMPGU_EQ_QB", LIEF::assembly::mips::OPCODE::CMPGU_EQ_QB)
.value("CMPGU_EQ_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_EQ_QB_MM);
opcodes.value("CMPGU_LE_QB", LIEF::assembly::mips::OPCODE::CMPGU_LE_QB)
.value("CMPGU_EQ_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_EQ_QB_MM)
.value("CMPGU_LE_QB", LIEF::assembly::mips::OPCODE::CMPGU_LE_QB)
.value("CMPGU_LE_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_LE_QB_MM)
.value("CMPGU_LT_QB", LIEF::assembly::mips::OPCODE::CMPGU_LT_QB)
.value("CMPGU_LT_QB_MM", LIEF::assembly::mips::OPCODE::CMPGU_LT_QB_MM)
@@ -1502,11 +1505,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("DMULT", LIEF::assembly::mips::OPCODE::DMULT)
.value("DMULTu", LIEF::assembly::mips::OPCODE::DMULTu)
.value("DMULU", LIEF::assembly::mips::OPCODE::DMULU)
.value("DMUL_R6", LIEF::assembly::mips::OPCODE::DMUL_R6)
.value("DOTP_S_D", LIEF::assembly::mips::OPCODE::DOTP_S_D)
.value("DMUL_R6", LIEF::assembly::mips::OPCODE::DMUL_R6);
opcodes.value("DOTP_S_D", LIEF::assembly::mips::OPCODE::DOTP_S_D)
.value("DOTP_S_H", LIEF::assembly::mips::OPCODE::DOTP_S_H)
.value("DOTP_S_W", LIEF::assembly::mips::OPCODE::DOTP_S_W);
opcodes.value("DOTP_U_D", LIEF::assembly::mips::OPCODE::DOTP_U_D)
.value("DOTP_S_W", LIEF::assembly::mips::OPCODE::DOTP_S_W)
.value("DOTP_U_D", LIEF::assembly::mips::OPCODE::DOTP_U_D)
.value("DOTP_U_H", LIEF::assembly::mips::OPCODE::DOTP_U_H)
.value("DOTP_U_W", LIEF::assembly::mips::OPCODE::DOTP_U_W)
.value("DPADD_S_D", LIEF::assembly::mips::OPCODE::DPADD_S_D)
@@ -1802,11 +1805,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("FTRUNC_S_D", LIEF::assembly::mips::OPCODE::FTRUNC_S_D)
.value("FTRUNC_S_W", LIEF::assembly::mips::OPCODE::FTRUNC_S_W)
.value("FTRUNC_U_D", LIEF::assembly::mips::OPCODE::FTRUNC_U_D)
.value("FTRUNC_U_W", LIEF::assembly::mips::OPCODE::FTRUNC_U_W)
.value("GINVI", LIEF::assembly::mips::OPCODE::GINVI)
.value("FTRUNC_U_W", LIEF::assembly::mips::OPCODE::FTRUNC_U_W);
opcodes.value("GINVI", LIEF::assembly::mips::OPCODE::GINVI)
.value("GINVI_MMR6", LIEF::assembly::mips::OPCODE::GINVI_MMR6)
.value("GINVT", LIEF::assembly::mips::OPCODE::GINVT);
opcodes.value("GINVT_MMR6", LIEF::assembly::mips::OPCODE::GINVT_MMR6)
.value("GINVT", LIEF::assembly::mips::OPCODE::GINVT)
.value("GINVT_MMR6", LIEF::assembly::mips::OPCODE::GINVT_MMR6)
.value("HADD_S_D", LIEF::assembly::mips::OPCODE::HADD_S_D)
.value("HADD_S_H", LIEF::assembly::mips::OPCODE::HADD_S_H)
.value("HADD_S_W", LIEF::assembly::mips::OPCODE::HADD_S_W)
@@ -2102,11 +2105,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("MFHI", LIEF::assembly::mips::OPCODE::MFHI)
.value("MFHI16_MM", LIEF::assembly::mips::OPCODE::MFHI16_MM)
.value("MFHI64", LIEF::assembly::mips::OPCODE::MFHI64)
.value("MFHI_DSP", LIEF::assembly::mips::OPCODE::MFHI_DSP)
.value("MFHI_DSP_MM", LIEF::assembly::mips::OPCODE::MFHI_DSP_MM)
.value("MFHI_DSP", LIEF::assembly::mips::OPCODE::MFHI_DSP);
opcodes.value("MFHI_DSP_MM", LIEF::assembly::mips::OPCODE::MFHI_DSP_MM)
.value("MFHI_MM", LIEF::assembly::mips::OPCODE::MFHI_MM)
.value("MFLO", LIEF::assembly::mips::OPCODE::MFLO);
opcodes.value("MFLO16_MM", LIEF::assembly::mips::OPCODE::MFLO16_MM)
.value("MFLO", LIEF::assembly::mips::OPCODE::MFLO)
.value("MFLO16_MM", LIEF::assembly::mips::OPCODE::MFLO16_MM)
.value("MFLO64", LIEF::assembly::mips::OPCODE::MFLO64)
.value("MFLO_DSP", LIEF::assembly::mips::OPCODE::MFLO_DSP)
.value("MFLO_DSP_MM", LIEF::assembly::mips::OPCODE::MFLO_DSP_MM)
@@ -2402,11 +2405,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("PRECEU_PH_QBR", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBR)
.value("PRECEU_PH_QBRA", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBRA)
.value("PRECEU_PH_QBRA_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBRA_MM)
.value("PRECEU_PH_QBR_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBR_MM)
.value("PRECRQU_S_QB_PH", LIEF::assembly::mips::OPCODE::PRECRQU_S_QB_PH)
.value("PRECEU_PH_QBR_MM", LIEF::assembly::mips::OPCODE::PRECEU_PH_QBR_MM);
opcodes.value("PRECRQU_S_QB_PH", LIEF::assembly::mips::OPCODE::PRECRQU_S_QB_PH)
.value("PRECRQU_S_QB_PH_MM", LIEF::assembly::mips::OPCODE::PRECRQU_S_QB_PH_MM)
.value("PRECRQ_PH_W", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W);
opcodes.value("PRECRQ_PH_W_MM", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W_MM)
.value("PRECRQ_PH_W", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W)
.value("PRECRQ_PH_W_MM", LIEF::assembly::mips::OPCODE::PRECRQ_PH_W_MM)
.value("PRECRQ_QB_PH", LIEF::assembly::mips::OPCODE::PRECRQ_QB_PH)
.value("PRECRQ_QB_PH_MM", LIEF::assembly::mips::OPCODE::PRECRQ_QB_PH_MM)
.value("PRECRQ_RS_PH_W", LIEF::assembly::mips::OPCODE::PRECRQ_RS_PH_W)
@@ -2702,11 +2705,11 @@ void create<LIEF::assembly::mips::OPCODE>(nb::module_& m) {
.value("SRL_B", LIEF::assembly::mips::OPCODE::SRL_B)
.value("SRL_D", LIEF::assembly::mips::OPCODE::SRL_D)
.value("SRL_H", LIEF::assembly::mips::OPCODE::SRL_H)
.value("SRL_MM", LIEF::assembly::mips::OPCODE::SRL_MM)
.value("SRL_W", LIEF::assembly::mips::OPCODE::SRL_W)
.value("SRL_MM", LIEF::assembly::mips::OPCODE::SRL_MM);
opcodes.value("SRL_W", LIEF::assembly::mips::OPCODE::SRL_W)
.value("SSNOP", LIEF::assembly::mips::OPCODE::SSNOP)
.value("SSNOP_MM", LIEF::assembly::mips::OPCODE::SSNOP_MM);
opcodes.value("SSNOP_MMR6", LIEF::assembly::mips::OPCODE::SSNOP_MMR6)
.value("SSNOP_MM", LIEF::assembly::mips::OPCODE::SSNOP_MM)
.value("SSNOP_MMR6", LIEF::assembly::mips::OPCODE::SSNOP_MMR6)
.value("ST_B", LIEF::assembly::mips::OPCODE::ST_B)
.value("ST_D", LIEF::assembly::mips::OPCODE::ST_D)
.value("ST_H", LIEF::assembly::mips::OPCODE::ST_H)
api/python/src/asm/powerpc/pyOpcode.cpp
+75 -69
View File
@@ -108,10 +108,12 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("G_LOAD", LIEF::assembly::powerpc::OPCODE::G_LOAD)
.value("G_SEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_SEXTLOAD)
.value("G_ZEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_ZEXTLOAD)
.value("G_FPEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_FPEXTLOAD)
.value("G_INDEXED_LOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_LOAD)
.value("G_INDEXED_SEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_SEXTLOAD)
.value("G_INDEXED_ZEXTLOAD", LIEF::assembly::powerpc::OPCODE::G_INDEXED_ZEXTLOAD)
.value("G_STORE", LIEF::assembly::powerpc::OPCODE::G_STORE)
.value("G_FPTRUNCSTORE", LIEF::assembly::powerpc::OPCODE::G_FPTRUNCSTORE)
.value("G_INDEXED_STORE", LIEF::assembly::powerpc::OPCODE::G_INDEXED_STORE)
.value("G_ATOMIC_CMPXCHG_WITH_SUCCESS", LIEF::assembly::powerpc::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
.value("G_ATOMIC_CMPXCHG", LIEF::assembly::powerpc::OPCODE::G_ATOMIC_CMPXCHG)
@@ -132,6 +134,8 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("G_ATOMICRMW_FMIN", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMIN)
.value("G_ATOMICRMW_FMAXIMUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMAXIMUM)
.value("G_ATOMICRMW_FMINIMUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMINIMUM)
.value("G_ATOMICRMW_FMAXIMUMNUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMAXIMUMNUM)
.value("G_ATOMICRMW_FMINIMUMNUM", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_FMINIMUMNUM)
.value("G_ATOMICRMW_UINC_WRAP", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UINC_WRAP)
.value("G_ATOMICRMW_UDEC_WRAP", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_UDEC_WRAP)
.value("G_ATOMICRMW_USUB_COND", LIEF::assembly::powerpc::OPCODE::G_ATOMICRMW_USUB_COND)
@@ -263,12 +267,14 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("G_STEP_VECTOR", LIEF::assembly::powerpc::OPCODE::G_STEP_VECTOR)
.value("G_VECTOR_COMPRESS", LIEF::assembly::powerpc::OPCODE::G_VECTOR_COMPRESS)
.value("G_CTTZ", LIEF::assembly::powerpc::OPCODE::G_CTTZ)
.value("G_CTTZ_ZERO_UNDEF", LIEF::assembly::powerpc::OPCODE::G_CTTZ_ZERO_UNDEF)
.value("G_CTTZ_ZERO_POISON", LIEF::assembly::powerpc::OPCODE::G_CTTZ_ZERO_POISON)
.value("G_CTLZ", LIEF::assembly::powerpc::OPCODE::G_CTLZ)
.value("G_CTLZ_ZERO_UNDEF", LIEF::assembly::powerpc::OPCODE::G_CTLZ_ZERO_UNDEF)
.value("G_CTLZ_ZERO_POISON", LIEF::assembly::powerpc::OPCODE::G_CTLZ_ZERO_POISON)
.value("G_CTLS", LIEF::assembly::powerpc::OPCODE::G_CTLS)
.value("G_CTPOP", LIEF::assembly::powerpc::OPCODE::G_CTPOP)
.value("G_BSWAP", LIEF::assembly::powerpc::OPCODE::G_BSWAP)
.value("G_BITREVERSE", LIEF::assembly::powerpc::OPCODE::G_BITREVERSE)
.value("G_CLMUL", LIEF::assembly::powerpc::OPCODE::G_CLMUL)
.value("G_FCEIL", LIEF::assembly::powerpc::OPCODE::G_FCEIL)
.value("G_FCOS", LIEF::assembly::powerpc::OPCODE::G_FCOS)
.value("G_FSIN", LIEF::assembly::powerpc::OPCODE::G_FSIN)
@@ -299,14 +305,17 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("G_STRICT_FMA", LIEF::assembly::powerpc::OPCODE::G_STRICT_FMA)
.value("G_STRICT_FSQRT", LIEF::assembly::powerpc::OPCODE::G_STRICT_FSQRT)
.value("G_STRICT_FLDEXP", LIEF::assembly::powerpc::OPCODE::G_STRICT_FLDEXP)
.value("G_STRICT_FCMP", LIEF::assembly::powerpc::OPCODE::G_STRICT_FCMP);
opcodes.value("G_STRICT_FCMPS", LIEF::assembly::powerpc::OPCODE::G_STRICT_FCMPS)
.value("G_READ_REGISTER", LIEF::assembly::powerpc::OPCODE::G_READ_REGISTER)
.value("G_WRITE_REGISTER", LIEF::assembly::powerpc::OPCODE::G_WRITE_REGISTER)
.value("G_MEMCPY", LIEF::assembly::powerpc::OPCODE::G_MEMCPY)
.value("G_MEMCPY_INLINE", LIEF::assembly::powerpc::OPCODE::G_MEMCPY_INLINE)
.value("G_MEMMOVE", LIEF::assembly::powerpc::OPCODE::G_MEMMOVE)
.value("G_MEMSET", LIEF::assembly::powerpc::OPCODE::G_MEMSET)
.value("G_BZERO", LIEF::assembly::powerpc::OPCODE::G_BZERO);
opcodes.value("G_TRAP", LIEF::assembly::powerpc::OPCODE::G_TRAP)
.value("G_BZERO", LIEF::assembly::powerpc::OPCODE::G_BZERO)
.value("G_MEMSET_INLINE", LIEF::assembly::powerpc::OPCODE::G_MEMSET_INLINE)
.value("G_TRAP", LIEF::assembly::powerpc::OPCODE::G_TRAP)
.value("G_DEBUGTRAP", LIEF::assembly::powerpc::OPCODE::G_DEBUGTRAP)
.value("G_UBSANTRAP", LIEF::assembly::powerpc::OPCODE::G_UBSANTRAP)
.value("G_VECREDUCE_SEQ_FADD", LIEF::assembly::powerpc::OPCODE::G_VECREDUCE_SEQ_FADD)
@@ -381,8 +390,10 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("INSRWI_rec", LIEF::assembly::powerpc::OPCODE::INSRWI_rec)
.value("KILL_PAIR", LIEF::assembly::powerpc::OPCODE::KILL_PAIR)
.value("LAx", LIEF::assembly::powerpc::OPCODE::LAx)
.value("LDAT_CSNE_PSEUDO", LIEF::assembly::powerpc::OPCODE::LDAT_CSNE_PSEUDO)
.value("LIWAX", LIEF::assembly::powerpc::OPCODE::LIWAX)
.value("LIWZX", LIEF::assembly::powerpc::OPCODE::LIWZX)
.value("LWAT_CSNE_PSEUDO", LIEF::assembly::powerpc::OPCODE::LWAT_CSNE_PSEUDO)
.value("PPCLdFixedAddr", LIEF::assembly::powerpc::OPCODE::PPCLdFixedAddr)
.value("PSUBI", LIEF::assembly::powerpc::OPCODE::PSUBI)
.value("RLWIMIbm", LIEF::assembly::powerpc::OPCODE::RLWIMIbm)
@@ -515,50 +526,39 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("ATOMIC_CMP_SWAP_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I32)
.value("ATOMIC_CMP_SWAP_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I64)
.value("ATOMIC_CMP_SWAP_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_CMP_SWAP_I8)
.value("ATOMIC_LOAD_ADD_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I16)
.value("ATOMIC_LOAD_ADD_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I32)
.value("ATOMIC_LOAD_ADD", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD)
.value("ATOMIC_LOAD_ADD_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I64)
.value("ATOMIC_LOAD_ADD_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_I8)
.value("ATOMIC_LOAD_AND_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I16)
.value("ATOMIC_LOAD_AND_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I32)
.value("ATOMIC_LOAD_ADD_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_ADD_NOWP)
.value("ATOMIC_LOAD_AND", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND)
.value("ATOMIC_LOAD_AND_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I64)
.value("ATOMIC_LOAD_AND_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_I8)
.value("ATOMIC_LOAD_MAX_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I16)
.value("ATOMIC_LOAD_MAX_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I32)
.value("ATOMIC_LOAD_AND_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_AND_NOWP)
.value("ATOMIC_LOAD_MAX", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX)
.value("ATOMIC_LOAD_MAX_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I64)
.value("ATOMIC_LOAD_MAX_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_I8)
.value("ATOMIC_LOAD_MIN_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I16)
.value("ATOMIC_LOAD_MIN_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I32)
.value("ATOMIC_LOAD_MAX_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MAX_NOWP)
.value("ATOMIC_LOAD_MIN", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN)
.value("ATOMIC_LOAD_MIN_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I64)
.value("ATOMIC_LOAD_MIN_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_I8)
.value("ATOMIC_LOAD_NAND_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I16)
.value("ATOMIC_LOAD_NAND_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I32)
.value("ATOMIC_LOAD_MIN_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_MIN_NOWP)
.value("ATOMIC_LOAD_NAND", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND)
.value("ATOMIC_LOAD_NAND_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I64)
.value("ATOMIC_LOAD_NAND_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_I8)
.value("ATOMIC_LOAD_OR_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I16)
.value("ATOMIC_LOAD_OR_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I32)
.value("ATOMIC_LOAD_NAND_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_NAND_NOWP)
.value("ATOMIC_LOAD_OR", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR)
.value("ATOMIC_LOAD_OR_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I64)
.value("ATOMIC_LOAD_OR_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_I8)
.value("ATOMIC_LOAD_SUB_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I16)
.value("ATOMIC_LOAD_SUB_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I32)
.value("ATOMIC_LOAD_OR_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_OR_NOWP)
.value("ATOMIC_LOAD_SUB", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB)
.value("ATOMIC_LOAD_SUB_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I64)
.value("ATOMIC_LOAD_SUB_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_I8)
.value("ATOMIC_LOAD_UMAX_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I16)
.value("ATOMIC_LOAD_UMAX_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I32)
.value("ATOMIC_LOAD_SUB_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_SUB_NOWP)
.value("ATOMIC_LOAD_UMAX", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX)
.value("ATOMIC_LOAD_UMAX_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I64)
.value("ATOMIC_LOAD_UMAX_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_I8)
.value("ATOMIC_LOAD_UMIN_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I16)
.value("ATOMIC_LOAD_UMIN_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I32)
.value("ATOMIC_LOAD_UMAX_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMAX_NOWP)
.value("ATOMIC_LOAD_UMIN", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN)
.value("ATOMIC_LOAD_UMIN_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I64)
.value("ATOMIC_LOAD_UMIN_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_I8)
.value("ATOMIC_LOAD_XOR_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I16)
.value("ATOMIC_LOAD_XOR_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I32)
.value("ATOMIC_LOAD_UMIN_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_UMIN_NOWP)
.value("ATOMIC_LOAD_XOR", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR)
.value("ATOMIC_LOAD_XOR_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I64)
.value("ATOMIC_LOAD_XOR_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_I8)
.value("ATOMIC_SWAP_I16", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I16)
.value("ATOMIC_SWAP_I32", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I32)
.value("ATOMIC_LOAD_XOR_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_LOAD_XOR_NOWP)
.value("ATOMIC_SWAP", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP)
.value("ATOMIC_SWAP_I64", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I64)
.value("ATOMIC_SWAP_I8", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_I8)
.value("ATOMIC_SWAP_NOWP", LIEF::assembly::powerpc::OPCODE::ATOMIC_SWAP_NOWP)
.value("ATTN", LIEF::assembly::powerpc::OPCODE::ATTN)
.value("B", LIEF::assembly::powerpc::OPCODE::B)
.value("BA", LIEF::assembly::powerpc::OPCODE::BA)
@@ -656,6 +656,8 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("BDZp", LIEF::assembly::powerpc::OPCODE::BDZp)
.value("BL", LIEF::assembly::powerpc::OPCODE::BL)
.value("BL8", LIEF::assembly::powerpc::OPCODE::BL8)
.value("BL8_LDinto_toc", LIEF::assembly::powerpc::OPCODE::BL8_LDinto_toc)
.value("BL8_LDinto_toc_RM", LIEF::assembly::powerpc::OPCODE::BL8_LDinto_toc_RM)
.value("BL8_NOP", LIEF::assembly::powerpc::OPCODE::BL8_NOP)
.value("BL8_NOP_RM", LIEF::assembly::powerpc::OPCODE::BL8_NOP_RM)
.value("BL8_NOP_TLS", LIEF::assembly::powerpc::OPCODE::BL8_NOP_TLS)
@@ -674,6 +676,8 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("BLR", LIEF::assembly::powerpc::OPCODE::BLR)
.value("BLR8", LIEF::assembly::powerpc::OPCODE::BLR8)
.value("BLRL", LIEF::assembly::powerpc::OPCODE::BLRL)
.value("BL_LWZinto_toc", LIEF::assembly::powerpc::OPCODE::BL_LWZinto_toc)
.value("BL_LWZinto_toc_RM", LIEF::assembly::powerpc::OPCODE::BL_LWZinto_toc_RM)
.value("BL_NOP", LIEF::assembly::powerpc::OPCODE::BL_NOP)
.value("BL_NOP_RM", LIEF::assembly::powerpc::OPCODE::BL_NOP_RM)
.value("BL_RM", LIEF::assembly::powerpc::OPCODE::BL_RM)
@@ -901,12 +905,12 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("DSUB_rec", LIEF::assembly::powerpc::OPCODE::DSUB_rec)
.value("DTSTDC", LIEF::assembly::powerpc::OPCODE::DTSTDC)
.value("DTSTDCQ", LIEF::assembly::powerpc::OPCODE::DTSTDCQ)
.value("DTSTDG", LIEF::assembly::powerpc::OPCODE::DTSTDG)
.value("DTSTDGQ", LIEF::assembly::powerpc::OPCODE::DTSTDGQ)
.value("DTSTDG", LIEF::assembly::powerpc::OPCODE::DTSTDG);
opcodes.value("DTSTDGQ", LIEF::assembly::powerpc::OPCODE::DTSTDGQ)
.value("DTSTEX", LIEF::assembly::powerpc::OPCODE::DTSTEX)
.value("DTSTEXQ", LIEF::assembly::powerpc::OPCODE::DTSTEXQ)
.value("DTSTSF", LIEF::assembly::powerpc::OPCODE::DTSTSF);
opcodes.value("DTSTSFI", LIEF::assembly::powerpc::OPCODE::DTSTSFI)
.value("DTSTSF", LIEF::assembly::powerpc::OPCODE::DTSTSF)
.value("DTSTSFI", LIEF::assembly::powerpc::OPCODE::DTSTSFI)
.value("DTSTSFIQ", LIEF::assembly::powerpc::OPCODE::DTSTSFIQ)
.value("DTSTSFQ", LIEF::assembly::powerpc::OPCODE::DTSTSFQ)
.value("DXEX", LIEF::assembly::powerpc::OPCODE::DXEX)
@@ -1201,12 +1205,12 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("FABSS_rec", LIEF::assembly::powerpc::OPCODE::FABSS_rec)
.value("FADD", LIEF::assembly::powerpc::OPCODE::FADD)
.value("FADDS", LIEF::assembly::powerpc::OPCODE::FADDS)
.value("FADDS_rec", LIEF::assembly::powerpc::OPCODE::FADDS_rec)
.value("FADD_rec", LIEF::assembly::powerpc::OPCODE::FADD_rec)
.value("FADDS_rec", LIEF::assembly::powerpc::OPCODE::FADDS_rec);
opcodes.value("FADD_rec", LIEF::assembly::powerpc::OPCODE::FADD_rec)
.value("FADDrtz", LIEF::assembly::powerpc::OPCODE::FADDrtz)
.value("FCFID", LIEF::assembly::powerpc::OPCODE::FCFID)
.value("FCFIDS", LIEF::assembly::powerpc::OPCODE::FCFIDS);
opcodes.value("FCFIDS_rec", LIEF::assembly::powerpc::OPCODE::FCFIDS_rec)
.value("FCFIDS", LIEF::assembly::powerpc::OPCODE::FCFIDS)
.value("FCFIDS_rec", LIEF::assembly::powerpc::OPCODE::FCFIDS_rec)
.value("FCFIDU", LIEF::assembly::powerpc::OPCODE::FCFIDU)
.value("FCFIDUS", LIEF::assembly::powerpc::OPCODE::FCFIDUS)
.value("FCFIDUS_rec", LIEF::assembly::powerpc::OPCODE::FCFIDUS_rec)
@@ -1362,7 +1366,7 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("LDARX", LIEF::assembly::powerpc::OPCODE::LDARX)
.value("LDARXL", LIEF::assembly::powerpc::OPCODE::LDARXL)
.value("LDAT", LIEF::assembly::powerpc::OPCODE::LDAT)
.value("LDAT_PSEUDO", LIEF::assembly::powerpc::OPCODE::LDAT_PSEUDO)
.value("LDAT_CSNE", LIEF::assembly::powerpc::OPCODE::LDAT_CSNE)
.value("LDBRX", LIEF::assembly::powerpc::OPCODE::LDBRX)
.value("LDCIX", LIEF::assembly::powerpc::OPCODE::LDCIX)
.value("LDU", LIEF::assembly::powerpc::OPCODE::LDU)
@@ -1441,7 +1445,7 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("LWARX", LIEF::assembly::powerpc::OPCODE::LWARX)
.value("LWARXL", LIEF::assembly::powerpc::OPCODE::LWARXL)
.value("LWAT", LIEF::assembly::powerpc::OPCODE::LWAT)
.value("LWAT_PSEUDO", LIEF::assembly::powerpc::OPCODE::LWAT_PSEUDO)
.value("LWAT_CSNE", LIEF::assembly::powerpc::OPCODE::LWAT_CSNE)
.value("LWAUX", LIEF::assembly::powerpc::OPCODE::LWAUX)
.value("LWAX", LIEF::assembly::powerpc::OPCODE::LWAX)
.value("LWAXTLS", LIEF::assembly::powerpc::OPCODE::LWAXTLS)
@@ -1501,12 +1505,12 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("MADDLD", LIEF::assembly::powerpc::OPCODE::MADDLD)
.value("MADDLD8", LIEF::assembly::powerpc::OPCODE::MADDLD8)
.value("MBAR", LIEF::assembly::powerpc::OPCODE::MBAR)
.value("MCRF", LIEF::assembly::powerpc::OPCODE::MCRF)
.value("MCRFS", LIEF::assembly::powerpc::OPCODE::MCRFS)
.value("MCRF", LIEF::assembly::powerpc::OPCODE::MCRF);
opcodes.value("MCRFS", LIEF::assembly::powerpc::OPCODE::MCRFS)
.value("MCRXRX", LIEF::assembly::powerpc::OPCODE::MCRXRX)
.value("MFBHRBE", LIEF::assembly::powerpc::OPCODE::MFBHRBE)
.value("MFCR", LIEF::assembly::powerpc::OPCODE::MFCR);
opcodes.value("MFCR8", LIEF::assembly::powerpc::OPCODE::MFCR8)
.value("MFCR", LIEF::assembly::powerpc::OPCODE::MFCR)
.value("MFCR8", LIEF::assembly::powerpc::OPCODE::MFCR8)
.value("MFCTR", LIEF::assembly::powerpc::OPCODE::MFCTR)
.value("MFCTR8", LIEF::assembly::powerpc::OPCODE::MFCTR8)
.value("MFDCR", LIEF::assembly::powerpc::OPCODE::MFDCR)
@@ -1543,6 +1547,8 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("MODSW", LIEF::assembly::powerpc::OPCODE::MODSW)
.value("MODUD", LIEF::assembly::powerpc::OPCODE::MODUD)
.value("MODUW", LIEF::assembly::powerpc::OPCODE::MODUW)
.value("MSGSNDP", LIEF::assembly::powerpc::OPCODE::MSGSNDP)
.value("MSGSNDP8", LIEF::assembly::powerpc::OPCODE::MSGSNDP8)
.value("MSGSYNC", LIEF::assembly::powerpc::OPCODE::MSGSYNC)
.value("MSYNC", LIEF::assembly::powerpc::OPCODE::MSYNC)
.value("MTCRF", LIEF::assembly::powerpc::OPCODE::MTCRF)
@@ -1799,14 +1805,14 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("PMXVI8GER4SPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4SPP)
.value("PMXVI8GER4W", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4W)
.value("PMXVI8GER4WPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4WPP)
.value("PMXVI8GER4WSPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4WSPP)
.value("POPCNTB", LIEF::assembly::powerpc::OPCODE::POPCNTB)
.value("PMXVI8GER4WSPP", LIEF::assembly::powerpc::OPCODE::PMXVI8GER4WSPP);
opcodes.value("POPCNTB", LIEF::assembly::powerpc::OPCODE::POPCNTB)
.value("POPCNTB8", LIEF::assembly::powerpc::OPCODE::POPCNTB8)
.value("POPCNTD", LIEF::assembly::powerpc::OPCODE::POPCNTD)
.value("POPCNTW", LIEF::assembly::powerpc::OPCODE::POPCNTW)
.value("PPC32GOT", LIEF::assembly::powerpc::OPCODE::PPC32GOT)
.value("PPC32PICGOT", LIEF::assembly::powerpc::OPCODE::PPC32PICGOT);
opcodes.value("PREPARE_PROBED_ALLOCA_32", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_32)
.value("PPC32PICGOT", LIEF::assembly::powerpc::OPCODE::PPC32PICGOT)
.value("PREPARE_PROBED_ALLOCA_32", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_32)
.value("PREPARE_PROBED_ALLOCA_64", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_64)
.value("PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)
.value("PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", LIEF::assembly::powerpc::OPCODE::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64)
@@ -2099,14 +2105,14 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("STXVRHX", LIEF::assembly::powerpc::OPCODE::STXVRHX)
.value("STXVRL", LIEF::assembly::powerpc::OPCODE::STXVRL)
.value("STXVRLL", LIEF::assembly::powerpc::OPCODE::STXVRLL)
.value("STXVRWX", LIEF::assembly::powerpc::OPCODE::STXVRWX)
.value("STXVW4X", LIEF::assembly::powerpc::OPCODE::STXVW4X)
.value("STXVRWX", LIEF::assembly::powerpc::OPCODE::STXVRWX);
opcodes.value("STXVW4X", LIEF::assembly::powerpc::OPCODE::STXVW4X)
.value("STXVX", LIEF::assembly::powerpc::OPCODE::STXVX)
.value("SUBF", LIEF::assembly::powerpc::OPCODE::SUBF)
.value("SUBF8", LIEF::assembly::powerpc::OPCODE::SUBF8)
.value("SUBF8O", LIEF::assembly::powerpc::OPCODE::SUBF8O)
.value("SUBF8O_rec", LIEF::assembly::powerpc::OPCODE::SUBF8O_rec);
opcodes.value("SUBF8_rec", LIEF::assembly::powerpc::OPCODE::SUBF8_rec)
.value("SUBF8O_rec", LIEF::assembly::powerpc::OPCODE::SUBF8O_rec)
.value("SUBF8_rec", LIEF::assembly::powerpc::OPCODE::SUBF8_rec)
.value("SUBFC", LIEF::assembly::powerpc::OPCODE::SUBFC)
.value("SUBFC8", LIEF::assembly::powerpc::OPCODE::SUBFC8)
.value("SUBFC8O", LIEF::assembly::powerpc::OPCODE::SUBFC8O)
@@ -2399,14 +2405,14 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("VMAXSW", LIEF::assembly::powerpc::OPCODE::VMAXSW)
.value("VMAXUB", LIEF::assembly::powerpc::OPCODE::VMAXUB)
.value("VMAXUD", LIEF::assembly::powerpc::OPCODE::VMAXUD)
.value("VMAXUH", LIEF::assembly::powerpc::OPCODE::VMAXUH)
.value("VMAXUW", LIEF::assembly::powerpc::OPCODE::VMAXUW)
.value("VMAXUH", LIEF::assembly::powerpc::OPCODE::VMAXUH);
opcodes.value("VMAXUW", LIEF::assembly::powerpc::OPCODE::VMAXUW)
.value("VMHADDSHS", LIEF::assembly::powerpc::OPCODE::VMHADDSHS)
.value("VMHRADDSHS", LIEF::assembly::powerpc::OPCODE::VMHRADDSHS)
.value("VMINFP", LIEF::assembly::powerpc::OPCODE::VMINFP)
.value("VMINSB", LIEF::assembly::powerpc::OPCODE::VMINSB)
.value("VMINSD", LIEF::assembly::powerpc::OPCODE::VMINSD);
opcodes.value("VMINSH", LIEF::assembly::powerpc::OPCODE::VMINSH)
.value("VMINSD", LIEF::assembly::powerpc::OPCODE::VMINSD)
.value("VMINSH", LIEF::assembly::powerpc::OPCODE::VMINSH)
.value("VMINSW", LIEF::assembly::powerpc::OPCODE::VMINSW)
.value("VMINUB", LIEF::assembly::powerpc::OPCODE::VMINUB)
.value("VMINUD", LIEF::assembly::powerpc::OPCODE::VMINUD)
@@ -2699,14 +2705,14 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("XSMINCQP", LIEF::assembly::powerpc::OPCODE::XSMINCQP)
.value("XSMINDP", LIEF::assembly::powerpc::OPCODE::XSMINDP)
.value("XSMINJDP", LIEF::assembly::powerpc::OPCODE::XSMINJDP)
.value("XSMSUBADP", LIEF::assembly::powerpc::OPCODE::XSMSUBADP)
.value("XSMSUBASP", LIEF::assembly::powerpc::OPCODE::XSMSUBASP)
.value("XSMSUBADP", LIEF::assembly::powerpc::OPCODE::XSMSUBADP);
opcodes.value("XSMSUBASP", LIEF::assembly::powerpc::OPCODE::XSMSUBASP)
.value("XSMSUBMDP", LIEF::assembly::powerpc::OPCODE::XSMSUBMDP)
.value("XSMSUBMSP", LIEF::assembly::powerpc::OPCODE::XSMSUBMSP)
.value("XSMSUBQP", LIEF::assembly::powerpc::OPCODE::XSMSUBQP)
.value("XSMSUBQPO", LIEF::assembly::powerpc::OPCODE::XSMSUBQPO)
.value("XSMULDP", LIEF::assembly::powerpc::OPCODE::XSMULDP);
opcodes.value("XSMULQP", LIEF::assembly::powerpc::OPCODE::XSMULQP)
.value("XSMULDP", LIEF::assembly::powerpc::OPCODE::XSMULDP)
.value("XSMULQP", LIEF::assembly::powerpc::OPCODE::XSMULQP)
.value("XSMULQPO", LIEF::assembly::powerpc::OPCODE::XSMULQPO)
.value("XSMULSP", LIEF::assembly::powerpc::OPCODE::XSMULSP)
.value("XSNABSDP", LIEF::assembly::powerpc::OPCODE::XSNABSDP)
@@ -2999,8 +3005,8 @@ void create<LIEF::assembly::powerpc::OPCODE>(nb::module_& m) {
.value("gBCLA", LIEF::assembly::powerpc::OPCODE::gBCLA)
.value("gBCLAat", LIEF::assembly::powerpc::OPCODE::gBCLAat)
.value("gBCLR", LIEF::assembly::powerpc::OPCODE::gBCLR)
.value("gBCLRL", LIEF::assembly::powerpc::OPCODE::gBCLRL)
.value("gBCLat", LIEF::assembly::powerpc::OPCODE::gBCLat)
.value("gBCLRL", LIEF::assembly::powerpc::OPCODE::gBCLRL);
opcodes.value("gBCLat", LIEF::assembly::powerpc::OPCODE::gBCLat)
.value("gBCat", LIEF::assembly::powerpc::OPCODE::gBCat)
.value("INSTRUCTION_LIST_END", LIEF::assembly::powerpc::OPCODE::INSTRUCTION_LIST_END)
;
api/python/src/asm/riscv/pyOpcode.cpp
+1079 -417
View File
File diff suppressed because it is too large Load Diff
api/python/src/asm/riscv/pyRegister.cpp
+130 -13
View File
@@ -18,6 +18,14 @@ void create<LIEF::assembly::riscv::REG>(nb::module_& m) {
.value("VXRM", LIEF::assembly::riscv::REG::VXRM)
.value("VXSAT", LIEF::assembly::riscv::REG::VXSAT)
.value("DUMMY_REG_PAIR_WITH_X0", LIEF::assembly::riscv::REG::DUMMY_REG_PAIR_WITH_X0)
.value("M0", LIEF::assembly::riscv::REG::M0)
.value("M1", LIEF::assembly::riscv::REG::M1)
.value("M2", LIEF::assembly::riscv::REG::M2)
.value("M3", LIEF::assembly::riscv::REG::M3)
.value("M4", LIEF::assembly::riscv::REG::M4)
.value("M5", LIEF::assembly::riscv::REG::M5)
.value("M6", LIEF::assembly::riscv::REG::M6)
.value("M7", LIEF::assembly::riscv::REG::M7)
.value("T0", LIEF::assembly::riscv::REG::T0)
.value("T1", LIEF::assembly::riscv::REG::T1)
.value("T2", LIEF::assembly::riscv::REG::T2)
@@ -291,6 +299,70 @@ void create<LIEF::assembly::riscv::REG>(nb::module_& m) {
.value("X29_W", LIEF::assembly::riscv::REG::X29_W)
.value("X30_W", LIEF::assembly::riscv::REG::X30_W)
.value("X31_W", LIEF::assembly::riscv::REG::X31_W)
.value("X0_Y", LIEF::assembly::riscv::REG::X0_Y)
.value("X1_Y", LIEF::assembly::riscv::REG::X1_Y)
.value("X2_Y", LIEF::assembly::riscv::REG::X2_Y)
.value("X3_Y", LIEF::assembly::riscv::REG::X3_Y)
.value("X4_Y", LIEF::assembly::riscv::REG::X4_Y)
.value("X5_Y", LIEF::assembly::riscv::REG::X5_Y)
.value("X6_Y", LIEF::assembly::riscv::REG::X6_Y);
reg.value("X7_Y", LIEF::assembly::riscv::REG::X7_Y)
.value("X8_Y", LIEF::assembly::riscv::REG::X8_Y)
.value("X9_Y", LIEF::assembly::riscv::REG::X9_Y)
.value("X10_Y", LIEF::assembly::riscv::REG::X10_Y)
.value("X11_Y", LIEF::assembly::riscv::REG::X11_Y)
.value("X12_Y", LIEF::assembly::riscv::REG::X12_Y)
.value("X13_Y", LIEF::assembly::riscv::REG::X13_Y)
.value("X14_Y", LIEF::assembly::riscv::REG::X14_Y)
.value("X15_Y", LIEF::assembly::riscv::REG::X15_Y)
.value("X16_Y", LIEF::assembly::riscv::REG::X16_Y)
.value("X17_Y", LIEF::assembly::riscv::REG::X17_Y)
.value("X18_Y", LIEF::assembly::riscv::REG::X18_Y)
.value("X19_Y", LIEF::assembly::riscv::REG::X19_Y)
.value("X20_Y", LIEF::assembly::riscv::REG::X20_Y)
.value("X21_Y", LIEF::assembly::riscv::REG::X21_Y)
.value("X22_Y", LIEF::assembly::riscv::REG::X22_Y)
.value("X23_Y", LIEF::assembly::riscv::REG::X23_Y)
.value("X24_Y", LIEF::assembly::riscv::REG::X24_Y)
.value("X25_Y", LIEF::assembly::riscv::REG::X25_Y)
.value("X26_Y", LIEF::assembly::riscv::REG::X26_Y)
.value("X27_Y", LIEF::assembly::riscv::REG::X27_Y)
.value("X28_Y", LIEF::assembly::riscv::REG::X28_Y)
.value("X29_Y", LIEF::assembly::riscv::REG::X29_Y)
.value("X30_Y", LIEF::assembly::riscv::REG::X30_Y)
.value("X31_Y", LIEF::assembly::riscv::REG::X31_Y)
.value("F0_Q2", LIEF::assembly::riscv::REG::F0_Q2)
.value("F1_Q2", LIEF::assembly::riscv::REG::F1_Q2)
.value("F2_Q2", LIEF::assembly::riscv::REG::F2_Q2)
.value("F3_Q2", LIEF::assembly::riscv::REG::F3_Q2)
.value("F4_Q2", LIEF::assembly::riscv::REG::F4_Q2)
.value("F5_Q2", LIEF::assembly::riscv::REG::F5_Q2)
.value("F6_Q2", LIEF::assembly::riscv::REG::F6_Q2)
.value("F7_Q2", LIEF::assembly::riscv::REG::F7_Q2)
.value("F8_Q2", LIEF::assembly::riscv::REG::F8_Q2)
.value("F9_Q2", LIEF::assembly::riscv::REG::F9_Q2)
.value("F10_Q2", LIEF::assembly::riscv::REG::F10_Q2)
.value("F11_Q2", LIEF::assembly::riscv::REG::F11_Q2)
.value("F12_Q2", LIEF::assembly::riscv::REG::F12_Q2)
.value("F13_Q2", LIEF::assembly::riscv::REG::F13_Q2)
.value("F14_Q2", LIEF::assembly::riscv::REG::F14_Q2)
.value("F15_Q2", LIEF::assembly::riscv::REG::F15_Q2)
.value("F16_Q2", LIEF::assembly::riscv::REG::F16_Q2)
.value("F17_Q2", LIEF::assembly::riscv::REG::F17_Q2)
.value("F18_Q2", LIEF::assembly::riscv::REG::F18_Q2)
.value("F19_Q2", LIEF::assembly::riscv::REG::F19_Q2)
.value("F20_Q2", LIEF::assembly::riscv::REG::F20_Q2)
.value("F21_Q2", LIEF::assembly::riscv::REG::F21_Q2)
.value("F22_Q2", LIEF::assembly::riscv::REG::F22_Q2)
.value("F23_Q2", LIEF::assembly::riscv::REG::F23_Q2)
.value("F24_Q2", LIEF::assembly::riscv::REG::F24_Q2)
.value("F25_Q2", LIEF::assembly::riscv::REG::F25_Q2)
.value("F26_Q2", LIEF::assembly::riscv::REG::F26_Q2)
.value("F27_Q2", LIEF::assembly::riscv::REG::F27_Q2)
.value("F28_Q2", LIEF::assembly::riscv::REG::F28_Q2)
.value("F29_Q2", LIEF::assembly::riscv::REG::F29_Q2)
.value("F30_Q2", LIEF::assembly::riscv::REG::F30_Q2)
.value("F31_Q2", LIEF::assembly::riscv::REG::F31_Q2)
.value("V0M2", LIEF::assembly::riscv::REG::V0M2)
.value("V0M4", LIEF::assembly::riscv::REG::V0M4)
.value("V0M8", LIEF::assembly::riscv::REG::V0M8)
@@ -305,8 +377,8 @@ void create<LIEF::assembly::riscv::REG>(nb::module_& m) {
.value("V12M2", LIEF::assembly::riscv::REG::V12M2)
.value("V12M4", LIEF::assembly::riscv::REG::V12M4)
.value("V14M2", LIEF::assembly::riscv::REG::V14M2)
.value("V16M2", LIEF::assembly::riscv::REG::V16M2);
reg.value("V16M4", LIEF::assembly::riscv::REG::V16M4)
.value("V16M2", LIEF::assembly::riscv::REG::V16M2)
.value("V16M4", LIEF::assembly::riscv::REG::V16M4)
.value("V16M8", LIEF::assembly::riscv::REG::V16M8)
.value("V18M2", LIEF::assembly::riscv::REG::V18M2)
.value("V20M2", LIEF::assembly::riscv::REG::V20M2)
@@ -533,8 +605,8 @@ void create<LIEF::assembly::riscv::REG>(nb::module_& m) {
.value("V3_V4_V5_V6_V7_V8_V9", LIEF::assembly::riscv::REG::V3_V4_V5_V6_V7_V8_V9)
.value("V4_V5_V6_V7_V8_V9_V10", LIEF::assembly::riscv::REG::V4_V5_V6_V7_V8_V9_V10)
.value("V5_V6_V7_V8_V9_V10_V11", LIEF::assembly::riscv::REG::V5_V6_V7_V8_V9_V10_V11)
.value("V6_V7_V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10_V11_V12)
.value("V7_V8_V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11_V12_V13)
.value("V6_V7_V8_V9_V10_V11_V12", LIEF::assembly::riscv::REG::V6_V7_V8_V9_V10_V11_V12);
reg.value("V7_V8_V9_V10_V11_V12_V13", LIEF::assembly::riscv::REG::V7_V8_V9_V10_V11_V12_V13)
.value("V8_V9_V10_V11_V12_V13_V14", LIEF::assembly::riscv::REG::V8_V9_V10_V11_V12_V13_V14)
.value("V9_V10_V11_V12_V13_V14_V15", LIEF::assembly::riscv::REG::V9_V10_V11_V12_V13_V14_V15)
.value("V10_V11_V12_V13_V14_V15_V16", LIEF::assembly::riscv::REG::V10_V11_V12_V13_V14_V15_V16)
@@ -898,20 +970,23 @@ void create<LIEF::assembly::riscv::SYSREG>(nb::module_& m) {
.value("dpc", LIEF::assembly::riscv::SYSREG::dpc)
.value("dscratch", LIEF::assembly::riscv::SYSREG::dscratch)
.value("dscratch1", LIEF::assembly::riscv::SYSREG::dscratch1)
.value("qc_mmcr", LIEF::assembly::riscv::SYSREG::qc_mmcr)
.value("aif_matp", LIEF::assembly::riscv::SYSREG::aif_matp)
.value("qc_mntvec", LIEF::assembly::riscv::SYSREG::qc_mntvec)
.value("qc_mstktopaddr", LIEF::assembly::riscv::SYSREG::qc_mstktopaddr)
.value("qc_mstkbottomaddr", LIEF::assembly::riscv::SYSREG::qc_mstkbottomaddr)
.value("qc_mthreadptr", LIEF::assembly::riscv::SYSREG::qc_mthreadptr)
.value("qc_mcause", LIEF::assembly::riscv::SYSREG::qc_mcause)
.value("qc_mwpstartaddr0", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr0)
.value("aif_minstmask", LIEF::assembly::riscv::SYSREG::aif_minstmask)
.value("aif_minstmatch", LIEF::assembly::riscv::SYSREG::aif_minstmatch)
.value("aif_cache_invalidate", LIEF::assembly::riscv::SYSREG::aif_cache_invalidate)
.value("qc_mwpstartaddr1", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr1)
.value("qc_mwpstartaddr2", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr2)
.value("qc_mwpstartaddr3", LIEF::assembly::riscv::SYSREG::qc_mwpstartaddr3)
.value("aif_menable_shadows", LIEF::assembly::riscv::SYSREG::aif_menable_shadows)
.value("aif_excl_mode", LIEF::assembly::riscv::SYSREG::aif_excl_mode)
.value("qc_mwpendaddr0", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr0)
.value("qc_mwpendaddr1", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr1)
.value("aif_mbusaddr", LIEF::assembly::riscv::SYSREG::aif_mbusaddr)
.value("qc_mwpendaddr2", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr2)
.value("qc_mwpendaddr3", LIEF::assembly::riscv::SYSREG::qc_mwpendaddr3)
.value("aif_mcache_control", LIEF::assembly::riscv::SYSREG::aif_mcache_control)
.value("qc_mclicip0", LIEF::assembly::riscv::SYSREG::qc_mclicip0)
.value("qc_mclicip1", LIEF::assembly::riscv::SYSREG::qc_mclicip1)
.value("qc_mclicip2", LIEF::assembly::riscv::SYSREG::qc_mclicip2)
@@ -921,13 +996,44 @@ void create<LIEF::assembly::riscv::SYSREG>(nb::module_& m) {
.value("qc_mclicip6", LIEF::assembly::riscv::SYSREG::qc_mclicip6)
.value("qc_mclicip7", LIEF::assembly::riscv::SYSREG::qc_mclicip7)
.value("qc_mclicie0", LIEF::assembly::riscv::SYSREG::qc_mclicie0)
.value("qc_mclicie1", LIEF::assembly::riscv::SYSREG::qc_mclicie1)
.value("aif_evict_sw", LIEF::assembly::riscv::SYSREG::aif_evict_sw)
.value("qc_mclicie2", LIEF::assembly::riscv::SYSREG::qc_mclicie2)
.value("qc_mclicie3", LIEF::assembly::riscv::SYSREG::qc_mclicie3)
.value("aif_flush_sw", LIEF::assembly::riscv::SYSREG::aif_flush_sw)
.value("qc_mclicie4", LIEF::assembly::riscv::SYSREG::qc_mclicie4)
.value("qc_mclicie5", LIEF::assembly::riscv::SYSREG::qc_mclicie5)
.value("aif_lock_sw", LIEF::assembly::riscv::SYSREG::aif_lock_sw)
.value("qc_mclicie6", LIEF::assembly::riscv::SYSREG::qc_mclicie6)
.value("qc_mclicie7", LIEF::assembly::riscv::SYSREG::qc_mclicie7)
.value("aif_unlock_sw", LIEF::assembly::riscv::SYSREG::aif_unlock_sw)
.value("aif_tensor_reduce", LIEF::assembly::riscv::SYSREG::aif_tensor_reduce)
.value("aif_tensor_fma", LIEF::assembly::riscv::SYSREG::aif_tensor_fma)
.value("aif_tensor_conv_size", LIEF::assembly::riscv::SYSREG::aif_tensor_conv_size)
.value("aif_tensor_conv_ctrl", LIEF::assembly::riscv::SYSREG::aif_tensor_conv_ctrl)
.value("aif_tensor_coop", LIEF::assembly::riscv::SYSREG::aif_tensor_coop)
.value("aif_tensor_mask", LIEF::assembly::riscv::SYSREG::aif_tensor_mask)
.value("aif_tensor_quant", LIEF::assembly::riscv::SYSREG::aif_tensor_quant)
.value("aif_tex_send", LIEF::assembly::riscv::SYSREG::aif_tex_send)
.value("aif_tensor_error", LIEF::assembly::riscv::SYSREG::aif_tensor_error)
.value("aif_ucache_control", LIEF::assembly::riscv::SYSREG::aif_ucache_control)
.value("aif_prefetch_va", LIEF::assembly::riscv::SYSREG::aif_prefetch_va)
.value("aif_flb", LIEF::assembly::riscv::SYSREG::aif_flb)
.value("aif_fcc", LIEF::assembly::riscv::SYSREG::aif_fcc)
.value("aif_stall", LIEF::assembly::riscv::SYSREG::aif_stall)
.value("aif_tensor_wait", LIEF::assembly::riscv::SYSREG::aif_tensor_wait)
.value("aif_tensor_load", LIEF::assembly::riscv::SYSREG::aif_tensor_load)
.value("aif_gsc_progress", LIEF::assembly::riscv::SYSREG::aif_gsc_progress)
.value("aif_tensor_load_l2", LIEF::assembly::riscv::SYSREG::aif_tensor_load_l2)
.value("aif_tensor_store", LIEF::assembly::riscv::SYSREG::aif_tensor_store)
.value("aif_evict_va", LIEF::assembly::riscv::SYSREG::aif_evict_va)
.value("aif_flush_va", LIEF::assembly::riscv::SYSREG::aif_flush_va)
.value("aif_validation0", LIEF::assembly::riscv::SYSREG::aif_validation0)
.value("aif_validation1", LIEF::assembly::riscv::SYSREG::aif_validation1)
.value("aif_validation2", LIEF::assembly::riscv::SYSREG::aif_validation2)
.value("aif_validation3", LIEF::assembly::riscv::SYSREG::aif_validation3)
.value("aif_lock_va", LIEF::assembly::riscv::SYSREG::aif_lock_va)
.value("aif_unlock_va", LIEF::assembly::riscv::SYSREG::aif_unlock_va)
.value("aif_portctrl0", LIEF::assembly::riscv::SYSREG::aif_portctrl0)
.value("aif_portctrl1", LIEF::assembly::riscv::SYSREG::aif_portctrl1)
.value("aif_portctrl2", LIEF::assembly::riscv::SYSREG::aif_portctrl2)
.value("aif_portctrl3", LIEF::assembly::riscv::SYSREG::aif_portctrl3)
.value("mcycle", LIEF::assembly::riscv::SYSREG::mcycle)
.value("minstret", LIEF::assembly::riscv::SYSREG::minstret)
.value("mhpmcounter3", LIEF::assembly::riscv::SYSREG::mhpmcounter3)
@@ -1089,6 +1195,16 @@ void create<LIEF::assembly::riscv::SYSREG>(nb::module_& m) {
.value("hpmcounter29h", LIEF::assembly::riscv::SYSREG::hpmcounter29h)
.value("hpmcounter30h", LIEF::assembly::riscv::SYSREG::hpmcounter30h)
.value("hpmcounter31h", LIEF::assembly::riscv::SYSREG::hpmcounter31h)
.value("aif_fccnb", LIEF::assembly::riscv::SYSREG::aif_fccnb)
.value("aif_porthead0", LIEF::assembly::riscv::SYSREG::aif_porthead0)
.value("aif_porthead1", LIEF::assembly::riscv::SYSREG::aif_porthead1)
.value("aif_porthead2", LIEF::assembly::riscv::SYSREG::aif_porthead2)
.value("aif_porthead3", LIEF::assembly::riscv::SYSREG::aif_porthead3)
.value("aif_portheadnb0", LIEF::assembly::riscv::SYSREG::aif_portheadnb0)
.value("aif_portheadnb1", LIEF::assembly::riscv::SYSREG::aif_portheadnb1)
.value("aif_portheadnb2", LIEF::assembly::riscv::SYSREG::aif_portheadnb2)
.value("aif_portheadnb3", LIEF::assembly::riscv::SYSREG::aif_portheadnb3)
.value("aif_hartid", LIEF::assembly::riscv::SYSREG::aif_hartid)
.value("scountovf", LIEF::assembly::riscv::SYSREG::scountovf)
.value("stopi", LIEF::assembly::riscv::SYSREG::stopi)
.value("hgeip", LIEF::assembly::riscv::SYSREG::hgeip)
@@ -1099,6 +1215,7 @@ void create<LIEF::assembly::riscv::SYSREG>(nb::module_& m) {
.value("mhartid", LIEF::assembly::riscv::SYSREG::mhartid)
.value("mconfigptr", LIEF::assembly::riscv::SYSREG::mconfigptr)
.value("mtopi", LIEF::assembly::riscv::SYSREG::mtopi)
.value("aif_dcache_debug", LIEF::assembly::riscv::SYSREG::aif_dcache_debug)
.value("NUM_TARGET_SYSREGS", LIEF::assembly::riscv::SYSREG::NUM_TARGET_SYSREGS)
;
}
api/python/src/asm/x86/pyOpcode.cpp
+456 -321
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File diff suppressed because it is too large Load Diff
api/rust/crates/lief/src/assembly/aarch64/opcodes.rs
+9163 -9049
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File diff suppressed because it is too large Load Diff
api/rust/crates/lief/src/assembly/aarch64/registers.rs
+23 -39
View File
@@ -2412,10 +2412,8 @@ pub enum SysReg {
APDAKeyHi_EL1,
APDBKeyLo_EL1,
APDBKeyHi_EL1,
TPMIN0_EL1,
TPMAX0_EL1,
TPMIN1_EL1,
TPMAX1_EL1,
TPCR0_EL1,
TPCR1_EL1,
APGAKeyLo_EL1,
APGAKeyHi_EL1,
GCSCR_EL1,
@@ -2695,10 +2693,8 @@ pub enum SysReg {
CSSELR_EL1,
CTR_EL0,
DCZID_EL0,
TPMIN0_EL0,
TPMAX0_EL0,
TPMIN1_EL0,
TPMAX1_EL0,
TPCR0_EL0,
TPCR1_EL0,
RNDR,
RNDRRS,
GCSPR_EL0,
@@ -2904,10 +2900,8 @@ pub enum SysReg {
LDSTT_EL2,
VNCR_EL2,
VNCCR_EL2,
TPMIN0_EL2,
TPMAX0_EL2,
TPMIN1_EL2,
TPMAX1_EL2,
TPCR0_EL2,
TPCR1_EL2,
HDBSSBR_EL2,
HDBSSPROD_EL2,
HACDBSBR_EL2,
@@ -3079,8 +3073,6 @@ pub enum SysReg {
MPAMVPM5_EL2,
MPAMVPM6_EL2,
MPAMVPM7_EL2,
MPAMVIDCR_EL2,
MPAMVIDSR_EL2,
MECID_P0_EL2,
MECID_A0_EL2,
MECID_P1_EL2,
@@ -3092,6 +3084,8 @@ pub enum SysReg {
RVBAR_EL2,
RMR_EL2,
VDISR_EL2,
ICH_PPI_HVIR0_EL2,
ICH_PPI_HVIR1_EL2,
ICH_AP0R0_EL2,
ICH_AP0R1_EL2,
ICH_AP0R2_EL2,
@@ -3229,10 +3223,8 @@ pub enum SysReg {
DPOTBR0_EL12,
DPOTBR1_EL12,
LDSTT_EL12,
TPMIN0_EL12,
TPMAX0_EL12,
TPMIN1_EL12,
TPMAX1_EL12,
TPCR0_EL12,
TPCR1_EL12,
GCSCR_EL12,
GCSPR_EL12,
TCRMASK_EL12,
@@ -3345,6 +3337,7 @@ pub enum SysReg {
CPTR_EL3,
FGWTE3_EL3,
ZCR_EL3,
SCR2_EL3,
SMCR_EL3,
MDCR_EL3,
TTBR0_EL3,
@@ -3412,7 +3405,6 @@ pub enum SysReg {
MPAM3_EL3,
MPAMCTL_EL3,
MPAMBW3_EL3,
MPAMVIDSR_EL3,
MECID_RL_A_EL3,
VBAR_EL3,
RVBAR_EL3,
@@ -4048,10 +4040,8 @@ impl From<u64> for SysReg {
49425 => SysReg::APDAKeyHi_EL1,
49426 => SysReg::APDBKeyLo_EL1,
49427 => SysReg::APDBKeyHi_EL1,
49428 => SysReg::TPMIN0_EL1,
49429 => SysReg::TPMAX0_EL1,
49430 => SysReg::TPMIN1_EL1,
49431 => SysReg::TPMAX1_EL1,
49428 => SysReg::TPCR0_EL1,
49429 => SysReg::TPCR1_EL1,
49432 => SysReg::APGAKeyLo_EL1,
49433 => SysReg::APGAKeyHi_EL1,
49448 => SysReg::GCSCR_EL1,
@@ -4331,10 +4321,8 @@ impl From<u64> for SysReg {
53248 => SysReg::CSSELR_EL1,
55297 => SysReg::CTR_EL0,
55303 => SysReg::DCZID_EL0,
55572 => SysReg::TPMIN0_EL0,
55573 => SysReg::TPMAX0_EL0,
55574 => SysReg::TPMIN1_EL0,
55575 => SysReg::TPMAX1_EL0,
55572 => SysReg::TPCR0_EL0,
55573 => SysReg::TPCR1_EL0,
55584 => SysReg::RNDR,
55585 => SysReg::RNDRRS,
55593 => SysReg::GCSPR_EL0,
@@ -4540,10 +4528,8 @@ impl From<u64> for SysReg {
57615 => SysReg::LDSTT_EL2,
57616 => SysReg::VNCR_EL2,
57617 => SysReg::VNCCR_EL2,
57620 => SysReg::TPMIN0_EL2,
57621 => SysReg::TPMAX0_EL2,
57622 => SysReg::TPMIN1_EL2,
57623 => SysReg::TPMAX1_EL2,
57620 => SysReg::TPCR0_EL2,
57621 => SysReg::TPCR1_EL2,
57626 => SysReg::HDBSSBR_EL2,
57627 => SysReg::HDBSSPROD_EL2,
57628 => SysReg::HACDBSBR_EL2,
@@ -4715,8 +4701,6 @@ impl From<u64> for SysReg {
58677 => SysReg::MPAMVPM5_EL2,
58678 => SysReg::MPAMVPM6_EL2,
58679 => SysReg::MPAMVPM7_EL2,
58680 => SysReg::MPAMVIDCR_EL2,
58681 => SysReg::MPAMVIDSR_EL2,
58688 => SysReg::MECID_P0_EL2,
58689 => SysReg::MECID_A0_EL2,
58690 => SysReg::MECID_P1_EL2,
@@ -4728,6 +4712,8 @@ impl From<u64> for SysReg {
58881 => SysReg::RVBAR_EL2,
58882 => SysReg::RMR_EL2,
58889 => SysReg::VDISR_EL2,
58936 => SysReg::ICH_PPI_HVIR0_EL2,
58937 => SysReg::ICH_PPI_HVIR1_EL2,
58944 => SysReg::ICH_AP0R0_EL2,
58945 => SysReg::ICH_AP0R1_EL2,
58946 => SysReg::ICH_AP0R2_EL2,
@@ -4865,10 +4851,8 @@ impl From<u64> for SysReg {
59654 => SysReg::DPOTBR0_EL12,
59655 => SysReg::DPOTBR1_EL12,
59663 => SysReg::LDSTT_EL12,
59668 => SysReg::TPMIN0_EL12,
59669 => SysReg::TPMAX0_EL12,
59670 => SysReg::TPMIN1_EL12,
59671 => SysReg::TPMAX1_EL12,
59668 => SysReg::TPCR0_EL12,
59669 => SysReg::TPCR1_EL12,
59688 => SysReg::GCSCR_EL12,
59689 => SysReg::GCSPR_EL12,
59706 => SysReg::TCRMASK_EL12,
@@ -4981,6 +4965,7 @@ impl From<u64> for SysReg {
61578 => SysReg::CPTR_EL3,
61581 => SysReg::FGWTE3_EL3,
61584 => SysReg::ZCR_EL3,
61586 => SysReg::SCR2_EL3,
61590 => SysReg::SMCR_EL3,
61593 => SysReg::MDCR_EL3,
61696 => SysReg::TTBR0_EL3,
@@ -5048,7 +5033,6 @@ impl From<u64> for SysReg {
62760 => SysReg::MPAM3_EL3,
62762 => SysReg::MPAMCTL_EL3,
62764 => SysReg::MPAMBW3_EL3,
62777 => SysReg::MPAMVIDSR_EL3,
62801 => SysReg::MECID_RL_A_EL3,
62976 => SysReg::VBAR_EL3,
62977 => SysReg::RVBAR_EL3,
@@ -5072,7 +5056,7 @@ impl From<u64> for SysReg {
65296 => SysReg::CNTPS_TVAL_EL1,
65297 => SysReg::CNTPS_CTL_EL1,
65298 => SysReg::CNTPS_CVAL_EL1,
1665 => SysReg::NUM_TARGET_SYSREGS,
1657 => SysReg::NUM_TARGET_SYSREGS,
_ => SysReg::UNKNOWN(value),
}
}
api/rust/crates/lief/src/assembly/arm/opcodes.rs
+4450 -4426
View File
File diff suppressed because it is too large Load Diff
api/rust/crates/lief/src/assembly/ebpf/opcodes.rs
+448 -424
View File
@@ -103,10 +103,12 @@ pub enum Opcode {
G_LOAD,
G_SEXTLOAD,
G_ZEXTLOAD,
G_FPEXTLOAD,
G_INDEXED_LOAD,
G_INDEXED_SEXTLOAD,
G_INDEXED_ZEXTLOAD,
G_STORE,
G_FPTRUNCSTORE,
G_INDEXED_STORE,
G_ATOMIC_CMPXCHG_WITH_SUCCESS,
G_ATOMIC_CMPXCHG,
@@ -127,6 +129,8 @@ pub enum Opcode {
G_ATOMICRMW_FMIN,
G_ATOMICRMW_FMAXIMUM,
G_ATOMICRMW_FMINIMUM,
G_ATOMICRMW_FMAXIMUMNUM,
G_ATOMICRMW_FMINIMUMNUM,
G_ATOMICRMW_UINC_WRAP,
G_ATOMICRMW_UDEC_WRAP,
G_ATOMICRMW_USUB_COND,
@@ -258,12 +262,14 @@ pub enum Opcode {
G_STEP_VECTOR,
G_VECTOR_COMPRESS,
G_CTTZ,
G_CTTZ_ZERO_UNDEF,
G_CTTZ_ZERO_POISON,
G_CTLZ,
G_CTLZ_ZERO_UNDEF,
G_CTLZ_ZERO_POISON,
G_CTLS,
G_CTPOP,
G_BSWAP,
G_BITREVERSE,
G_CLMUL,
G_FCEIL,
G_FCOS,
G_FSIN,
@@ -294,6 +300,8 @@ pub enum Opcode {
G_STRICT_FMA,
G_STRICT_FSQRT,
G_STRICT_FLDEXP,
G_STRICT_FCMP,
G_STRICT_FCMPS,
G_READ_REGISTER,
G_WRITE_REGISTER,
G_MEMCPY,
@@ -301,6 +309,7 @@ pub enum Opcode {
G_MEMMOVE,
G_MEMSET,
G_BZERO,
G_MEMSET_INLINE,
G_TRAP,
G_DEBUGTRAP,
G_UBSANTRAP,
@@ -327,7 +336,10 @@ pub enum Opcode {
ADJCALLSTACKUP,
FI_ri,
LDIMM64,
LOAD_STACK_ARG_PSEUDO,
MEMCPY,
STORE_STACK_ARG_IMM_PSEUDO,
STORE_STACK_ARG_PSEUDO,
Select,
Select_32,
Select_32_64,
@@ -633,428 +645,440 @@ impl From<u64> for Opcode {
99 => Opcode::G_LOAD,
100 => Opcode::G_SEXTLOAD,
101 => Opcode::G_ZEXTLOAD,
102 => Opcode::G_INDEXED_LOAD,
103 => Opcode::G_INDEXED_SEXTLOAD,
104 => Opcode::G_INDEXED_ZEXTLOAD,
105 => Opcode::G_STORE,
106 => Opcode::G_INDEXED_STORE,
107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS,
108 => Opcode::G_ATOMIC_CMPXCHG,
109 => Opcode::G_ATOMICRMW_XCHG,
110 => Opcode::G_ATOMICRMW_ADD,
111 => Opcode::G_ATOMICRMW_SUB,
112 => Opcode::G_ATOMICRMW_AND,
113 => Opcode::G_ATOMICRMW_NAND,
114 => Opcode::G_ATOMICRMW_OR,
115 => Opcode::G_ATOMICRMW_XOR,
116 => Opcode::G_ATOMICRMW_MAX,
117 => Opcode::G_ATOMICRMW_MIN,
118 => Opcode::G_ATOMICRMW_UMAX,
119 => Opcode::G_ATOMICRMW_UMIN,
120 => Opcode::G_ATOMICRMW_FADD,
121 => Opcode::G_ATOMICRMW_FSUB,
122 => Opcode::G_ATOMICRMW_FMAX,
123 => Opcode::G_ATOMICRMW_FMIN,
124 => Opcode::G_ATOMICRMW_FMAXIMUM,
125 => Opcode::G_ATOMICRMW_FMINIMUM,
126 => Opcode::G_ATOMICRMW_UINC_WRAP,
127 => Opcode::G_ATOMICRMW_UDEC_WRAP,
128 => Opcode::G_ATOMICRMW_USUB_COND,
129 => Opcode::G_ATOMICRMW_USUB_SAT,
130 => Opcode::G_FENCE,
131 => Opcode::G_PREFETCH,
132 => Opcode::G_BRCOND,
133 => Opcode::G_BRINDIRECT,
134 => Opcode::G_INVOKE_REGION_START,
135 => Opcode::G_INTRINSIC,
136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS,
137 => Opcode::G_INTRINSIC_CONVERGENT,
138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
139 => Opcode::G_ANYEXT,
140 => Opcode::G_TRUNC,
141 => Opcode::G_TRUNC_SSAT_S,
142 => Opcode::G_TRUNC_SSAT_U,
143 => Opcode::G_TRUNC_USAT_U,
144 => Opcode::G_CONSTANT,
145 => Opcode::G_FCONSTANT,
146 => Opcode::G_VASTART,
147 => Opcode::G_VAARG,
148 => Opcode::G_SEXT,
149 => Opcode::G_SEXT_INREG,
150 => Opcode::G_ZEXT,
151 => Opcode::G_SHL,
152 => Opcode::G_LSHR,
153 => Opcode::G_ASHR,
154 => Opcode::G_FSHL,
155 => Opcode::G_FSHR,
156 => Opcode::G_ROTR,
157 => Opcode::G_ROTL,
158 => Opcode::G_ICMP,
159 => Opcode::G_FCMP,
160 => Opcode::G_SCMP,
161 => Opcode::G_UCMP,
162 => Opcode::G_SELECT,
163 => Opcode::G_UADDO,
164 => Opcode::G_UADDE,
165 => Opcode::G_USUBO,
166 => Opcode::G_USUBE,
167 => Opcode::G_SADDO,
168 => Opcode::G_SADDE,
169 => Opcode::G_SSUBO,
170 => Opcode::G_SSUBE,
171 => Opcode::G_UMULO,
172 => Opcode::G_SMULO,
173 => Opcode::G_UMULH,
174 => Opcode::G_SMULH,
175 => Opcode::G_UADDSAT,
176 => Opcode::G_SADDSAT,
177 => Opcode::G_USUBSAT,
178 => Opcode::G_SSUBSAT,
179 => Opcode::G_USHLSAT,
180 => Opcode::G_SSHLSAT,
181 => Opcode::G_SMULFIX,
182 => Opcode::G_UMULFIX,
183 => Opcode::G_SMULFIXSAT,
184 => Opcode::G_UMULFIXSAT,
185 => Opcode::G_SDIVFIX,
186 => Opcode::G_UDIVFIX,
187 => Opcode::G_SDIVFIXSAT,
188 => Opcode::G_UDIVFIXSAT,
189 => Opcode::G_FADD,
190 => Opcode::G_FSUB,
191 => Opcode::G_FMUL,
192 => Opcode::G_FMA,
193 => Opcode::G_FMAD,
194 => Opcode::G_FDIV,
195 => Opcode::G_FREM,
196 => Opcode::G_FMODF,
197 => Opcode::G_FPOW,
198 => Opcode::G_FPOWI,
199 => Opcode::G_FEXP,
200 => Opcode::G_FEXP2,
201 => Opcode::G_FEXP10,
202 => Opcode::G_FLOG,
203 => Opcode::G_FLOG2,
204 => Opcode::G_FLOG10,
205 => Opcode::G_FLDEXP,
206 => Opcode::G_FFREXP,
207 => Opcode::G_FNEG,
208 => Opcode::G_FPEXT,
209 => Opcode::G_FPTRUNC,
210 => Opcode::G_FPTOSI,
211 => Opcode::G_FPTOUI,
212 => Opcode::G_SITOFP,
213 => Opcode::G_UITOFP,
214 => Opcode::G_FPTOSI_SAT,
215 => Opcode::G_FPTOUI_SAT,
216 => Opcode::G_FABS,
217 => Opcode::G_FCOPYSIGN,
218 => Opcode::G_IS_FPCLASS,
219 => Opcode::G_FCANONICALIZE,
220 => Opcode::G_FMINNUM,
221 => Opcode::G_FMAXNUM,
222 => Opcode::G_FMINNUM_IEEE,
223 => Opcode::G_FMAXNUM_IEEE,
224 => Opcode::G_FMINIMUM,
225 => Opcode::G_FMAXIMUM,
226 => Opcode::G_FMINIMUMNUM,
227 => Opcode::G_FMAXIMUMNUM,
228 => Opcode::G_GET_FPENV,
229 => Opcode::G_SET_FPENV,
230 => Opcode::G_RESET_FPENV,
231 => Opcode::G_GET_FPMODE,
232 => Opcode::G_SET_FPMODE,
233 => Opcode::G_RESET_FPMODE,
234 => Opcode::G_GET_ROUNDING,
235 => Opcode::G_SET_ROUNDING,
236 => Opcode::G_PTR_ADD,
237 => Opcode::G_PTRMASK,
238 => Opcode::G_SMIN,
239 => Opcode::G_SMAX,
240 => Opcode::G_UMIN,
241 => Opcode::G_UMAX,
242 => Opcode::G_ABS,
243 => Opcode::G_LROUND,
244 => Opcode::G_LLROUND,
245 => Opcode::G_BR,
246 => Opcode::G_BRJT,
247 => Opcode::G_VSCALE,
248 => Opcode::G_INSERT_SUBVECTOR,
249 => Opcode::G_EXTRACT_SUBVECTOR,
250 => Opcode::G_INSERT_VECTOR_ELT,
251 => Opcode::G_EXTRACT_VECTOR_ELT,
252 => Opcode::G_SHUFFLE_VECTOR,
253 => Opcode::G_SPLAT_VECTOR,
254 => Opcode::G_STEP_VECTOR,
255 => Opcode::G_VECTOR_COMPRESS,
256 => Opcode::G_CTTZ,
257 => Opcode::G_CTTZ_ZERO_UNDEF,
258 => Opcode::G_CTLZ,
259 => Opcode::G_CTLZ_ZERO_UNDEF,
260 => Opcode::G_CTPOP,
261 => Opcode::G_BSWAP,
262 => Opcode::G_BITREVERSE,
263 => Opcode::G_FCEIL,
264 => Opcode::G_FCOS,
265 => Opcode::G_FSIN,
266 => Opcode::G_FSINCOS,
267 => Opcode::G_FTAN,
268 => Opcode::G_FACOS,
269 => Opcode::G_FASIN,
270 => Opcode::G_FATAN,
271 => Opcode::G_FATAN2,
272 => Opcode::G_FCOSH,
273 => Opcode::G_FSINH,
274 => Opcode::G_FTANH,
275 => Opcode::G_FSQRT,
276 => Opcode::G_FFLOOR,
277 => Opcode::G_FRINT,
278 => Opcode::G_FNEARBYINT,
279 => Opcode::G_ADDRSPACE_CAST,
280 => Opcode::G_BLOCK_ADDR,
281 => Opcode::G_JUMP_TABLE,
282 => Opcode::G_DYN_STACKALLOC,
283 => Opcode::G_STACKSAVE,
284 => Opcode::G_STACKRESTORE,
285 => Opcode::G_STRICT_FADD,
286 => Opcode::G_STRICT_FSUB,
287 => Opcode::G_STRICT_FMUL,
288 => Opcode::G_STRICT_FDIV,
289 => Opcode::G_STRICT_FREM,
290 => Opcode::G_STRICT_FMA,
291 => Opcode::G_STRICT_FSQRT,
292 => Opcode::G_STRICT_FLDEXP,
293 => Opcode::G_READ_REGISTER,
294 => Opcode::G_WRITE_REGISTER,
295 => Opcode::G_MEMCPY,
296 => Opcode::G_MEMCPY_INLINE,
297 => Opcode::G_MEMMOVE,
298 => Opcode::G_MEMSET,
299 => Opcode::G_BZERO,
300 => Opcode::G_TRAP,
301 => Opcode::G_DEBUGTRAP,
302 => Opcode::G_UBSANTRAP,
303 => Opcode::G_VECREDUCE_SEQ_FADD,
304 => Opcode::G_VECREDUCE_SEQ_FMUL,
305 => Opcode::G_VECREDUCE_FADD,
306 => Opcode::G_VECREDUCE_FMUL,
307 => Opcode::G_VECREDUCE_FMAX,
308 => Opcode::G_VECREDUCE_FMIN,
309 => Opcode::G_VECREDUCE_FMAXIMUM,
310 => Opcode::G_VECREDUCE_FMINIMUM,
311 => Opcode::G_VECREDUCE_ADD,
312 => Opcode::G_VECREDUCE_MUL,
313 => Opcode::G_VECREDUCE_AND,
314 => Opcode::G_VECREDUCE_OR,
315 => Opcode::G_VECREDUCE_XOR,
316 => Opcode::G_VECREDUCE_SMAX,
317 => Opcode::G_VECREDUCE_SMIN,
318 => Opcode::G_VECREDUCE_UMAX,
319 => Opcode::G_VECREDUCE_UMIN,
320 => Opcode::G_SBFX,
321 => Opcode::G_UBFX,
322 => Opcode::ADJCALLSTACKDOWN,
323 => Opcode::ADJCALLSTACKUP,
324 => Opcode::FI_ri,
325 => Opcode::LDIMM64,
326 => Opcode::MEMCPY,
327 => Opcode::Select,
328 => Opcode::Select_32,
329 => Opcode::Select_32_64,
330 => Opcode::Select_64_32,
331 => Opcode::Select_Ri,
332 => Opcode::Select_Ri_32,
333 => Opcode::Select_Ri_32_64,
334 => Opcode::Select_Ri_64_32,
335 => Opcode::ADDR_SPACE_CAST,
336 => Opcode::ADD_ri,
337 => Opcode::ADD_ri_32,
338 => Opcode::ADD_rr,
339 => Opcode::ADD_rr_32,
340 => Opcode::AND_ri,
341 => Opcode::AND_ri_32,
342 => Opcode::AND_rr,
343 => Opcode::AND_rr_32,
344 => Opcode::BE16,
345 => Opcode::BE32,
346 => Opcode::BE64,
347 => Opcode::BSWAP16,
348 => Opcode::BSWAP32,
349 => Opcode::BSWAP64,
350 => Opcode::CMPXCHGD,
351 => Opcode::CMPXCHGW32,
352 => Opcode::CORE_LD32,
353 => Opcode::CORE_LD64,
354 => Opcode::CORE_SHIFT,
355 => Opcode::CORE_ST,
356 => Opcode::DIV_ri,
357 => Opcode::DIV_ri_32,
358 => Opcode::DIV_rr,
359 => Opcode::DIV_rr_32,
360 => Opcode::JAL,
361 => Opcode::JALX,
362 => Opcode::JCOND,
363 => Opcode::JEQ_ri,
364 => Opcode::JEQ_ri_32,
365 => Opcode::JEQ_rr,
366 => Opcode::JEQ_rr_32,
367 => Opcode::JMP,
368 => Opcode::JMPL,
369 => Opcode::JNE_ri,
370 => Opcode::JNE_ri_32,
371 => Opcode::JNE_rr,
372 => Opcode::JNE_rr_32,
373 => Opcode::JSET_ri,
374 => Opcode::JSET_ri_32,
375 => Opcode::JSET_rr,
376 => Opcode::JSET_rr_32,
377 => Opcode::JSGE_ri,
378 => Opcode::JSGE_ri_32,
379 => Opcode::JSGE_rr,
380 => Opcode::JSGE_rr_32,
381 => Opcode::JSGT_ri,
382 => Opcode::JSGT_ri_32,
383 => Opcode::JSGT_rr,
384 => Opcode::JSGT_rr_32,
385 => Opcode::JSLE_ri,
386 => Opcode::JSLE_ri_32,
387 => Opcode::JSLE_rr,
388 => Opcode::JSLE_rr_32,
389 => Opcode::JSLT_ri,
390 => Opcode::JSLT_ri_32,
391 => Opcode::JSLT_rr,
392 => Opcode::JSLT_rr_32,
393 => Opcode::JUGE_ri,
394 => Opcode::JUGE_ri_32,
395 => Opcode::JUGE_rr,
396 => Opcode::JUGE_rr_32,
397 => Opcode::JUGT_ri,
398 => Opcode::JUGT_ri_32,
399 => Opcode::JUGT_rr,
400 => Opcode::JUGT_rr_32,
401 => Opcode::JULE_ri,
402 => Opcode::JULE_ri_32,
403 => Opcode::JULE_rr,
404 => Opcode::JULE_rr_32,
405 => Opcode::JULT_ri,
406 => Opcode::JULT_ri_32,
407 => Opcode::JULT_rr,
408 => Opcode::JULT_rr_32,
409 => Opcode::JX,
410 => Opcode::LDB,
411 => Opcode::LDB32,
412 => Opcode::LDBACQ32,
413 => Opcode::LDBSX,
414 => Opcode::LDD,
415 => Opcode::LDDACQ,
416 => Opcode::LDH,
417 => Opcode::LDH32,
418 => Opcode::LDHACQ32,
419 => Opcode::LDHSX,
420 => Opcode::LDW,
421 => Opcode::LDW32,
422 => Opcode::LDWACQ32,
423 => Opcode::LDWSX,
424 => Opcode::LD_ABS_B,
425 => Opcode::LD_ABS_H,
426 => Opcode::LD_ABS_W,
427 => Opcode::LD_IND_B,
428 => Opcode::LD_IND_H,
429 => Opcode::LD_IND_W,
430 => Opcode::LD_imm64,
431 => Opcode::LD_pseudo,
432 => Opcode::LE16,
433 => Opcode::LE32,
434 => Opcode::LE64,
435 => Opcode::MOD_ri,
436 => Opcode::MOD_ri_32,
437 => Opcode::MOD_rr,
438 => Opcode::MOD_rr_32,
439 => Opcode::MOVSX_rr_16,
440 => Opcode::MOVSX_rr_32,
441 => Opcode::MOVSX_rr_32_16,
442 => Opcode::MOVSX_rr_32_8,
443 => Opcode::MOVSX_rr_8,
444 => Opcode::MOV_32_64,
445 => Opcode::MOV_ri,
446 => Opcode::MOV_ri_32,
447 => Opcode::MOV_rr,
448 => Opcode::MOV_rr_32,
449 => Opcode::MUL_ri,
450 => Opcode::MUL_ri_32,
451 => Opcode::MUL_rr,
452 => Opcode::MUL_rr_32,
453 => Opcode::NEG_32,
454 => Opcode::NEG_64,
455 => Opcode::NOP,
456 => Opcode::OR_ri,
457 => Opcode::OR_ri_32,
458 => Opcode::OR_rr,
459 => Opcode::OR_rr_32,
460 => Opcode::RET,
461 => Opcode::SDIV_ri,
462 => Opcode::SDIV_ri_32,
463 => Opcode::SDIV_rr,
464 => Opcode::SDIV_rr_32,
465 => Opcode::SLL_ri,
466 => Opcode::SLL_ri_32,
467 => Opcode::SLL_rr,
468 => Opcode::SLL_rr_32,
469 => Opcode::SMOD_ri,
470 => Opcode::SMOD_ri_32,
471 => Opcode::SMOD_rr,
472 => Opcode::SMOD_rr_32,
473 => Opcode::SRA_ri,
474 => Opcode::SRA_ri_32,
475 => Opcode::SRA_rr,
476 => Opcode::SRA_rr_32,
477 => Opcode::SRL_ri,
478 => Opcode::SRL_ri_32,
479 => Opcode::SRL_rr,
480 => Opcode::SRL_rr_32,
481 => Opcode::STB,
482 => Opcode::STB32,
483 => Opcode::STBREL32,
484 => Opcode::STB_imm,
485 => Opcode::STD,
486 => Opcode::STDREL,
487 => Opcode::STD_imm,
488 => Opcode::STH,
489 => Opcode::STH32,
490 => Opcode::STHREL32,
491 => Opcode::STH_imm,
492 => Opcode::STW,
493 => Opcode::STW32,
494 => Opcode::STWREL32,
495 => Opcode::STW_imm,
496 => Opcode::SUB_ri,
497 => Opcode::SUB_ri_32,
498 => Opcode::SUB_rr,
499 => Opcode::SUB_rr_32,
500 => Opcode::XADDD,
501 => Opcode::XADDW,
502 => Opcode::XADDW32,
503 => Opcode::XANDD,
504 => Opcode::XANDW32,
505 => Opcode::XCHGD,
506 => Opcode::XCHGW32,
507 => Opcode::XFADDD,
508 => Opcode::XFADDW32,
509 => Opcode::XFANDD,
510 => Opcode::XFANDW32,
511 => Opcode::XFORD,
512 => Opcode::XFORW32,
513 => Opcode::XFXORD,
514 => Opcode::XFXORW32,
515 => Opcode::XORD,
516 => Opcode::XORW32,
517 => Opcode::XOR_ri,
518 => Opcode::XOR_ri_32,
519 => Opcode::XOR_rr,
520 => Opcode::XOR_rr_32,
521 => Opcode::XXORD,
522 => Opcode::XXORW32,
523 => Opcode::INSTRUCTION_LIST_END,
102 => Opcode::G_FPEXTLOAD,
103 => Opcode::G_INDEXED_LOAD,
104 => Opcode::G_INDEXED_SEXTLOAD,
105 => Opcode::G_INDEXED_ZEXTLOAD,
106 => Opcode::G_STORE,
107 => Opcode::G_FPTRUNCSTORE,
108 => Opcode::G_INDEXED_STORE,
109 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS,
110 => Opcode::G_ATOMIC_CMPXCHG,
111 => Opcode::G_ATOMICRMW_XCHG,
112 => Opcode::G_ATOMICRMW_ADD,
113 => Opcode::G_ATOMICRMW_SUB,
114 => Opcode::G_ATOMICRMW_AND,
115 => Opcode::G_ATOMICRMW_NAND,
116 => Opcode::G_ATOMICRMW_OR,
117 => Opcode::G_ATOMICRMW_XOR,
118 => Opcode::G_ATOMICRMW_MAX,
119 => Opcode::G_ATOMICRMW_MIN,
120 => Opcode::G_ATOMICRMW_UMAX,
121 => Opcode::G_ATOMICRMW_UMIN,
122 => Opcode::G_ATOMICRMW_FADD,
123 => Opcode::G_ATOMICRMW_FSUB,
124 => Opcode::G_ATOMICRMW_FMAX,
125 => Opcode::G_ATOMICRMW_FMIN,
126 => Opcode::G_ATOMICRMW_FMAXIMUM,
127 => Opcode::G_ATOMICRMW_FMINIMUM,
128 => Opcode::G_ATOMICRMW_FMAXIMUMNUM,
129 => Opcode::G_ATOMICRMW_FMINIMUMNUM,
130 => Opcode::G_ATOMICRMW_UINC_WRAP,
131 => Opcode::G_ATOMICRMW_UDEC_WRAP,
132 => Opcode::G_ATOMICRMW_USUB_COND,
133 => Opcode::G_ATOMICRMW_USUB_SAT,
134 => Opcode::G_FENCE,
135 => Opcode::G_PREFETCH,
136 => Opcode::G_BRCOND,
137 => Opcode::G_BRINDIRECT,
138 => Opcode::G_INVOKE_REGION_START,
139 => Opcode::G_INTRINSIC,
140 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS,
141 => Opcode::G_INTRINSIC_CONVERGENT,
142 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
143 => Opcode::G_ANYEXT,
144 => Opcode::G_TRUNC,
145 => Opcode::G_TRUNC_SSAT_S,
146 => Opcode::G_TRUNC_SSAT_U,
147 => Opcode::G_TRUNC_USAT_U,
148 => Opcode::G_CONSTANT,
149 => Opcode::G_FCONSTANT,
150 => Opcode::G_VASTART,
151 => Opcode::G_VAARG,
152 => Opcode::G_SEXT,
153 => Opcode::G_SEXT_INREG,
154 => Opcode::G_ZEXT,
155 => Opcode::G_SHL,
156 => Opcode::G_LSHR,
157 => Opcode::G_ASHR,
158 => Opcode::G_FSHL,
159 => Opcode::G_FSHR,
160 => Opcode::G_ROTR,
161 => Opcode::G_ROTL,
162 => Opcode::G_ICMP,
163 => Opcode::G_FCMP,
164 => Opcode::G_SCMP,
165 => Opcode::G_UCMP,
166 => Opcode::G_SELECT,
167 => Opcode::G_UADDO,
168 => Opcode::G_UADDE,
169 => Opcode::G_USUBO,
170 => Opcode::G_USUBE,
171 => Opcode::G_SADDO,
172 => Opcode::G_SADDE,
173 => Opcode::G_SSUBO,
174 => Opcode::G_SSUBE,
175 => Opcode::G_UMULO,
176 => Opcode::G_SMULO,
177 => Opcode::G_UMULH,
178 => Opcode::G_SMULH,
179 => Opcode::G_UADDSAT,
180 => Opcode::G_SADDSAT,
181 => Opcode::G_USUBSAT,
182 => Opcode::G_SSUBSAT,
183 => Opcode::G_USHLSAT,
184 => Opcode::G_SSHLSAT,
185 => Opcode::G_SMULFIX,
186 => Opcode::G_UMULFIX,
187 => Opcode::G_SMULFIXSAT,
188 => Opcode::G_UMULFIXSAT,
189 => Opcode::G_SDIVFIX,
190 => Opcode::G_UDIVFIX,
191 => Opcode::G_SDIVFIXSAT,
192 => Opcode::G_UDIVFIXSAT,
193 => Opcode::G_FADD,
194 => Opcode::G_FSUB,
195 => Opcode::G_FMUL,
196 => Opcode::G_FMA,
197 => Opcode::G_FMAD,
198 => Opcode::G_FDIV,
199 => Opcode::G_FREM,
200 => Opcode::G_FMODF,
201 => Opcode::G_FPOW,
202 => Opcode::G_FPOWI,
203 => Opcode::G_FEXP,
204 => Opcode::G_FEXP2,
205 => Opcode::G_FEXP10,
206 => Opcode::G_FLOG,
207 => Opcode::G_FLOG2,
208 => Opcode::G_FLOG10,
209 => Opcode::G_FLDEXP,
210 => Opcode::G_FFREXP,
211 => Opcode::G_FNEG,
212 => Opcode::G_FPEXT,
213 => Opcode::G_FPTRUNC,
214 => Opcode::G_FPTOSI,
215 => Opcode::G_FPTOUI,
216 => Opcode::G_SITOFP,
217 => Opcode::G_UITOFP,
218 => Opcode::G_FPTOSI_SAT,
219 => Opcode::G_FPTOUI_SAT,
220 => Opcode::G_FABS,
221 => Opcode::G_FCOPYSIGN,
222 => Opcode::G_IS_FPCLASS,
223 => Opcode::G_FCANONICALIZE,
224 => Opcode::G_FMINNUM,
225 => Opcode::G_FMAXNUM,
226 => Opcode::G_FMINNUM_IEEE,
227 => Opcode::G_FMAXNUM_IEEE,
228 => Opcode::G_FMINIMUM,
229 => Opcode::G_FMAXIMUM,
230 => Opcode::G_FMINIMUMNUM,
231 => Opcode::G_FMAXIMUMNUM,
232 => Opcode::G_GET_FPENV,
233 => Opcode::G_SET_FPENV,
234 => Opcode::G_RESET_FPENV,
235 => Opcode::G_GET_FPMODE,
236 => Opcode::G_SET_FPMODE,
237 => Opcode::G_RESET_FPMODE,
238 => Opcode::G_GET_ROUNDING,
239 => Opcode::G_SET_ROUNDING,
240 => Opcode::G_PTR_ADD,
241 => Opcode::G_PTRMASK,
242 => Opcode::G_SMIN,
243 => Opcode::G_SMAX,
244 => Opcode::G_UMIN,
245 => Opcode::G_UMAX,
246 => Opcode::G_ABS,
247 => Opcode::G_LROUND,
248 => Opcode::G_LLROUND,
249 => Opcode::G_BR,
250 => Opcode::G_BRJT,
251 => Opcode::G_VSCALE,
252 => Opcode::G_INSERT_SUBVECTOR,
253 => Opcode::G_EXTRACT_SUBVECTOR,
254 => Opcode::G_INSERT_VECTOR_ELT,
255 => Opcode::G_EXTRACT_VECTOR_ELT,
256 => Opcode::G_SHUFFLE_VECTOR,
257 => Opcode::G_SPLAT_VECTOR,
258 => Opcode::G_STEP_VECTOR,
259 => Opcode::G_VECTOR_COMPRESS,
260 => Opcode::G_CTTZ,
261 => Opcode::G_CTTZ_ZERO_POISON,
262 => Opcode::G_CTLZ,
263 => Opcode::G_CTLZ_ZERO_POISON,
264 => Opcode::G_CTLS,
265 => Opcode::G_CTPOP,
266 => Opcode::G_BSWAP,
267 => Opcode::G_BITREVERSE,
268 => Opcode::G_CLMUL,
269 => Opcode::G_FCEIL,
270 => Opcode::G_FCOS,
271 => Opcode::G_FSIN,
272 => Opcode::G_FSINCOS,
273 => Opcode::G_FTAN,
274 => Opcode::G_FACOS,
275 => Opcode::G_FASIN,
276 => Opcode::G_FATAN,
277 => Opcode::G_FATAN2,
278 => Opcode::G_FCOSH,
279 => Opcode::G_FSINH,
280 => Opcode::G_FTANH,
281 => Opcode::G_FSQRT,
282 => Opcode::G_FFLOOR,
283 => Opcode::G_FRINT,
284 => Opcode::G_FNEARBYINT,
285 => Opcode::G_ADDRSPACE_CAST,
286 => Opcode::G_BLOCK_ADDR,
287 => Opcode::G_JUMP_TABLE,
288 => Opcode::G_DYN_STACKALLOC,
289 => Opcode::G_STACKSAVE,
290 => Opcode::G_STACKRESTORE,
291 => Opcode::G_STRICT_FADD,
292 => Opcode::G_STRICT_FSUB,
293 => Opcode::G_STRICT_FMUL,
294 => Opcode::G_STRICT_FDIV,
295 => Opcode::G_STRICT_FREM,
296 => Opcode::G_STRICT_FMA,
297 => Opcode::G_STRICT_FSQRT,
298 => Opcode::G_STRICT_FLDEXP,
299 => Opcode::G_STRICT_FCMP,
300 => Opcode::G_STRICT_FCMPS,
301 => Opcode::G_READ_REGISTER,
302 => Opcode::G_WRITE_REGISTER,
303 => Opcode::G_MEMCPY,
304 => Opcode::G_MEMCPY_INLINE,
305 => Opcode::G_MEMMOVE,
306 => Opcode::G_MEMSET,
307 => Opcode::G_BZERO,
308 => Opcode::G_MEMSET_INLINE,
309 => Opcode::G_TRAP,
310 => Opcode::G_DEBUGTRAP,
311 => Opcode::G_UBSANTRAP,
312 => Opcode::G_VECREDUCE_SEQ_FADD,
313 => Opcode::G_VECREDUCE_SEQ_FMUL,
314 => Opcode::G_VECREDUCE_FADD,
315 => Opcode::G_VECREDUCE_FMUL,
316 => Opcode::G_VECREDUCE_FMAX,
317 => Opcode::G_VECREDUCE_FMIN,
318 => Opcode::G_VECREDUCE_FMAXIMUM,
319 => Opcode::G_VECREDUCE_FMINIMUM,
320 => Opcode::G_VECREDUCE_ADD,
321 => Opcode::G_VECREDUCE_MUL,
322 => Opcode::G_VECREDUCE_AND,
323 => Opcode::G_VECREDUCE_OR,
324 => Opcode::G_VECREDUCE_XOR,
325 => Opcode::G_VECREDUCE_SMAX,
326 => Opcode::G_VECREDUCE_SMIN,
327 => Opcode::G_VECREDUCE_UMAX,
328 => Opcode::G_VECREDUCE_UMIN,
329 => Opcode::G_SBFX,
330 => Opcode::G_UBFX,
331 => Opcode::ADJCALLSTACKDOWN,
332 => Opcode::ADJCALLSTACKUP,
333 => Opcode::FI_ri,
334 => Opcode::LDIMM64,
335 => Opcode::LOAD_STACK_ARG_PSEUDO,
336 => Opcode::MEMCPY,
337 => Opcode::STORE_STACK_ARG_IMM_PSEUDO,
338 => Opcode::STORE_STACK_ARG_PSEUDO,
339 => Opcode::Select,
340 => Opcode::Select_32,
341 => Opcode::Select_32_64,
342 => Opcode::Select_64_32,
343 => Opcode::Select_Ri,
344 => Opcode::Select_Ri_32,
345 => Opcode::Select_Ri_32_64,
346 => Opcode::Select_Ri_64_32,
347 => Opcode::ADDR_SPACE_CAST,
348 => Opcode::ADD_ri,
349 => Opcode::ADD_ri_32,
350 => Opcode::ADD_rr,
351 => Opcode::ADD_rr_32,
352 => Opcode::AND_ri,
353 => Opcode::AND_ri_32,
354 => Opcode::AND_rr,
355 => Opcode::AND_rr_32,
356 => Opcode::BE16,
357 => Opcode::BE32,
358 => Opcode::BE64,
359 => Opcode::BSWAP16,
360 => Opcode::BSWAP32,
361 => Opcode::BSWAP64,
362 => Opcode::CMPXCHGD,
363 => Opcode::CMPXCHGW32,
364 => Opcode::CORE_LD32,
365 => Opcode::CORE_LD64,
366 => Opcode::CORE_SHIFT,
367 => Opcode::CORE_ST,
368 => Opcode::DIV_ri,
369 => Opcode::DIV_ri_32,
370 => Opcode::DIV_rr,
371 => Opcode::DIV_rr_32,
372 => Opcode::JAL,
373 => Opcode::JALX,
374 => Opcode::JCOND,
375 => Opcode::JEQ_ri,
376 => Opcode::JEQ_ri_32,
377 => Opcode::JEQ_rr,
378 => Opcode::JEQ_rr_32,
379 => Opcode::JMP,
380 => Opcode::JMPL,
381 => Opcode::JNE_ri,
382 => Opcode::JNE_ri_32,
383 => Opcode::JNE_rr,
384 => Opcode::JNE_rr_32,
385 => Opcode::JSET_ri,
386 => Opcode::JSET_ri_32,
387 => Opcode::JSET_rr,
388 => Opcode::JSET_rr_32,
389 => Opcode::JSGE_ri,
390 => Opcode::JSGE_ri_32,
391 => Opcode::JSGE_rr,
392 => Opcode::JSGE_rr_32,
393 => Opcode::JSGT_ri,
394 => Opcode::JSGT_ri_32,
395 => Opcode::JSGT_rr,
396 => Opcode::JSGT_rr_32,
397 => Opcode::JSLE_ri,
398 => Opcode::JSLE_ri_32,
399 => Opcode::JSLE_rr,
400 => Opcode::JSLE_rr_32,
401 => Opcode::JSLT_ri,
402 => Opcode::JSLT_ri_32,
403 => Opcode::JSLT_rr,
404 => Opcode::JSLT_rr_32,
405 => Opcode::JUGE_ri,
406 => Opcode::JUGE_ri_32,
407 => Opcode::JUGE_rr,
408 => Opcode::JUGE_rr_32,
409 => Opcode::JUGT_ri,
410 => Opcode::JUGT_ri_32,
411 => Opcode::JUGT_rr,
412 => Opcode::JUGT_rr_32,
413 => Opcode::JULE_ri,
414 => Opcode::JULE_ri_32,
415 => Opcode::JULE_rr,
416 => Opcode::JULE_rr_32,
417 => Opcode::JULT_ri,
418 => Opcode::JULT_ri_32,
419 => Opcode::JULT_rr,
420 => Opcode::JULT_rr_32,
421 => Opcode::JX,
422 => Opcode::LDB,
423 => Opcode::LDB32,
424 => Opcode::LDBACQ32,
425 => Opcode::LDBSX,
426 => Opcode::LDD,
427 => Opcode::LDDACQ,
428 => Opcode::LDH,
429 => Opcode::LDH32,
430 => Opcode::LDHACQ32,
431 => Opcode::LDHSX,
432 => Opcode::LDW,
433 => Opcode::LDW32,
434 => Opcode::LDWACQ32,
435 => Opcode::LDWSX,
436 => Opcode::LD_ABS_B,
437 => Opcode::LD_ABS_H,
438 => Opcode::LD_ABS_W,
439 => Opcode::LD_IND_B,
440 => Opcode::LD_IND_H,
441 => Opcode::LD_IND_W,
442 => Opcode::LD_imm64,
443 => Opcode::LD_pseudo,
444 => Opcode::LE16,
445 => Opcode::LE32,
446 => Opcode::LE64,
447 => Opcode::MOD_ri,
448 => Opcode::MOD_ri_32,
449 => Opcode::MOD_rr,
450 => Opcode::MOD_rr_32,
451 => Opcode::MOVSX_rr_16,
452 => Opcode::MOVSX_rr_32,
453 => Opcode::MOVSX_rr_32_16,
454 => Opcode::MOVSX_rr_32_8,
455 => Opcode::MOVSX_rr_8,
456 => Opcode::MOV_32_64,
457 => Opcode::MOV_ri,
458 => Opcode::MOV_ri_32,
459 => Opcode::MOV_rr,
460 => Opcode::MOV_rr_32,
461 => Opcode::MUL_ri,
462 => Opcode::MUL_ri_32,
463 => Opcode::MUL_rr,
464 => Opcode::MUL_rr_32,
465 => Opcode::NEG_32,
466 => Opcode::NEG_64,
467 => Opcode::NOP,
468 => Opcode::OR_ri,
469 => Opcode::OR_ri_32,
470 => Opcode::OR_rr,
471 => Opcode::OR_rr_32,
472 => Opcode::RET,
473 => Opcode::SDIV_ri,
474 => Opcode::SDIV_ri_32,
475 => Opcode::SDIV_rr,
476 => Opcode::SDIV_rr_32,
477 => Opcode::SLL_ri,
478 => Opcode::SLL_ri_32,
479 => Opcode::SLL_rr,
480 => Opcode::SLL_rr_32,
481 => Opcode::SMOD_ri,
482 => Opcode::SMOD_ri_32,
483 => Opcode::SMOD_rr,
484 => Opcode::SMOD_rr_32,
485 => Opcode::SRA_ri,
486 => Opcode::SRA_ri_32,
487 => Opcode::SRA_rr,
488 => Opcode::SRA_rr_32,
489 => Opcode::SRL_ri,
490 => Opcode::SRL_ri_32,
491 => Opcode::SRL_rr,
492 => Opcode::SRL_rr_32,
493 => Opcode::STB,
494 => Opcode::STB32,
495 => Opcode::STBREL32,
496 => Opcode::STB_imm,
497 => Opcode::STD,
498 => Opcode::STDREL,
499 => Opcode::STD_imm,
500 => Opcode::STH,
501 => Opcode::STH32,
502 => Opcode::STHREL32,
503 => Opcode::STH_imm,
504 => Opcode::STW,
505 => Opcode::STW32,
506 => Opcode::STWREL32,
507 => Opcode::STW_imm,
508 => Opcode::SUB_ri,
509 => Opcode::SUB_ri_32,
510 => Opcode::SUB_rr,
511 => Opcode::SUB_rr_32,
512 => Opcode::XADDD,
513 => Opcode::XADDW,
514 => Opcode::XADDW32,
515 => Opcode::XANDD,
516 => Opcode::XANDW32,
517 => Opcode::XCHGD,
518 => Opcode::XCHGW32,
519 => Opcode::XFADDD,
520 => Opcode::XFADDW32,
521 => Opcode::XFANDD,
522 => Opcode::XFANDW32,
523 => Opcode::XFORD,
524 => Opcode::XFORW32,
525 => Opcode::XFXORD,
526 => Opcode::XFXORW32,
527 => Opcode::XORD,
528 => Opcode::XORW32,
529 => Opcode::XOR_ri,
530 => Opcode::XOR_ri_32,
531 => Opcode::XOR_rr,
532 => Opcode::XOR_rr_32,
533 => Opcode::XXORD,
534 => Opcode::XXORW32,
535 => Opcode::INSTRUCTION_LIST_END,
_ => Opcode::UNKNOWN(value),
}
}
api/rust/crates/lief/src/assembly/mips/opcodes.rs
+2833 -2827
View File
File diff suppressed because it is too large Load Diff
api/rust/crates/lief/src/assembly/powerpc/opcodes.rs
+2846 -2834
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api/rust/crates/lief/src/assembly/riscv/opcodes.rs
+17647 -16323
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api/rust/crates/lief/src/assembly/riscv/registers.rs
+815 -581
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api/rust/crates/lief/src/assembly/x86/opcodes.rs
+22493 -22223
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doc/sphinx/changelog.md
+4
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@@ -108,6 +108,10 @@
an unpaired surrogate makes the conversion fail: the function now returns a
``result<std::string>``.
:Extended:
* Use LLVM ``23.x``
:Dependencies:
* Update nanobind to version ``3.0.1``
include/LIEF/asm/aarch64/opcodes.hpp
+9092 -9035
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include/LIEF/asm/aarch64/registers.hpp
+12 -20
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@@ -1527,10 +1527,8 @@ enum class SYSREG {
APDAKeyHi_EL1 = 49425,
APDBKeyLo_EL1 = 49426,
APDBKeyHi_EL1 = 49427,
TPMIN0_EL1 = 49428,
TPMAX0_EL1 = 49429,
TPMIN1_EL1 = 49430,
TPMAX1_EL1 = 49431,
TPCR0_EL1 = 49428,
TPCR1_EL1 = 49429,
APGAKeyLo_EL1 = 49432,
APGAKeyHi_EL1 = 49433,
GCSCR_EL1 = 49448,
@@ -1810,10 +1808,8 @@ enum class SYSREG {
CSSELR_EL1 = 53248,
CTR_EL0 = 55297,
DCZID_EL0 = 55303,
TPMIN0_EL0 = 55572,
TPMAX0_EL0 = 55573,
TPMIN1_EL0 = 55574,
TPMAX1_EL0 = 55575,
TPCR0_EL0 = 55572,
TPCR1_EL0 = 55573,
RNDR = 55584,
RNDRRS = 55585,
GCSPR_EL0 = 55593,
@@ -2019,10 +2015,8 @@ enum class SYSREG {
LDSTT_EL2 = 57615,
VNCR_EL2 = 57616,
VNCCR_EL2 = 57617,
TPMIN0_EL2 = 57620,
TPMAX0_EL2 = 57621,
TPMIN1_EL2 = 57622,
TPMAX1_EL2 = 57623,
TPCR0_EL2 = 57620,
TPCR1_EL2 = 57621,
HDBSSBR_EL2 = 57626,
HDBSSPROD_EL2 = 57627,
HACDBSBR_EL2 = 57628,
@@ -2194,8 +2188,6 @@ enum class SYSREG {
MPAMVPM5_EL2 = 58677,
MPAMVPM6_EL2 = 58678,
MPAMVPM7_EL2 = 58679,
MPAMVIDCR_EL2 = 58680,
MPAMVIDSR_EL2 = 58681,
MECID_P0_EL2 = 58688,
MECID_A0_EL2 = 58689,
MECID_P1_EL2 = 58690,
@@ -2207,6 +2199,8 @@ enum class SYSREG {
RVBAR_EL2 = 58881,
RMR_EL2 = 58882,
VDISR_EL2 = 58889,
ICH_PPI_HVIR0_EL2 = 58936,
ICH_PPI_HVIR1_EL2 = 58937,
ICH_AP0R0_EL2 = 58944,
ICH_AP0R1_EL2 = 58945,
ICH_AP0R2_EL2 = 58946,
@@ -2344,10 +2338,8 @@ enum class SYSREG {
DPOTBR0_EL12 = 59654,
DPOTBR1_EL12 = 59655,
LDSTT_EL12 = 59663,
TPMIN0_EL12 = 59668,
TPMAX0_EL12 = 59669,
TPMIN1_EL12 = 59670,
TPMAX1_EL12 = 59671,
TPCR0_EL12 = 59668,
TPCR1_EL12 = 59669,
GCSCR_EL12 = 59688,
GCSPR_EL12 = 59689,
TCRMASK_EL12 = 59706,
@@ -2460,6 +2452,7 @@ enum class SYSREG {
CPTR_EL3 = 61578,
FGWTE3_EL3 = 61581,
ZCR_EL3 = 61584,
SCR2_EL3 = 61586,
SMCR_EL3 = 61590,
MDCR_EL3 = 61593,
TTBR0_EL3 = 61696,
@@ -2527,7 +2520,6 @@ enum class SYSREG {
MPAM3_EL3 = 62760,
MPAMCTL_EL3 = 62762,
MPAMBW3_EL3 = 62764,
MPAMVIDSR_EL3 = 62777,
MECID_RL_A_EL3 = 62801,
VBAR_EL3 = 62976,
RVBAR_EL3 = 62977,
@@ -2551,7 +2543,7 @@ enum class SYSREG {
CNTPS_TVAL_EL1 = 65296,
CNTPS_CTL_EL1 = 65297,
CNTPS_CVAL_EL1 = 65298,
NUM_TARGET_SYSREGS = 1665,
NUM_TARGET_SYSREGS = 1657,
};
}
include/LIEF/asm/arm/opcodes.hpp
+4431 -4419
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include/LIEF/asm/ebpf/opcodes.hpp
+435 -423
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@@ -15,7 +15,7 @@
#ifndef LIEF_ASM_EBPF_OPCODE_H
#define LIEF_ASM_EBPF_OPCODE_H
/* Generated from LLVM: 22.1.8 */
/* Generated from LLVM: 23.1.3 */
namespace LIEF::assembly::ebpf {
@@ -122,428 +122,440 @@ enum class OPCODE {
G_LOAD = 99,
G_SEXTLOAD = 100,
G_ZEXTLOAD = 101,
G_INDEXED_LOAD = 102,
G_INDEXED_SEXTLOAD = 103,
G_INDEXED_ZEXTLOAD = 104,
G_STORE = 105,
G_INDEXED_STORE = 106,
G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107,
G_ATOMIC_CMPXCHG = 108,
G_ATOMICRMW_XCHG = 109,
G_ATOMICRMW_ADD = 110,
G_ATOMICRMW_SUB = 111,
G_ATOMICRMW_AND = 112,
G_ATOMICRMW_NAND = 113,
G_ATOMICRMW_OR = 114,
G_ATOMICRMW_XOR = 115,
G_ATOMICRMW_MAX = 116,
G_ATOMICRMW_MIN = 117,
G_ATOMICRMW_UMAX = 118,
G_ATOMICRMW_UMIN = 119,
G_ATOMICRMW_FADD = 120,
G_ATOMICRMW_FSUB = 121,
G_ATOMICRMW_FMAX = 122,
G_ATOMICRMW_FMIN = 123,
G_ATOMICRMW_FMAXIMUM = 124,
G_ATOMICRMW_FMINIMUM = 125,
G_ATOMICRMW_UINC_WRAP = 126,
G_ATOMICRMW_UDEC_WRAP = 127,
G_ATOMICRMW_USUB_COND = 128,
G_ATOMICRMW_USUB_SAT = 129,
G_FENCE = 130,
G_PREFETCH = 131,
G_BRCOND = 132,
G_BRINDIRECT = 133,
G_INVOKE_REGION_START = 134,
G_INTRINSIC = 135,
G_INTRINSIC_W_SIDE_EFFECTS = 136,
G_INTRINSIC_CONVERGENT = 137,
G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138,
G_ANYEXT = 139,
G_TRUNC = 140,
G_TRUNC_SSAT_S = 141,
G_TRUNC_SSAT_U = 142,
G_TRUNC_USAT_U = 143,
G_CONSTANT = 144,
G_FCONSTANT = 145,
G_VASTART = 146,
G_VAARG = 147,
G_SEXT = 148,
G_SEXT_INREG = 149,
G_ZEXT = 150,
G_SHL = 151,
G_LSHR = 152,
G_ASHR = 153,
G_FSHL = 154,
G_FSHR = 155,
G_ROTR = 156,
G_ROTL = 157,
G_ICMP = 158,
G_FCMP = 159,
G_SCMP = 160,
G_UCMP = 161,
G_SELECT = 162,
G_UADDO = 163,
G_UADDE = 164,
G_USUBO = 165,
G_USUBE = 166,
G_SADDO = 167,
G_SADDE = 168,
G_SSUBO = 169,
G_SSUBE = 170,
G_UMULO = 171,
G_SMULO = 172,
G_UMULH = 173,
G_SMULH = 174,
G_UADDSAT = 175,
G_SADDSAT = 176,
G_USUBSAT = 177,
G_SSUBSAT = 178,
G_USHLSAT = 179,
G_SSHLSAT = 180,
G_SMULFIX = 181,
G_UMULFIX = 182,
G_SMULFIXSAT = 183,
G_UMULFIXSAT = 184,
G_SDIVFIX = 185,
G_UDIVFIX = 186,
G_SDIVFIXSAT = 187,
G_UDIVFIXSAT = 188,
G_FADD = 189,
G_FSUB = 190,
G_FMUL = 191,
G_FMA = 192,
G_FMAD = 193,
G_FDIV = 194,
G_FREM = 195,
G_FMODF = 196,
G_FPOW = 197,
G_FPOWI = 198,
G_FEXP = 199,
G_FEXP2 = 200,
G_FEXP10 = 201,
G_FLOG = 202,
G_FLOG2 = 203,
G_FLOG10 = 204,
G_FLDEXP = 205,
G_FFREXP = 206,
G_FNEG = 207,
G_FPEXT = 208,
G_FPTRUNC = 209,
G_FPTOSI = 210,
G_FPTOUI = 211,
G_SITOFP = 212,
G_UITOFP = 213,
G_FPTOSI_SAT = 214,
G_FPTOUI_SAT = 215,
G_FABS = 216,
G_FCOPYSIGN = 217,
G_IS_FPCLASS = 218,
G_FCANONICALIZE = 219,
G_FMINNUM = 220,
G_FMAXNUM = 221,
G_FMINNUM_IEEE = 222,
G_FMAXNUM_IEEE = 223,
G_FMINIMUM = 224,
G_FMAXIMUM = 225,
G_FMINIMUMNUM = 226,
G_FMAXIMUMNUM = 227,
G_GET_FPENV = 228,
G_SET_FPENV = 229,
G_RESET_FPENV = 230,
G_GET_FPMODE = 231,
G_SET_FPMODE = 232,
G_RESET_FPMODE = 233,
G_GET_ROUNDING = 234,
G_SET_ROUNDING = 235,
G_PTR_ADD = 236,
G_PTRMASK = 237,
G_SMIN = 238,
G_SMAX = 239,
G_UMIN = 240,
G_UMAX = 241,
G_ABS = 242,
G_LROUND = 243,
G_LLROUND = 244,
G_BR = 245,
G_BRJT = 246,
G_VSCALE = 247,
G_INSERT_SUBVECTOR = 248,
G_EXTRACT_SUBVECTOR = 249,
G_INSERT_VECTOR_ELT = 250,
G_EXTRACT_VECTOR_ELT = 251,
G_SHUFFLE_VECTOR = 252,
G_SPLAT_VECTOR = 253,
G_STEP_VECTOR = 254,
G_VECTOR_COMPRESS = 255,
G_CTTZ = 256,
G_CTTZ_ZERO_UNDEF = 257,
G_CTLZ = 258,
G_CTLZ_ZERO_UNDEF = 259,
G_CTPOP = 260,
G_BSWAP = 261,
G_BITREVERSE = 262,
G_FCEIL = 263,
G_FCOS = 264,
G_FSIN = 265,
G_FSINCOS = 266,
G_FTAN = 267,
G_FACOS = 268,
G_FASIN = 269,
G_FATAN = 270,
G_FATAN2 = 271,
G_FCOSH = 272,
G_FSINH = 273,
G_FTANH = 274,
G_FSQRT = 275,
G_FFLOOR = 276,
G_FRINT = 277,
G_FNEARBYINT = 278,
G_ADDRSPACE_CAST = 279,
G_BLOCK_ADDR = 280,
G_JUMP_TABLE = 281,
G_DYN_STACKALLOC = 282,
G_STACKSAVE = 283,
G_STACKRESTORE = 284,
G_STRICT_FADD = 285,
G_STRICT_FSUB = 286,
G_STRICT_FMUL = 287,
G_STRICT_FDIV = 288,
G_STRICT_FREM = 289,
G_STRICT_FMA = 290,
G_STRICT_FSQRT = 291,
G_STRICT_FLDEXP = 292,
G_READ_REGISTER = 293,
G_WRITE_REGISTER = 294,
G_MEMCPY = 295,
G_MEMCPY_INLINE = 296,
G_MEMMOVE = 297,
G_MEMSET = 298,
G_BZERO = 299,
G_TRAP = 300,
G_DEBUGTRAP = 301,
G_UBSANTRAP = 302,
G_VECREDUCE_SEQ_FADD = 303,
G_VECREDUCE_SEQ_FMUL = 304,
G_VECREDUCE_FADD = 305,
G_VECREDUCE_FMUL = 306,
G_VECREDUCE_FMAX = 307,
G_VECREDUCE_FMIN = 308,
G_VECREDUCE_FMAXIMUM = 309,
G_VECREDUCE_FMINIMUM = 310,
G_VECREDUCE_ADD = 311,
G_VECREDUCE_MUL = 312,
G_VECREDUCE_AND = 313,
G_VECREDUCE_OR = 314,
G_VECREDUCE_XOR = 315,
G_VECREDUCE_SMAX = 316,
G_VECREDUCE_SMIN = 317,
G_VECREDUCE_UMAX = 318,
G_VECREDUCE_UMIN = 319,
G_SBFX = 320,
G_UBFX = 321,
ADJCALLSTACKDOWN = 322,
ADJCALLSTACKUP = 323,
FI_ri = 324,
LDIMM64 = 325,
MEMCPY = 326,
Select = 327,
Select_32 = 328,
Select_32_64 = 329,
Select_64_32 = 330,
Select_Ri = 331,
Select_Ri_32 = 332,
Select_Ri_32_64 = 333,
Select_Ri_64_32 = 334,
ADDR_SPACE_CAST = 335,
ADD_ri = 336,
ADD_ri_32 = 337,
ADD_rr = 338,
ADD_rr_32 = 339,
AND_ri = 340,
AND_ri_32 = 341,
AND_rr = 342,
AND_rr_32 = 343,
BE16 = 344,
BE32 = 345,
BE64 = 346,
BSWAP16 = 347,
BSWAP32 = 348,
BSWAP64 = 349,
CMPXCHGD = 350,
CMPXCHGW32 = 351,
CORE_LD32 = 352,
CORE_LD64 = 353,
CORE_SHIFT = 354,
CORE_ST = 355,
DIV_ri = 356,
DIV_ri_32 = 357,
DIV_rr = 358,
DIV_rr_32 = 359,
JAL = 360,
JALX = 361,
JCOND = 362,
JEQ_ri = 363,
JEQ_ri_32 = 364,
JEQ_rr = 365,
JEQ_rr_32 = 366,
JMP = 367,
JMPL = 368,
JNE_ri = 369,
JNE_ri_32 = 370,
JNE_rr = 371,
JNE_rr_32 = 372,
JSET_ri = 373,
JSET_ri_32 = 374,
JSET_rr = 375,
JSET_rr_32 = 376,
JSGE_ri = 377,
JSGE_ri_32 = 378,
JSGE_rr = 379,
JSGE_rr_32 = 380,
JSGT_ri = 381,
JSGT_ri_32 = 382,
JSGT_rr = 383,
JSGT_rr_32 = 384,
JSLE_ri = 385,
JSLE_ri_32 = 386,
JSLE_rr = 387,
JSLE_rr_32 = 388,
JSLT_ri = 389,
JSLT_ri_32 = 390,
JSLT_rr = 391,
JSLT_rr_32 = 392,
JUGE_ri = 393,
JUGE_ri_32 = 394,
JUGE_rr = 395,
JUGE_rr_32 = 396,
JUGT_ri = 397,
JUGT_ri_32 = 398,
JUGT_rr = 399,
JUGT_rr_32 = 400,
JULE_ri = 401,
JULE_ri_32 = 402,
JULE_rr = 403,
JULE_rr_32 = 404,
JULT_ri = 405,
JULT_ri_32 = 406,
JULT_rr = 407,
JULT_rr_32 = 408,
JX = 409,
LDB = 410,
LDB32 = 411,
LDBACQ32 = 412,
LDBSX = 413,
LDD = 414,
LDDACQ = 415,
LDH = 416,
LDH32 = 417,
LDHACQ32 = 418,
LDHSX = 419,
LDW = 420,
LDW32 = 421,
LDWACQ32 = 422,
LDWSX = 423,
LD_ABS_B = 424,
LD_ABS_H = 425,
LD_ABS_W = 426,
LD_IND_B = 427,
LD_IND_H = 428,
LD_IND_W = 429,
LD_imm64 = 430,
LD_pseudo = 431,
LE16 = 432,
LE32 = 433,
LE64 = 434,
MOD_ri = 435,
MOD_ri_32 = 436,
MOD_rr = 437,
MOD_rr_32 = 438,
MOVSX_rr_16 = 439,
MOVSX_rr_32 = 440,
MOVSX_rr_32_16 = 441,
MOVSX_rr_32_8 = 442,
MOVSX_rr_8 = 443,
MOV_32_64 = 444,
MOV_ri = 445,
MOV_ri_32 = 446,
MOV_rr = 447,
MOV_rr_32 = 448,
MUL_ri = 449,
MUL_ri_32 = 450,
MUL_rr = 451,
MUL_rr_32 = 452,
NEG_32 = 453,
NEG_64 = 454,
NOP = 455,
OR_ri = 456,
OR_ri_32 = 457,
OR_rr = 458,
OR_rr_32 = 459,
RET = 460,
SDIV_ri = 461,
SDIV_ri_32 = 462,
SDIV_rr = 463,
SDIV_rr_32 = 464,
SLL_ri = 465,
SLL_ri_32 = 466,
SLL_rr = 467,
SLL_rr_32 = 468,
SMOD_ri = 469,
SMOD_ri_32 = 470,
SMOD_rr = 471,
SMOD_rr_32 = 472,
SRA_ri = 473,
SRA_ri_32 = 474,
SRA_rr = 475,
SRA_rr_32 = 476,
SRL_ri = 477,
SRL_ri_32 = 478,
SRL_rr = 479,
SRL_rr_32 = 480,
STB = 481,
STB32 = 482,
STBREL32 = 483,
STB_imm = 484,
STD = 485,
STDREL = 486,
STD_imm = 487,
STH = 488,
STH32 = 489,
STHREL32 = 490,
STH_imm = 491,
STW = 492,
STW32 = 493,
STWREL32 = 494,
STW_imm = 495,
SUB_ri = 496,
SUB_ri_32 = 497,
SUB_rr = 498,
SUB_rr_32 = 499,
XADDD = 500,
XADDW = 501,
XADDW32 = 502,
XANDD = 503,
XANDW32 = 504,
XCHGD = 505,
XCHGW32 = 506,
XFADDD = 507,
XFADDW32 = 508,
XFANDD = 509,
XFANDW32 = 510,
XFORD = 511,
XFORW32 = 512,
XFXORD = 513,
XFXORW32 = 514,
XORD = 515,
XORW32 = 516,
XOR_ri = 517,
XOR_ri_32 = 518,
XOR_rr = 519,
XOR_rr_32 = 520,
XXORD = 521,
XXORW32 = 522,
INSTRUCTION_LIST_END = 523,
G_FPEXTLOAD = 102,
G_INDEXED_LOAD = 103,
G_INDEXED_SEXTLOAD = 104,
G_INDEXED_ZEXTLOAD = 105,
G_STORE = 106,
G_FPTRUNCSTORE = 107,
G_INDEXED_STORE = 108,
G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109,
G_ATOMIC_CMPXCHG = 110,
G_ATOMICRMW_XCHG = 111,
G_ATOMICRMW_ADD = 112,
G_ATOMICRMW_SUB = 113,
G_ATOMICRMW_AND = 114,
G_ATOMICRMW_NAND = 115,
G_ATOMICRMW_OR = 116,
G_ATOMICRMW_XOR = 117,
G_ATOMICRMW_MAX = 118,
G_ATOMICRMW_MIN = 119,
G_ATOMICRMW_UMAX = 120,
G_ATOMICRMW_UMIN = 121,
G_ATOMICRMW_FADD = 122,
G_ATOMICRMW_FSUB = 123,
G_ATOMICRMW_FMAX = 124,
G_ATOMICRMW_FMIN = 125,
G_ATOMICRMW_FMAXIMUM = 126,
G_ATOMICRMW_FMINIMUM = 127,
G_ATOMICRMW_FMAXIMUMNUM = 128,
G_ATOMICRMW_FMINIMUMNUM = 129,
G_ATOMICRMW_UINC_WRAP = 130,
G_ATOMICRMW_UDEC_WRAP = 131,
G_ATOMICRMW_USUB_COND = 132,
G_ATOMICRMW_USUB_SAT = 133,
G_FENCE = 134,
G_PREFETCH = 135,
G_BRCOND = 136,
G_BRINDIRECT = 137,
G_INVOKE_REGION_START = 138,
G_INTRINSIC = 139,
G_INTRINSIC_W_SIDE_EFFECTS = 140,
G_INTRINSIC_CONVERGENT = 141,
G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142,
G_ANYEXT = 143,
G_TRUNC = 144,
G_TRUNC_SSAT_S = 145,
G_TRUNC_SSAT_U = 146,
G_TRUNC_USAT_U = 147,
G_CONSTANT = 148,
G_FCONSTANT = 149,
G_VASTART = 150,
G_VAARG = 151,
G_SEXT = 152,
G_SEXT_INREG = 153,
G_ZEXT = 154,
G_SHL = 155,
G_LSHR = 156,
G_ASHR = 157,
G_FSHL = 158,
G_FSHR = 159,
G_ROTR = 160,
G_ROTL = 161,
G_ICMP = 162,
G_FCMP = 163,
G_SCMP = 164,
G_UCMP = 165,
G_SELECT = 166,
G_UADDO = 167,
G_UADDE = 168,
G_USUBO = 169,
G_USUBE = 170,
G_SADDO = 171,
G_SADDE = 172,
G_SSUBO = 173,
G_SSUBE = 174,
G_UMULO = 175,
G_SMULO = 176,
G_UMULH = 177,
G_SMULH = 178,
G_UADDSAT = 179,
G_SADDSAT = 180,
G_USUBSAT = 181,
G_SSUBSAT = 182,
G_USHLSAT = 183,
G_SSHLSAT = 184,
G_SMULFIX = 185,
G_UMULFIX = 186,
G_SMULFIXSAT = 187,
G_UMULFIXSAT = 188,
G_SDIVFIX = 189,
G_UDIVFIX = 190,
G_SDIVFIXSAT = 191,
G_UDIVFIXSAT = 192,
G_FADD = 193,
G_FSUB = 194,
G_FMUL = 195,
G_FMA = 196,
G_FMAD = 197,
G_FDIV = 198,
G_FREM = 199,
G_FMODF = 200,
G_FPOW = 201,
G_FPOWI = 202,
G_FEXP = 203,
G_FEXP2 = 204,
G_FEXP10 = 205,
G_FLOG = 206,
G_FLOG2 = 207,
G_FLOG10 = 208,
G_FLDEXP = 209,
G_FFREXP = 210,
G_FNEG = 211,
G_FPEXT = 212,
G_FPTRUNC = 213,
G_FPTOSI = 214,
G_FPTOUI = 215,
G_SITOFP = 216,
G_UITOFP = 217,
G_FPTOSI_SAT = 218,
G_FPTOUI_SAT = 219,
G_FABS = 220,
G_FCOPYSIGN = 221,
G_IS_FPCLASS = 222,
G_FCANONICALIZE = 223,
G_FMINNUM = 224,
G_FMAXNUM = 225,
G_FMINNUM_IEEE = 226,
G_FMAXNUM_IEEE = 227,
G_FMINIMUM = 228,
G_FMAXIMUM = 229,
G_FMINIMUMNUM = 230,
G_FMAXIMUMNUM = 231,
G_GET_FPENV = 232,
G_SET_FPENV = 233,
G_RESET_FPENV = 234,
G_GET_FPMODE = 235,
G_SET_FPMODE = 236,
G_RESET_FPMODE = 237,
G_GET_ROUNDING = 238,
G_SET_ROUNDING = 239,
G_PTR_ADD = 240,
G_PTRMASK = 241,
G_SMIN = 242,
G_SMAX = 243,
G_UMIN = 244,
G_UMAX = 245,
G_ABS = 246,
G_LROUND = 247,
G_LLROUND = 248,
G_BR = 249,
G_BRJT = 250,
G_VSCALE = 251,
G_INSERT_SUBVECTOR = 252,
G_EXTRACT_SUBVECTOR = 253,
G_INSERT_VECTOR_ELT = 254,
G_EXTRACT_VECTOR_ELT = 255,
G_SHUFFLE_VECTOR = 256,
G_SPLAT_VECTOR = 257,
G_STEP_VECTOR = 258,
G_VECTOR_COMPRESS = 259,
G_CTTZ = 260,
G_CTTZ_ZERO_POISON = 261,
G_CTLZ = 262,
G_CTLZ_ZERO_POISON = 263,
G_CTLS = 264,
G_CTPOP = 265,
G_BSWAP = 266,
G_BITREVERSE = 267,
G_CLMUL = 268,
G_FCEIL = 269,
G_FCOS = 270,
G_FSIN = 271,
G_FSINCOS = 272,
G_FTAN = 273,
G_FACOS = 274,
G_FASIN = 275,
G_FATAN = 276,
G_FATAN2 = 277,
G_FCOSH = 278,
G_FSINH = 279,
G_FTANH = 280,
G_FSQRT = 281,
G_FFLOOR = 282,
G_FRINT = 283,
G_FNEARBYINT = 284,
G_ADDRSPACE_CAST = 285,
G_BLOCK_ADDR = 286,
G_JUMP_TABLE = 287,
G_DYN_STACKALLOC = 288,
G_STACKSAVE = 289,
G_STACKRESTORE = 290,
G_STRICT_FADD = 291,
G_STRICT_FSUB = 292,
G_STRICT_FMUL = 293,
G_STRICT_FDIV = 294,
G_STRICT_FREM = 295,
G_STRICT_FMA = 296,
G_STRICT_FSQRT = 297,
G_STRICT_FLDEXP = 298,
G_STRICT_FCMP = 299,
G_STRICT_FCMPS = 300,
G_READ_REGISTER = 301,
G_WRITE_REGISTER = 302,
G_MEMCPY = 303,
G_MEMCPY_INLINE = 304,
G_MEMMOVE = 305,
G_MEMSET = 306,
G_BZERO = 307,
G_MEMSET_INLINE = 308,
G_TRAP = 309,
G_DEBUGTRAP = 310,
G_UBSANTRAP = 311,
G_VECREDUCE_SEQ_FADD = 312,
G_VECREDUCE_SEQ_FMUL = 313,
G_VECREDUCE_FADD = 314,
G_VECREDUCE_FMUL = 315,
G_VECREDUCE_FMAX = 316,
G_VECREDUCE_FMIN = 317,
G_VECREDUCE_FMAXIMUM = 318,
G_VECREDUCE_FMINIMUM = 319,
G_VECREDUCE_ADD = 320,
G_VECREDUCE_MUL = 321,
G_VECREDUCE_AND = 322,
G_VECREDUCE_OR = 323,
G_VECREDUCE_XOR = 324,
G_VECREDUCE_SMAX = 325,
G_VECREDUCE_SMIN = 326,
G_VECREDUCE_UMAX = 327,
G_VECREDUCE_UMIN = 328,
G_SBFX = 329,
G_UBFX = 330,
ADJCALLSTACKDOWN = 331,
ADJCALLSTACKUP = 332,
FI_ri = 333,
LDIMM64 = 334,
LOAD_STACK_ARG_PSEUDO = 335,
MEMCPY = 336,
STORE_STACK_ARG_IMM_PSEUDO = 337,
STORE_STACK_ARG_PSEUDO = 338,
Select = 339,
Select_32 = 340,
Select_32_64 = 341,
Select_64_32 = 342,
Select_Ri = 343,
Select_Ri_32 = 344,
Select_Ri_32_64 = 345,
Select_Ri_64_32 = 346,
ADDR_SPACE_CAST = 347,
ADD_ri = 348,
ADD_ri_32 = 349,
ADD_rr = 350,
ADD_rr_32 = 351,
AND_ri = 352,
AND_ri_32 = 353,
AND_rr = 354,
AND_rr_32 = 355,
BE16 = 356,
BE32 = 357,
BE64 = 358,
BSWAP16 = 359,
BSWAP32 = 360,
BSWAP64 = 361,
CMPXCHGD = 362,
CMPXCHGW32 = 363,
CORE_LD32 = 364,
CORE_LD64 = 365,
CORE_SHIFT = 366,
CORE_ST = 367,
DIV_ri = 368,
DIV_ri_32 = 369,
DIV_rr = 370,
DIV_rr_32 = 371,
JAL = 372,
JALX = 373,
JCOND = 374,
JEQ_ri = 375,
JEQ_ri_32 = 376,
JEQ_rr = 377,
JEQ_rr_32 = 378,
JMP = 379,
JMPL = 380,
JNE_ri = 381,
JNE_ri_32 = 382,
JNE_rr = 383,
JNE_rr_32 = 384,
JSET_ri = 385,
JSET_ri_32 = 386,
JSET_rr = 387,
JSET_rr_32 = 388,
JSGE_ri = 389,
JSGE_ri_32 = 390,
JSGE_rr = 391,
JSGE_rr_32 = 392,
JSGT_ri = 393,
JSGT_ri_32 = 394,
JSGT_rr = 395,
JSGT_rr_32 = 396,
JSLE_ri = 397,
JSLE_ri_32 = 398,
JSLE_rr = 399,
JSLE_rr_32 = 400,
JSLT_ri = 401,
JSLT_ri_32 = 402,
JSLT_rr = 403,
JSLT_rr_32 = 404,
JUGE_ri = 405,
JUGE_ri_32 = 406,
JUGE_rr = 407,
JUGE_rr_32 = 408,
JUGT_ri = 409,
JUGT_ri_32 = 410,
JUGT_rr = 411,
JUGT_rr_32 = 412,
JULE_ri = 413,
JULE_ri_32 = 414,
JULE_rr = 415,
JULE_rr_32 = 416,
JULT_ri = 417,
JULT_ri_32 = 418,
JULT_rr = 419,
JULT_rr_32 = 420,
JX = 421,
LDB = 422,
LDB32 = 423,
LDBACQ32 = 424,
LDBSX = 425,
LDD = 426,
LDDACQ = 427,
LDH = 428,
LDH32 = 429,
LDHACQ32 = 430,
LDHSX = 431,
LDW = 432,
LDW32 = 433,
LDWACQ32 = 434,
LDWSX = 435,
LD_ABS_B = 436,
LD_ABS_H = 437,
LD_ABS_W = 438,
LD_IND_B = 439,
LD_IND_H = 440,
LD_IND_W = 441,
LD_imm64 = 442,
LD_pseudo = 443,
LE16 = 444,
LE32 = 445,
LE64 = 446,
MOD_ri = 447,
MOD_ri_32 = 448,
MOD_rr = 449,
MOD_rr_32 = 450,
MOVSX_rr_16 = 451,
MOVSX_rr_32 = 452,
MOVSX_rr_32_16 = 453,
MOVSX_rr_32_8 = 454,
MOVSX_rr_8 = 455,
MOV_32_64 = 456,
MOV_ri = 457,
MOV_ri_32 = 458,
MOV_rr = 459,
MOV_rr_32 = 460,
MUL_ri = 461,
MUL_ri_32 = 462,
MUL_rr = 463,
MUL_rr_32 = 464,
NEG_32 = 465,
NEG_64 = 466,
NOP = 467,
OR_ri = 468,
OR_ri_32 = 469,
OR_rr = 470,
OR_rr_32 = 471,
RET = 472,
SDIV_ri = 473,
SDIV_ri_32 = 474,
SDIV_rr = 475,
SDIV_rr_32 = 476,
SLL_ri = 477,
SLL_ri_32 = 478,
SLL_rr = 479,
SLL_rr_32 = 480,
SMOD_ri = 481,
SMOD_ri_32 = 482,
SMOD_rr = 483,
SMOD_rr_32 = 484,
SRA_ri = 485,
SRA_ri_32 = 486,
SRA_rr = 487,
SRA_rr_32 = 488,
SRL_ri = 489,
SRL_ri_32 = 490,
SRL_rr = 491,
SRL_rr_32 = 492,
STB = 493,
STB32 = 494,
STBREL32 = 495,
STB_imm = 496,
STD = 497,
STDREL = 498,
STD_imm = 499,
STH = 500,
STH32 = 501,
STHREL32 = 502,
STH_imm = 503,
STW = 504,
STW32 = 505,
STWREL32 = 506,
STW_imm = 507,
SUB_ri = 508,
SUB_ri_32 = 509,
SUB_rr = 510,
SUB_rr_32 = 511,
XADDD = 512,
XADDW = 513,
XADDW32 = 514,
XANDD = 515,
XANDW32 = 516,
XCHGD = 517,
XCHGW32 = 518,
XFADDD = 519,
XFADDW32 = 520,
XFANDD = 521,
XFANDW32 = 522,
XFORD = 523,
XFORW32 = 524,
XFXORD = 525,
XFXORW32 = 526,
XORD = 527,
XORW32 = 528,
XOR_ri = 529,
XOR_ri_32 = 530,
XOR_rr = 531,
XOR_rr_32 = 532,
XXORD = 533,
XXORW32 = 534,
INSTRUCTION_LIST_END = 535,
};
}
include/LIEF/asm/mips/opcodes.hpp
+2823 -2820
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include/LIEF/asm/powerpc/opcodes.hpp
+2804 -2798
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include/LIEF/asm/riscv/opcodes.hpp
+16783 -16121
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include/LIEF/asm/riscv/registers.hpp
+689 -572
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include/LIEF/asm/x86/opcodes.hpp
+22330 -22195
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